DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/06/2025 has been entered.
Response to Remarks/Arguments
With respect to the rejection of claim 21 under 35 USC 112(a), Applicant’s arguments filed 10/06/2025 have been fully considered but are moot in view of new ground rejection set forth herein as necessitated by Applicant's amendments.
With respect to the rejection of claim 21-35 under 35 USC 112(b), Applicant’s arguments filed 10/06/2025 have been fully considered but are moot in view of new ground rejection set forth herein as necessitated by Applicant's amendments.
With respect to the rejection of claim 21-23, 26, 31, 32, and 35-39 under 35 USC 102(a)(1), Applicant’s arguments filed 10/06/2025 have been fully considered but are moot in view of new ground rejection set forth herein as necessitated by Applicant's amendments.
With respect to the rejection of claim 21, 22, 36 under 35 USC 102(a)(1), Applicant’s arguments filed 10/06/2025 have been fully considered but are moot in view of new ground rejection set forth herein as necessitated by Applicant's amendments.
With respect to the rejection of claim 27-29 under 35 USC 103, Applicant’s arguments filed 10/06/2025 have been fully considered but are moot in view of new ground rejection set forth herein as necessitated by Applicant's amendments.
Claim Objections
Claim 41 is objected to because of the following informalities: claim 41 claims “(Fig. 2, 225). [valuable information]”. It appears this limitation is not part of the claim but was included inadvertently. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-38 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 21, the claim claims a limitation “a classical Josephson junction circuit”. Applicant provided Figs. 1A, 2, and paragraphs [0018]-[0033], and Figs. 6A-6B, paragraph [0103] as the support for the term. However, none of the support positively describes what “classical Josephson junction circuit” is. The specification as filed discusses “non-quantum” electronics as “classical” electronics (see para. [0006]). However, “classical Josephson junction circuit” is not positively described or defined in the specification.
Regarding claim 21, the claim claims “all the information” that is stored in a first stage can be moved to a second stage and “all the information” can be moved from the second stage to the first stage, the information comprising bits. Applicant provided Figs. 1A, 2 and 6, and paragraphs [0018]-[0060], [0080], [0081] and [0100]-[0118] as the support for the amendment. Figs. 1 and 2 describe information is exchanged among the stages 1, 2 and 3 in a general manner. However, none of the figures or paragraphs specifically describe “all the information” is exchanged among the stages or between two stages and the information comprising bits (emphasis added).
Regarding claims 22-35, the claims 22-35 are rejected due to their dependencies to claim 21 above.
Regarding claim 36, the claim claims limitations, “a Josephson junction circuit configured to contain a bit” and “the bit can be moved from the Josephson junction circuit to the transistor circuit, after which the transistor circuit contains the bit”. The specification as filed does not positively discuss or disclose the limitations and Applicant did not provide the support for the amendment.
Regarding claims 37-38, the claims 37-38 are rejected due to their dependencies to claim 36 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 21, the claim claims a limitation “a classical Josephson junction circuit”. The specification as filed discusses “non-quantum” electronics as “classical” electronics (see para. [0006]). However, “classical Josephson junction circuit” is not described in the specification as filed. Applicant provided Figs. 1A, 2, and paragraphs [0018]-[0033], [0080], and Fig. 6A-6B, [0099]-[0104] as the support for the amendment. However, none of the support positively describes what “classical Josephson junction circuit” is. Therefore, it is vague and unclear what “classical Josephson junction circuit” means, and thus renders the claim indefinite. For the examination on the merit, “classical Josephson junction circuit” will read “Josephson junction circuit”.
Regarding claim 21, the claim claims “all the information” that is stored in a first stage can be moved to a second stage and “all the information” can be moved from the second stage to the first stage, the information comprising bits. Applicant provided Figs. 1A, 2 and 6, and paragraphs [0018]-[0060], [0080], [0081] and [0100]-[0118] as the support for the amendment. Figs. 1 and 2 describe information is exchanged among the stages 1, 2 and 3 in a general manner. However, none of the figures or paragraphs specifically describe “all the information” is exchanged among the stages or between two stages and the information comprising bits (emphasis added). Therefore, it is vague and unclear what “all the information” and “information comprising bits” mean as recited in the claim, and thus render the claim indefinite. For the examination on the merit, “all the information” will read “information” without the term “information comprising bits”.
Regarding claims 22-35, the claims 22-25 are rejected due to their dependencies to claim 21 above.
Regarding claim 27, Claim 27 recites the limitation "the josephson junction circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Regarding claims 28-30, claim 28-30 are rejected due to their dependencies to claim 27 above.
Regarding claim 36, the claim claims limitations, “a Josephson junction circuit configured to contain a bit” and “the bit can be moved from the Josephson junction circuit to the transistor circuit, after which the transistor circuit contains the bit”. The specification as filed does not positively discuss or disclose the limitations and Applicant did not provide the support for the amendment. Therefore, it is vague and unclear what “a Josephson junction circuit configured to contain a bit” means and “the bit can be moved from the Josephson junction circuit to the transistor circuit, after which the transistor circuit contains the bit” as recited in the claim, and thus render the claim indefinite.
Regarding claims 37-38, the claims 37-38 are rejected due to their dependencies to claim 36 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23, 26 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rigetti (US 2016/0267032 A1).
Regarding claim 21, Rigetti teaches a system comprising:
a second stage (Fig. 23A, QPC assembly 2346, [0269] a quantum processor cell (QPC) assembly 2346) comprising a Josephson junction circuit configured to contain information ([0284] QPC assembly shown and described with respect to Figs. 1-22, [0077] superconducting quantum circuits based on Josephson junctions);
a first stage comprising a transistor circuit comprising logic and cells that store the information ([0046] the control system 110 includes one or more classical computers, a control system shown in Figs. 23A-23B and 24-28);
wherein all the information can be moved from the first stage to the second stage and all the information can be moved from the second stage to the first stage (Fig. 23A, information moving between 2301 and 2331).
Regarding claim 22, all the limitations of claim 21 are taught by Rigetti.
Rigetti further teaches the system further comprising:
a qubit-containing payload (Fig. 23A, 2346, [0269] a quantum processor cell (QPC) assembly 2346, [0284] QPC assembly houses the qubit devices), wherein the information is transferred to the payload (Fig. 23A, information moving between 2301 and 2331).
Regarding claim 23, all the limitations of claim 21 are taught by Rigetti.
Rigetti further teaches the system further comprising: an external processor ([0266] control interface 2305) connected to the transistor circuit (control interface 230 signal processor system 2310), the external processor configured in a room temperature environment (Fig. 23A, 2301 room temp), wherein the external processor can load and update the information in the transistor circuit ([0266] 2305 where the information can be processed).
Regarding claim 26, all the limitations of claim 22 are taught by Rigetti.
Rigetti further teaches the system further comprising: a multiplexer associated with the transistor circuit, wherein information in the transistor circuit can be moved with different access rates ([0264] multiplexed control signal).
Regarding claim 31, all the limitations of claim 22 are taught by Rigetti.
Rigetti further teaches the system further comprising:
a second Josephson junction circuit (Fig. 23A, QPC Assembly 2346);
a microwave carrier transmission line configured as an input to the second Josephson junction circuit (Fig. 23A, Microwave signal generator 2304 – 2306 – 2335, [0270] input channels 2335);
a modulated signal transmission line configured as an output of the second Josephson junction circuit ([0270] output signals through 2350, Fig. 23A), wherein the second Josephson junction circuit modulates information on the microwave carrier transmission line to yield information on the modulated signal transmission line based on the information, and wherein a modulated signal is transferred to a qubit (QPC assembly 2346).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti (US 2016/0267032 A1) in view of Dickinson (US 5,521,538 A1).
Regarding claim 24, all the limitations of claim 21 are taught by Rigetti.
Rigetti does not explicitly teach the system, wherein the transistor circuit comprises an adiabatic circuit.
Dickinson teaches a system wherein a transistor circuit comprises an adiabatic circuit (Figs. 1 and 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the adiabatic circuit of Dickinson to the teachings of Rigetti in order to save power (Dickinson, Background).
Regarding claim 25, all the limitations of claim 21 are taught by Rigetti in view of Dickinson.
Rigetti in view of Dickinson further teaches the system, further comprising: at least one clock and power supply (Dickinson, Fig. 1) configured in a room temperature environment (Rigetti, Fig. 23A, 2301), wherein the at least one clock and power supply is operably connected to the transistor circuit , wherein both power and time synchronization are provided to the transistor circuit (Dickinson, Fig. 1).
Claims 27 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti (US 2016/0267032 A1) in view of Pedram (US 2019/0296743 A1).
Regarding claim 27, all the limitations of claim 21 are taught by Rigetti.
Rigetti does not explicitly teach the system, wherein the Josephson junction circuit comprises configurable logic, wherein the configurable logic is configured by the information.
Regarding claim 32, all the limitations of claim 22 are taught by Rigetti.
Rigetti does not explicitly teach the system, wherein the Josephson junction circuit is configured as a single-flux quantum (SFQ) circuit.
Pedram teaches a system wherein a Josephson junction circuit is configured as a single-flux quantum (SFQ) circuit ([0007] a new and complete SFQ FPGA design).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the SQF circuit of Pedram to the teachings of Rigetti in order to achieve higher area efficiency (Pedram, [0007]).
Claims 41-42 are rejected under 35 U.S.C. 103 as being unpatentable over Hornibrook (J.M. Hornibrook et. al., “Cryogenic Control Architecture for Large-Scale Quantum Computing”, Physical Review Applied, vol. 3, no. 2, February 23, 2015) in view of Biamonte (US 2011/0054876 A1).
Regarding claim 41, Hornibrook teaches a system comprising:
a circuit configured in a cryogenic environment (Fig. 2, Qubits, Switch matrix, Multiplexors in 20mK area);
an external processor (Fig. 2, PC in 300K area) connected to the adiabatic circuit, the external processor configured in a room temperature environment (Fig. 2, PC in 300K area), wherein the external processor can load and update control signal values stored in the adiabatic circuit (Fig. 2, provides Addressline, Biasing to Switch matrix and Qubits);
at least one clock and power supply configured in a room temperature environment (Fig. 2, Clock and Power in 300K area), wherein the at least one clock and power supply is operably connected to the adiabatic circuit (connected via Logic in 4K area), wherein both power and time synchronization are provided to the adiabatic circuit (page 024101-3, left column, lines 1-3 located in close proximity to qubits);
wherein the output of the adiabatic circuit produces output (Fig. 2, Readout).
However, Hornibrook does not explicitly teach the circuit is an adiabatic circuit.
Biamonte teaches adiabatic quantum computation approach wherein long qubit coherence times are not required ([0010]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the adiabatic quantum computation of Biamonte to the qubit circuit of Hornibrook in order to avoid long qubit coherence time (Biamonte [0010]).
Regarding claim 42, all the limitations of claim 41 are taught by Hornibrook in view of Biamonte.
Hornibrook further teaches the system further comprising:
at least one capacitive node connected to an output of the adiabatic circuit thereby producing an AC/DC cryogenic control signal (page 024010-4, right column, 2nd paragraph, The switch is capacitively coupled to the input and output ports, Fig. 2, switch matrix output to Qubits); and
a semiconductor FET wherein the control signal connects to a gate of the semiconductor FET (Fig. 2 switch matrix, page 024010-5, right column, section E. Cryogenic logic, 2nd paragraph, CMOS-based FPGA or ASIC operating at 4 K).
Allowable Subject Matter
Claims 33-35 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) and 35 U.S.C 112(b), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 33, the prior arts fail to teach or reasonably a suggest system further comprising: at least one transistor, wherein a leakage current of the at least one transistor is rebalanced for cryogenic operation, in combination with the other limitations of the claim.
Regarding claim 34, the prior arts fail to teach or reasonably a suggest system wherein the transistor circuit comprises a tapped adiabatic SRAM, wherein information in the SRAM is transferred to the payload via taps, in combination with the other limitations of the claim.
Regarding claim 35, the prior arts fail to teach or reasonably a suggest system comprising: a semiconductor FET that either passes or blocks an SFQ pulse based on the information, in combination with the other limitations of the claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844