DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 22 June 2026 has been entered. The amendments to the claims have overcome the 35 USC 112(b) rejections. Claims 26-49 remain pending.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the method 80 returning to block 88 after selecting values for M and Z at block 90 as described in the specification on pg. 11 lines 26-27. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the recitation of “non-transitory” in claim 38-43 lacks antecedent basis from the specification. Examiner suggests amending the specification to include “non-transitory” in the description of the computer readable storage medium.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26, 30, 32, 36, 38, 42, 44, and 48 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210201124 A1 Gelashvili (hereinafter “Gelashvili”).
Regarding claim 26, Gelashvili teaches a computing system comprising:
a network controller (Gelashvili, Fig. 2 and ¶ [0082]); and
a processor coupled to the network controller (Gelashvili, Fig. 2 element 105 and ¶ [0076]), wherein the processor includes a cache (Gelashvili, Fig. 2 element 110 and/or elements 107 including cache) and logic to:
determine a ratio of floating point instructions to memory read instructions (Gelashvili, ¶ [0011], [0065], and [0114]), and
control a dimension size of a matrix kernel based at least in part on the ratio (Gelashvili, ¶ [0014], [0065], and [0114] requirement 2 at [0116]).
Claim 32 recites a semiconductor apparatus comprising one or more substrates and logic to perform the functions of the computing system of claim 26. Gelashvili teaches a processor as an integrated circuit (Gelashvili, Fig. 2 element 105 and ¶ [0078]), which inherently comprises a semiconductor device comprising one or more substrates. Therefore, claim 32 is rejected for at least the same reason(s) as claim 26.
Claim 38 recites a computer readable storage medium comprising a set of executable program instructions which when executed cause a computing system to perform the functions of the computing system of claim 26. Gelashvili teaches storage media storing computer executable instructions executable by a processor to carry out the function of the computer system of claim 26 (Gelashvili, ¶ [0083]). Therefore, claim 38 is rejected for at least the same reason(s) as claim 26.
Claim 44 recites a method which performs the functions of the computing system of claim 26, and is therefore rejected for at least the same reason(s).
Regarding claim 30, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelashvili further teaches:
wherein the dimension size is controlled further based on a hardware constraint (Gelashvili, ¶ [0121]) and a latency constraint (Gelashvili, ¶ [0011] and [0114]).
Claims 36, 42, and 48 recite similar limitations to those recited in claim 30 and are therefore rejected for at least the same reason(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27, 29, 33, 35, 39, 41, 45, and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili, in view of M. Kretz “SIMD Types Example: Matrix Multiplication”, N4454, Programming Language C++ Library Working Group, April 10, 2015 (hereinafter “Kretz”).
Regarding claim 27, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelahsvili further teaches:
wherein the kernel matrix is to conduct an operation between a first matrix and a second matrix (Gelashvili, ¶ [0103]).
Gelashvili does not explicitly teach:
wherein the logic
However, Kretz teaches:
wherein the logic (Kretz, pg. 3 ¶ 2-3 and eqn. 2).
Gelashvili and Kretz are both considered to be analogous to the claimed invention because they are in the same field of computer implemented matrix multiplication. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the kernel matrix multiplication as taught by Gelashvili to include the reuse of elements for multiple vector lines as taught by Kretz. This modification would have been obvious because the vectorization method of Kretz leads to efficient SIMD vector loads and stores (Kretz, pg. 3 ¶ 3).
Claims 33, 39, and 45 recite similar limitations to those recited in claim 27 and are therefore rejected for at least the same reason(s).
Regarding claim 29, the combination of Gelashvili in view of Kretz teaches the invention substantially as claimed. See the rejection of claim 27 above. Gelashvili further teaches:
wherein the operation is one of a multiplication operation or a convolution operation (Gelashvili, ¶ [0103]).
Claims 35, 41, and 47 recite similar limitations to those recited in claim 29 and are therefore rejected for at least the same reason(s).
Claims 28, 34, 40, and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili, in view of Kretz, further in view of US 20160259728 A1 Eddy et al. (hereinafter “Eddy”).
Regarding claim 28, the combination of Gelashvili in view of Kretz teaches the invention substantially as claimed. See the rejection of claim 27 above. Neither Gelashvili nor Kretz explicitly teaches:
wherein the cache is a set-associative cache, and wherein the logic is to:
detect an overflow condition, wherein the overflow condition includes a portion of the first matrix exceeding a number of ways in the set-associative cache; and
conduct an inline copy of the portion in response to the overflow condition.
However, Eddy teaches:
wherein the cache is a set-associative cache, and wherein the logic is to:
detect an overflow condition, wherein the overflow condition includes a portion of (Eddy, ¶ [0043]); and
conduct an inline copy of the portion in response to the overflow condition (Eddy, Fig. 4 and ¶ [0039], [0048]).
Eddy is considered to be analogous to the claimed invention because it is in the same field of cache memory storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing system as taught by Gelashvili in view of Kretz to include the overflow cache as taught by Eddy. This modification would have been obvious because the use of an overflow cache improves performance and cache memory utilization (Eddy, ¶ [0022]).
Claims 34, 40, and 46 recite similar limitations to those recited in claim 28 and are therefore rejected for at least the same reason(s).
Claims 31, 37, 43, and 49 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili in view of Hong, C. et al. “Effective padding of multidimensional arrays to avoid cache conflict misses”. ACM SIGPLAN Notices, 51(6), 129-144. July 1, 2016. (hereinafter “Hong”).
Regarding claim 31, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelashvili does not explicitly teach:
wherein the dimension size is controlled to prevent a conflict in the cache.
However, Hong teaches:
wherein the dimension size is controlled to prevent a conflict in the cache (Hong, Abstract and § 3.2).
Hong is considered to be analogous to the claimed invention because it is in the same field of cache memory storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing system with cache memory storage as taught by Gelashvili to implement the padding method to avoid cache conflicts as taught by Hong. This modification would have been obvious because array padding is a well-known technique for optimizing performance by reducing cache conflict misses (Hong, Abstract and § I. Introduction, ¶ 1).
Claims 37, 43, and 49 recite similar limitations to those recited in claim 28 and are therefore rejected for at least the same reason(s).
Response to Arguments
Drawings. Applicant asserts that, an arrow in a method description is not "structural." Moreover, as noted in the objection, the MPEP uses the language "should" (as does the CFR) which hortatory, not mandatory (see Remarks p. 6 ¶3).
Examiner respectfully disagrees. Figure 6 solely illustrates a flowchart of the claimed method. Structural is meant to refer to the structure of the flowchart, rather than a tangible structure of a circuit, as an example. Further, 37 CFR 1.83(a) recites “should be illustrated in the drawing in the form of a graphical drawing symbol or a labeled representation (e.g. a labeled rectangular box)” which further evidences that such changes do not stringently preclude things that are not structure-related in the sense of the circuit example, but rather features of the overall invention.
Moreover, the specification recites on p. 11 ln. 24-29:
“A determination may then be made at block 88 as to whether the value of Z is acceptable for task balancing (e.g., between available cores). If not, other (e.g., "sub-optimum") values are selected at block 90 for parameters M and Z, and the method 80 returns to block 88. Once it is determined at block 88 that the value of Z is acceptable for task balancing, block 92 may set the kernel parameters to the values of M and Z.”
However, Fig. 6 (a portion depicted below) appears not to contain the feature “the method 80 returns to block 88.” It appears that such returning function is critical for ensuring task balancing.
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35 USC 101. The claim amendments have overcome the previous rejections.
35 USC 112(b). The claim amendments have overcome the previous rejections.
35 USC 102. Applicant asserts the following in substance:
Applicant asserts that, the cited reference fails to disclose, teach, or suggest logic to determine a ratio of floating point instructions to memory read instructions. The Examiner alleges that Gelashvili teaches this limitation, citing paragraphs [0011], [0065], and [0114]. However, a review of Gelashvili reveals that it does not evaluate executable instructions. Instead, Gelashvili discloses calculating a "compute-to-memory ratio (CMR)," which is defined as the "number of compute operations that one must perform per item brought into a given memory level," and an "Arithmetic intensity (Al)," which is defined as "the number of compute operations per byte of data" (Gelashvili, paragraph [0011]) (see Remarks p. 7 ¶4).
Examiner respectfully disagrees. The limitation “executable instructions” appears to be recited only in claims 38-43 and the claim mapping can be found on p. 4-5 of this action and on p. 5 of the Non-Final Action filed 03/19/2026. Gelashvili discloses in [0083] computer-executable instructions which when executed by a processor or controller, carry out the methods disclosed.
Applicant asserts that, calculating a ratio of abstract mathematical operations to bytes or items of data is fundamentally different from determining a ratio of executable processor instructions. Modern processors utilize Single Instruction, Multiple Data (SIMD) or vector instructions that perform multiple floating-point operations per single instruction, as well as vector load instructions that read many bytes of data per single memory read instruction. Because Gelashvili evaluates theoretical compute operations per byte of data specifically estimating theoretical "FLOPS" versus the "amount of memory that is streamed" (Gelashvili, paragraph [0122])-the cited reference fails to disclose, teach, or suggest determining a ratio of actual "floating point instructions" to "memory read instructions" as required by the claims (see Remarks p. 8 ¶1).
Examiner respectfully disagrees. Applicant appears to be referring to an uncited portion of Gelashvili that was not relied upon in the prior art rejection, [0012]. Gelashvili discloses in [0012] how compute utilization measures a theoretical maximum of a given algorithm. Note, “theoretical” is used to qualify the absolute greatest value measurable of utilization rather than used to describe whether computer operations are actually happening or not. “Theoretical” is used more so to describe the concept of a limit/boundary of the utilization because in practice other factors such as implementation, algorithm, and other design changes may influence the theoretical utilization in contrast to the actual utilization. This paragraph merely serves as a means of providing context of how memory accesses affect performance when.
Applicant asserts that, the cited reference fails to disclose, teach, or suggest logic to determine this ratio during system operation to control a dimension size. Gelashvili explicitly performs its theoretical evaluations offline during a "planning phase" (Gelashvili, paragraph [0119]) to select parameters, rather than utilizing computing system logic or executable instructions to determine a ratio of floating point instructions to memory read instructions. Consequently, Gelashvili also fails to teach controlling a dimension size of a matrix kernel based at least in part on the claimed ratio (see Remarks p. 8 ¶3).
Examiner respectfully disagrees. Gelashvili discloses in Fig. 2 a block diagram of an exemplary computing device which may be used with embodiments of the invention ([0076]). The computing device of Fig. 2 contains a processor that includes a cache ([0076] “110” and/or “107”) and logic ([0076] code) to perform the determining ([0011], [0065], [0114]) and controlling ([0014], [0065], [0114]) functionalities. Gelashvili discloses in [0065] how the embodiments described may use data partitioning and task partitioning.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
