DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the method 80 returning to block 88 after selecting values for M and Z at block 90 as described in the specification on pg. 11 lines 26-27. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 27-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 27 recites the limitation "wherein the logic coupled to the one or more substrates is to reuse…" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. There is no previous mention of one or more substrates in claim 27 or claim 26 on which it depends. For the purposes of prior art examination it is assumed the claim reads “wherein the logic is to reuse…”.
Claims 28-29 are rejected for their dependence on claim 27.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 38-43 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims are directed to transitory forms of signal transmission, i.e. signals per se. The broadest reasonable interpretation of computer readable storage media encompasses signals per se (see In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007)). Nowhere in the claims or in the accompanying specification is the definition of computer readable storage media limited to non-transitory media, and therefore the claims are not patent eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26, 30, 32, 36, 38, 42, 44, and 48 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gelashvili (US 20210201124 A1).
Regarding claim 26, Gelashvili teaches a computing system comprising:
a network controller (Gelashvili, Fig. 2 and ¶ [0082]); and
a processor coupled to the network controller (Gelashvili, Fig. 2 element 105 and ¶ [0076]), wherein the processor includes a cache (Gelashvili, Fig. 2 element 110 and/or elements 107 including cache) and logic to:
determine a ratio of floating point instructions to memory read instructions (Gelashvili, ¶ [0011], [0065], and [0114]), and
control a dimension size of a matrix kernel based at least in part on the ratio (Gelashvili, ¶ [0014], [0065], and [0114] requirement 2 at [0116]).
Claim 32 recites a semiconductor apparatus comprising one or more substrates and logic to perform the functions of the computing system of claim 26. Gelashvili teaches a processor as an integrated circuit (Gelashvili, Fig. 2 element 105 and ¶ [0078]), which inherently comprises a semiconductor device comprising one or more substrates. Therefore, claim 32 is rejected for at least the same reason(s) as claim 26.
Claim 38 recites a computer readable storage medium comprising a set of executable program instructions which when executed cause a computing system to perform the functions of the computing system of claim 26. Gelashvili teaches storage media storing computer executable instructions executable by a processor to carry out the function of the computer system of claim 26 (Gelashvili, ¶ [0083]). Therefore, claim 38 is rejected for at least the same reason(s) as claim 26.
Claim 44 recites a method which performs the functions of the computing system of claim 26, and is therefore rejected for at least the same reason(s).
Regarding claim 30, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelashvili further teaches:
wherein the dimension size is controlled further based on a hardware constraint (Gelashvili, ¶ [0121]) and a latency constraint (Gelashvili, ¶ [0011] and [0114]).
Claims 36, 42, and 48 recite similar limitations to those recited in claim 30 and are therefore rejected for at least the same reason(s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27, 29, 33, 35, 39, 41, 45, and 47 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili, in view of Kretz (“SIMD Types Example: Matrix Multiplication”, 2015).
Regarding claim 27, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelahsvili further teaches:
wherein the kernel matrix is to conduct an operation between a first matrix and a second matrix (Gelashvili, ¶ [0103]).
Gelashvili does not explicitly teach:
wherein the logic
However, Kretz teaches:
wherein the logic (Kretz, pg. 3 ¶ 2-3 and eqn. 2).
Gelashvili and Kretz are both considered to be analogous to the claimed invention because they are in the same field of computer implemented matrix multiplication. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the kernel matrix multiplication as taught by Gelashvili to include the reuse of elements for multiple vector lines as taught by Kretz. This modification would have been obvious because the vectorization method of Kretz leads to efficient SIMD vector loads and stores (Kretz, pg. 3 ¶ 3).
Claims 33, 39, and 45 recite similar limitations to those recited in claim 27 and are therefore rejected for at least the same reason(s).
Regarding claim 29, the combination of Gelashvili in view of Kretz teaches the invention substantially as claimed. See the rejection of claim 27 above. Gelashvili further teaches:
wherein the operation is one of a multiplication operation or a convolution operation (Gelashvili, ¶ [0103]).
Claims 35, 41, and 47 recite similar limitations to those recited in claim 29 and are therefore rejected for at least the same reason(s).
Claims 28, 34, 40, and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili, in view of Kretz, further in view of Eddy et al. (US 20160259728 A1), hereinafter Eddy.
Regarding claim 28, the combination of Gelashvili in view of Kretz teaches the invention substantially as claimed. See the rejection of claim 27 above. Neither Gelashvili nor Kretz explicitly teaches:
wherein the cache is a set-associative cache, and wherein the logic is to:
detect an overflow condition, wherein the overflow condition includes a portion of the first matrix exceeding a number of ways in the set-associative cache; and
conduct an inline copy of the portion in response to the overflow condition.
However, Eddy teaches:
wherein the cache is a set-associative cache, and wherein the logic is to:
detect an overflow condition, wherein the overflow condition includes a portion of (Eddy, ¶ [0043]); and
conduct an inline copy of the portion in response to the overflow condition (Eddy, Fig. 4 and ¶ [0039], [0048]).
Eddy is considered to be analogous to the claimed invention because it is in the same field of cache memory storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing system as taught by Gelashvili in view of Kretz to include the overflow cache as taught by Eddy. This modification would have been obvious because the use of an overflow cache improves performance and cache memory utilization (Eddy, ¶ [0022]).
Claims 34, 40, and 46 recite similar limitations to those recited in claim 28 and are therefore rejected for at least the same reason(s).
Claims 31, 37, 43, and 49 are rejected under 35 U.S.C. 103 as being unpatentable over Gelashvili in view of Hong et al. (“Effective padding of multidimensional arrays to avoid cache conflict misses”, 2016), hereinafter Hong.
Regarding claim 31, Gelashvili teaches the invention substantially as claimed. See the rejection of claim 26 above. Gelashvili does not explicitly teach:
wherein the dimension size is controlled to prevent a conflict in the cache.
However, Hong teaches:
wherein the dimension size is controlled to prevent a conflict in the cache (Hong, Abstract and § 3.2).
Hong is considered to be analogous to the claimed invention because it is in the same field of cache memory storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing system with cache memory storage as taught by Gelashvili to implement the padding method to avoid cache conflicts as taught by Hong. This modification would have been obvious because array padding is a well-known technique for optimizing performance by reducing cache conflict misses (Hong, Abstract and § I. Introduction, ¶ 1).
Claims 37, 43, and 49 recite similar limitations to those recited in claim 28 and are therefore rejected for at least the same reason(s).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN DAVID WARNER whose telephone number is (703)756-5956. The examiner can normally be reached M-F: 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.D.W./
Jonathan David WarnerExaminer, Art Unit 2182
(703) 756-5956
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182