DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on an identical interpretation of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 1, Applicant’s arguments (Applicant’s Remarks pages 9-12) accurately observe that as presented in previous office actions, claimed elements are interpreted in view of the disclosure of US 20180337226 A1 (Liu et al) as follows: at least one first power signal lead (FIG. 7, second power fan-out line 520), at least one second power signal lead (FIG. 7, portion of first power fan-out line 510 excluding the left “stem” which overlaps layer 121) and the power connecting bus (FIG. 7, portion of the “left stem” of first power fan-out line 510 which overlaps layer 121). Under the previously presented interpretation, Liu does not read on the newly-added limitations of claim 1, specifically “an extending direction of a length of the power connecting bus is parallel to an extending direction of a length of a part of the at least one retaining wall, the two second power signal leads are arranged at two ends of the power connecting bus respectively, and an extending direction of a length of each of the two second power signal leads is perpendicular to the extending direction of the length of the power connecting bus; the at least one aperture is respectively disposed in the at least one first power signal lead, the two second power signal leads and the power connecting bus”.
However, the previously presented interpretation is not the only broadly-reasonable interpretation of the prior art. For example, if considering the power connecting bus to be a narrow band in the Liu FIG. 7 embodiment which covers a middle “row” of three illustrated apertures on the left stem of power fan-out line 510, and the two second power signal leads are segments of the left stem of power fan-out line 510 which overlap the upper and lower “rows” of three illustrated apertures in the Liu FIG. 7 embodiment, and extend lengthwise along a vertical direction (an annotated version of Liu FIG. 7 which illustrates this interpretation is provided in the rejections under 35 U.S.C. 103 below), the disclosure of Liu teaches the newly-claimed limitations of claim 1 (see rejections under 35 U.S.C. 103 below for additional details).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20180337226 A1 (Liu et al hereinafter Liu) in view of US 20200381653 A1 (Bang et al hereinafter Bang).
Regarding claim 1, Liu discloses a display panel (the display panel of FIGS. 7-8, ¶ [0018]), comprising: a substrate (FIG. 7, substrate 100, ¶ [0027]), comprising a display region (FIG. 7, display region 110, ¶ [0027]) and a non-display region (FIG. 7, step region 120, ¶ [0027]) disposed on an outer periphery of the display region (FIG. 7, the step region is on the outer periphery of the display region); a light-emitting device (FIG. 7, one of the non-drawn display pixels in the display region 110, ¶ [0072]) and a packaging layer (FIG. 8, sealant 800 and insulating layer IN2, ¶ [0082, 0053]), disposed on the substrate (FIG. 8, sealant 800 and IN2 are both disposed above substrate 100); and at least one retaining wall (FIG. 7, encapsulating region 121, ¶ [0077]) and a signal trace (FIG. 7, power supply fan-out line 500, ¶ [0047]), disposed on a side of the packaging layer proximate to the substrate (FIG. 8, fan-out line 510, a portion of fan-out line 500, is between sealant 800/layer IN2 and substrate 100);
wherein the light-emitting device is disposed within the display region (the pixels are located in the display region, ¶ [0032]), the at least one retaining wall and the signal trace are disposed within the non-display region (FIG. 7, encapsulating region 121 and fan-out line 500 are both located in step region 120), and the signal trace is electrically connected to the light-emitting device (fan-out line 500’s portion 520 connects to second power line 320, which connects to metal interconnection layer 600, which connects to the light-emitting device’s cathode ¶ [0047-0051]) and is provided with at least one aperture (FIGS. 7-8, fan-out line 500 comprises through holes 530, ¶ [0055-0057]), wherein an orthographic projection of the at least one aperture on the substrate is disposed within an orthographic projection of the at least one retaining wall on the substrate (FIG. 7, orthographic projections of through holes 530 overlap the orthographic projection of encapsulating region 121 in the direction toward the substrate);
wherein the signal trace comprises at least one first power signal lead (FIG. 7, second power fan-out line 520, which connects to second power line 320 ¶ [0047-0051]), two second power signal leads (FIG. 7, portions of the left “stem” of first power fan-out line 510 excluding a band of the left “stem” which includes the “middle row” of three of the illustrated apertures, specifically the regions directly above and below the central band, respectively represent two second power signal leads ¶ [0039]; see annotated FIG. 7 below for additional clarification) and a power connecting bus (FIG. 7, a band of the left “stem” of fan-out line 510 which includes the “middle row” of three of the illustrated apertures can be interpreted to constitute a power connecting bus) wherein an extending direction of a length of the power connecting bus (FIG. 7, the length of the bus portion of the left “stem” of first power fan-out line 510 which overlaps layer 121 extends along a horizontal direction) is parallel to an extending direction of a length of a part of the at least one retaining wall (FIG. 7, layer 121 extends lengthwise along the same horizontal direction, and is therefore parallel), the two second power signal leads are arranged at two ends of the power connecting bus respectively (annotated FIG. 7 below, the upper and lower ends of the bus portion of the left “stem” of first power fan-out line 510 have the two second power signal leads respectively arranged at them), and an extending direction of a length of each of the two second power signal leads is perpendicular to the extending direction of the length of the power connecting bus (annotated FIG. 7 below, the two second power signal leads have a vertical extension direction, which is perpendicular to the horizontal extension direction of the bus portion of fan-out line 510);
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the at least one aperture is respectively disposed in the at least one first power signal lead, the two second power signal leads and the power connecting bus (annotated FIG. 7, through holes 530 are disposed in second power fan-out line 520, the portion of first power fan-out line 510 including the “middle row” of three of the illustrated apertures in the left “stem” which overlaps layer 121, that portion being the bus portion, and the portion of the left “stem” of first power fan-out line 510 which includes the “upper and lower” rows of three of the illustrated apertures in the left “stem”, those being the two second power signal leads); an orthographic projection of the at least one first power signal lead on the substrate comprises a first overlap region with the orthographic projection of the at least one retaining wall on the substrate (FIG. 7, second power fan-out line 520’s projection has an overlap region over layer 121), an orthographic projection of each of the two second power signal leads on the substrate comprises a second overlap region with the orthographic projection of the at least one retaining wall on the substrate (annotated FIG. 7 above, portion of first power fan-out line 510 which includes the “upper and lower” rows of three of the illustrated apertures in the left “stem” overlaps layer 121), and an orthographic projection of the power connecting bus on the substrate comprises a third overlap region with the orthographic projection of the at least one retaining wall on the substrate (annotated FIG. 7, portion of the left “stem” of first power fan-out line 510 which includes the “middle row” of three illustrated aperture has an overlap region over layer 121); and the orthographic projection of the at least one aperture on the substrate is respectively disposed within the first overlap region, the second overlap region and the third overlap region (FIG. 7, through holes 530 are located in each of the three aforementioned overlap regions).
Liu does not disclose that each of the at least one retaining wall comprises at least two organic insulating layers that are laminated, and the display panel further comprises a third conductive layer between two adjacent organic insulating layers in the at least one retaining wall, and the third conductive layer comprises the signal trace. The conductive signal trace of Liu (FIG. 8, first power fan-out line portion 510) is located between two adjacent insulating layers (FIG. 8, IN2 and IN5), but Liu does not specify that those insulating layers are also organic layers. Consequently, Liu also does not disclose that the at least one retaining wall comprises a first retaining wall and a second retaining wall, and at least two organic insulating layers in the first retaining wall comprise a first organic insulating layer, a second organic insulating layer and a pixel defining layer that are laminated; and wherein the third conductive layer is disposed between the first organic insulating layer and the second organic insulating layer, and the orthographic projection of the at least one aperture on the substrate is within an orthographic projection of the first retaining wall on the substrate so as to release the moisture absorbed by the first organic insulating layer.
However, Bang discloses a display panel (the display panel of FIGS. 1, 3-7B, ¶ [0033-0040]) comprising at least one retaining wall (FIG. 5, dam portions 110, 120, and 130 and underlying layer 109, ¶ [0083]; consistent with applicant’s disclosure, a portion of the retaining wall may be disposed below a signal line) wherein each of the at least one retaining wall comprises at least two organic insulating layers that are laminated (FIG. 5, each of dam portions 110, 120, and 130 overlap at least organic planarization films 109 and 111, ¶ [0129, 0163-0166]), and the display panel further comprises a third conductive layer (FIG. 5, second power voltage supply line 20, ¶ [0074]) between two adjacent organic insulating layers in the at least one retaining wall (FIG. 5, power line 20 is between organic planarization films 109 and 111a, 111b, or 111c at each of the dam portions), wherein the third conductive layer comprises a signal trace (FIG. 5, second power voltage supply line 20 is a signal trace, ¶ [0074]). Bang also discloses that their configuration of retaining walls prevent an overflow of material when forming the encapsulation layer (¶ [0084]), which would reduce defects in the device.
Bang further discloses that the at least one retaining wall comprises a first retaining wall (Bang FIG. 5, first dam portion 110, ¶ [0083]) and a second retaining wall (Bang FIG. 5, third dam portion 130, ¶ [0083]), and at least two organic insulating layers in the first retaining wall comprise a first organic insulating layer (Bang FIG. 5, first planarization film 109, ¶ [0129]), a second organic insulating layer (Bang FIG. 5, first layer 111a, formed of same material as second planarization film 111, ¶ [0129, 0165]) and a pixel defining layer (Bang FIG. 5, second layer 113a, formed of same material as pixel defining layer 113, ¶ [0138, 0165]) that are laminated; and wherein the third conductive layer is disposed between the first organic insulating layer and the second organic insulating layer (Bang FIG. 5, power line 20 is between first organic insulating layer 109 and second organic insulating layer 111; as they are the same material as layer 111, layers 111a and 111c are considered part of the second organic insulating layer), and the orthographic projection of the at least one aperture on the substrate is within an orthographic projection of the first retaining wall on the substrate (Liu FIG. 7, the through-hole apertures 530 overlap the encapsulation 121; as the structures are analogous, power line 20 in relation to retaining walls 130 and 110 of Bang has the apertures 530 of Liu disposed in positions that overlap both retaining walls 130 and 110) so as to release the moisture absorbed by the first organic insulating layer (since the combined structure of Liu in view of Bang comprises the organic layers of Bang contacting the apertures of Liu, it naturally follows that some amount of moisture is released through the apertures due to their structure).
Liu and Bang both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the retaining wall of Liu to employ the configuration and layering of the retaining walls of Bang such that each of the at least one retaining wall comprises at least two organic insulating layers that are laminated, and the display panel further comprises a third conductive layer between two adjacent organic insulating layers in the at least one retaining wall, and the third conductive layer comprises the signal trace, in order to prevent an overflow of material when forming the device and reduce manufacturing defects. In so doing, the device of Liu in view of Bang further comprises that the at least one retaining wall comprises a first retaining wall and a second retaining wall, and at least two organic insulating layers in the first retaining wall comprise a first organic insulating layer, a second organic insulating layer and a pixel defining layer that are laminated; and wherein the third conductive layer is disposed between the first organic insulating layer and the second organic insulating layer, and the orthographic projection of the at least one aperture on the substrate is within an orthographic projection of the first retaining wall on the substrate so as to release the moisture absorbed by the first organic insulating layer.
Regarding claim 14, Liu in view of Bang discloses the limitations of claim 1 as detailed above, and Liu further discloses that the power connecting bus (FIG. 7, portion of “left stem” of first power fan-out line 510 that overlaps the illustrated “middle row” of three apertures) is electrically connected to the two second power signal leads (FIG. 7, the bus portion of line 510 electrically connects to the non-bus portions of line 510; the portions directly above and below the bus portion are respectively the two second power signal leads).
Regarding claim 18, Liu in view of Bang discloses the limitations of claim 1 as detailed above, and they further disclose that the second retaining wall is proximate to the display region relative to the first retaining wall (Bang FIGS. 1 and 5, third dam portion 130 is closer to the display area DA than first dam portion 110); and at least two organic insulating layers in the second retaining wall comprise the second organic insulating layer (Bang FIG. 5, first layer 111c, formed of same material as second planarization film 111, ¶ [0129, 0163]) and the pixel defining layer (Bang FIG. 5, second layer 113c, formed of same material as pixel defining layer 113, ¶ [0138, 0163]) that are laminated.
Regarding claim 19, Liu in view of Bang discloses the display panel as defined in claim 1 (refer back to the rejection of claim 1 above), and they further disclose a method for manufacturing a display panel, wherein the display panel is the display panel as defined in claim 1, the method comprising: providing the substrate (Liu FIG. 7, substrate 100 is provided, ¶ [0027]), wherein the substrate comprises the display region (Liu FIG. 7, display region 110, ¶ [0027]) and the non-display region disposed on an outer periphery of the display region (Liu FIG. 7, the step region is on the outer periphery of the display region); and forming the light-emitting device (Liu FIG. 7, one of the non-drawn display pixels in the display region is formed, ¶ [0072]), the packaging layer (Liu FIG. 8, sealant 800 and insulating layer IN2 are formed, ¶ [0082, 0053]), at least one retaining wall (Liu FIG. 7, encapsulating region 121, ¶ [0077]), and the signal trace on the substrate (Liu FIG. 8, fan-out line 510, a portion of fan-out line 500, is between sealant 800 and substrate 100).
Regarding claim 20, Liu in view of Bang discloses a display device, comprising: the display panel as defined in claim 1 (as detailed regarding claim 1 above) and a driving chip (Liu FIG. 7, bonding region 122 is used to bond a driving chip to the display panel, ¶ [0030]); wherein the driving chip is electrically connected to the signal trace in the display panel (Liu FIG. 7, bonding region 122 connects the chip with first power fan-out line 510 of the signal trace 500, ¶ [0030, 0049]).
Claims 3-6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Bang as applied to claim 1 above, and further in view of US patent publication US 20200301535 A1 (Choi et al hereinafter Choi).
Regarding claim 3, Liu in view of Bang discloses or suggests the limitations of claim 1 as detailed above, but does not disclose a touch unit and at least one touch signal lead, disposed on a side of the packaging layer distal from the substrate, wherein the at least one touch signal lead is connected to the touch unit; wherein the touch unit is disposed within the display region, the at least one touch signal lead is disposed within the non-display region, and an orthographic projection of the at least one touch signal lead on the substrate is at least partially within the orthographic projection of the at least one first power signal lead on the substrate and is not overlapped with the orthographic projection of the at least one aperture on the substrate.
However, Choi discloses a touch unit (Choi FIGS. 1A-3, any of touch sensing electrodes e.g. IE1 or IE2, ¶ [0075, 0114-0119]) and at least one touch signal lead (Choi FIGS. 1A-3, touch sensing lines TSL/TSL1/TSL2, particularly TSL1, ¶ [0063-0064, 0075, 0114-0119]), disposed on a side of a packaging layer (FIG. 2, encapsulation layer TFE, ¶ [0061, 0075]) distal from a substrate (FIG. 2, touch electrodes IE1/IE2 have layer TFE between themselves and substrate SUB, ¶ [0052]; the touch sensing lines may extend onto side and upper surfaces of TFE when they connect to the touch electrodes ¶ [0063, 0114]), wherein the touch signal lead is connected to the touch unit (¶ [0063, 0114]);
wherein the touch unit is disposed within the display region (FIG. 2, touch electrodes IE1/IE2 are in display region DA ¶ [0075]), the at least one touch signal lead is disposed within the non-display region (FIGS. 1A/3, touch signal lead TSL1 is in non-display peripheral regions PA1, PA2), and an orthographic projection of the at least one touch signal lead on the substrate is at least partially within an orthographic projection of a first power signal lead on the substrate (FIG. 3, several touch sensing lines TSL overlap first power line PL1, ¶ [0130]).
Liu, Bang, and Choi all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have it obvious to modify the device of Liu in view of Bang further in view of Choi to include the touch-sensing elements of Choi, including a touch unit and at least one touch signal lead, disposed on a side of the packaging layer distal from the substrate, wherein the at least one touch signal lead is connected to the touch unit; wherein the touch unit is disposed within the display region, the at least one touch signal lead is disposed within the non-display region, and an orthographic projection of the at least one touch signal lead on the substrate is at least partially within an orthographic projection of the at least one first power signal lead on the substrate, in order to add touch-sensing functionality to the device, which allows a user to input information by touching an image in the display region of the device (Choi ¶ [0004]).
Choi does not disclose that an orthographic projection of the at least one touch signal lead is not overlapped with the orthographic projection of the at least one aperture on the substrate, since the disclosure of Choi does not disclose apertures in the power signal lead. However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have an orthographic projection of the touch signal lead is not overlapped with the orthographic projection of the aperture on the substrate in view of the disclosure of Liu, because in the process of making the device of Liu the sealant is designed to extend into the apertures to release stress during a laser-treatment (Liu ¶ [0057, 0084-0085]). Disposing touch signal leads such that they do not overlap the apertures would prevent interference in that stress-releasing process since they would not block the sealant from extending into the apertures, for the same reason that data lines 200 are intentionally arranged to not overlap the portions of the power lines comprising the apertures (Liu, ¶ [0004-0005]). In addition, even if some of the touch signal lines could arguably overlap some apertures in the device, due to the array nature of the configurations each of the touch signal lines and apertures, it would be obvious that there exists at least one touch signal line that does not overlap at least one aperture.
Regarding claim 4, Liu in view of Bang and Choi discloses or suggests the limitations of claim 3 as detailed above, and they further disclose that the at least one touch signal lead comprises a plurality of touch signal leads (Choi FIGS. 1 and 3, several touch sensing lines TSL/TSL1/TSL2 are arranged; some of them overlap first power line PL1, ¶ [0130]). They do not explicitly state that the at least one aperture is arranged between at least two adjacent touch signal leads of the plurality of touch signal leads.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have such a feature, because Liu FIG. 7 shows a plurality of through hole apertures 530 are disposed in power supply fan-out line 500, Choi FIG. 3 shows a plurality of touch signal leads TSL overlap the power line PL1, and it was established in the section regarding claim 3 above that the modified combination of Liu in view of Bang and Choi holds that the touch signal leads do not overlap an aperture to avoid interfering with the stress-releasing feature of the apertures in the power line. In order to arrange sufficient touch signal lines to enable touch-sensing functionality while at the same time not overlapping the apertures, a person of ordinary skill in the art before the effective filing date of the claimed invention would therefore have found it obvious to have at least one aperture is arranged between at least two adjacent touch signal leads of the plurality of touch signal leads, in order to make effective use of space to enable touch-sensing functionality while avoiding interfering with the stress-releasing feature.
Regarding claim 5, Liu in view of Bang and Choi discloses or suggests the limitations of claim 4 as detailed above, and they further disclose that the at least one aperture comprises a plurality of apertures (Liu FIG. 7, there is a plurality of through holes 530) and the plurality of apertures are arranged in the first power signal lead (Liu FIG. 7, a plurality of through holes 530 are arranged in power fan-out line 520, the first power signal lead). They do not explicitly state that the at least one aperture is arranged between any two adjacent touch signal leads of the plurality of touch signal leads.
However, for similar reasons as described regarding claim 4, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to have such a feature, because Liu FIG. 7 shows a plurality of through holes 530 are disposed in power fan-out line 520, Choi FIG. 3 shows a plurality of touch signal leads TSL overlap the power line PL1, and it was established in the section regarding claim 3 above that the modified combination of Liu in view of Bang and Choi holds that the touch signal leads do not overlap an aperture to avoid interfering with the stress-releasing feature of the apertures in the power line. In order to arrange sufficient touch signal lines to enable touch-sensing functionality while at the same time not overlapping the apertures, a person of ordinary skill in the art before the effective filing date of the claimed invention would therefore have found it obvious to have at least one said aperture is arranged between any two adjacent touch signal leads of the plurality of apertures, in order to make effective use of space to enable touch-sensing functionality while avoiding interfering with the stress-releasing feature.
Regarding claim 6, Liu in view of Bang and Choi discloses or suggests the limitations of claim 5 as detailed above, but they do not explicitly disclose that a distance between any two adjacent touch signal leads is greater than a width each of the plurality of apertures, and a width direction of each of the plurality of apertures is perpendicular to an extending direction of the touch signal lead. Widths of apertures and distances between touch signal leads were not parameters of particular relevance to the disclosure of their inventions.
However, it would be obvious to have a distance between any two adjacent touch signal leads is greater than a width of each of the plurality of apertures, and a width direction of each of the plurality of apertures is perpendicular to an extending direction of the touch signal lead (e.g. compare the distance between touch signal leads TSL1 and TSL2 in FIG. 1A of Choi to the width of apertures 530 in FIG. 7 of Liu), so that sufficient space is provided between the two adjacent touch signal leads to avoid their overlapping an aperture, as discussed regarding claims 3-5, to avoid interfering with the stress-releasing feature of the apertures of Liu.
Regarding claim 13, Liu in view of Bang and Choi discloses or suggests the limitations of claim 3 as detailed above, and they further disclose a touch signal line configured to connect the touch unit and the touch signal lead (Choi, a small non-shown portion of the touch sensing lines TSL1/TSL2 which connect the touch unit IE1/IE2 may constitute a touch signal line ¶ [0063, 0114]; portions of touch signal lead portions of TSL1/TSL2 are still disposed in the display area).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Bang and Choi as applied to claim 5 above, and further in view of US patent publication US 20220102468 A1 (Lee et al hereinafter Lee).
Liu in view of Bang and Choi discloses or suggests the limitations of claim 5 as detailed above, and they further disclose two first power signal leads (Liu FIG. 7, two power fan-out lines 510 are arranged); the plurality of the touch signal leads are divided into two groups of touch signal leads (Choi FIGS. 1A and 3, the touch sensing lines TLS/TSL1/TSL2 can be arbitrarily divided into groups of touch signal leads). As described regarding claim 5 they do not state that the two first power signal leads correspond to the two groups of touch signal leads one by one, an orthographic projection of each group of the touch signal leads on the substrate is at least partially within an orthographic projection of a corresponding first power signal lead on the substrate, and wherein the at least one first power signal lead comprises the two first power signal leads.
However, Choi further teaches that the touch sensing lines are not required to all be disposed over a single power line PL1 (¶ [0130-0131]), and suggests that some touch sensing lines may be disposed over a second power line PL2, and/or that others may be formed at positions not overlapping the power lines. Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to dispose two groups of touch signal leads such that the two first power signal leads correspond to the two groups of touch signal leads one by one, and an orthographic projection of each group of the touch signal leads on the substrate is at least partially within an orthographic projection of a corresponding first power signal lead on the substrate to provide adequate spacing among the total plurality of touch signal leads to avoid signal crosstalk between them; to do so would also be to use an obvious design alternative suggested by the prior art.
Liu in view of Bang and Choi do not teach that the at least one first power signal lead comprises the two first power signal leads. However, Lee discloses a display panel (the display panel shown in display device 10 of FIG. 1, ¶ [0031]) wherein two second power signal leads are arranged (FIG. 1, two second wires 52 connect to driving voltage supply line 30, ¶ [0079]), wherein the two second power signal leads are disposed between two first power signal leads (FIG. 1, two fourth wires 54 connect to common voltage supply line 40, which connects to the cathode of the OLED ¶ [0078-0079]; second wires 52 are between fourth wires 54). Further, an increased number of power signal leads would reduce the total current in each lead, reducing the chance of defects arising from sustained performance, and the configuration of the two second power signal leads being between the two first power signal leads is a matter of obvious design choice demonstrated as viable by the prior art.
Liu, Bang, Choi, and Lee pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Liu in view of Bang and Choi further in view of Lee such that two first power signal leads are arranged, and the two second power signal leads are disposed between the two first power signal leads, and wherein each one of the two first power signal leads comprises the properties of the first power signal lead as defined in claim 1, in order to reduce the chance of defects arising from sustained performance, and because such a configuration is presented as an obvious design alternative. By doing so, the at least one first power signal lead comprises the two first power signal leads.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Bang, Choi, and Lee as applied to claim 7 above, and further in view of US patent publication US 20180095581 A1 (Hwang et al hereinafter Hwang).
Regarding claim 8, Liu in view of Bang, Choi, and Lee disclose the limitations of claim 7 as detailed above, and further disclose that one of the two groups of the touch signal leads comprises a plurality of first touch signal leads successively arranged (Choi FIG. 3, the group of touch signal leads TSL disposed on power line PL1, ¶ [0130-0131]), and other one of the two groups of the touch signal leads comprises a plurality of second touch signal leads successively arranged (Choi FIG. 3, the group of touch signal leads TSL disposed on power line PL2, in the non-shown variation suggested in ¶ [0131]). They do not further disclose that the touch unit comprises a touch sensing electrode and a touch driving electrode, insulated from each other, wherein the first touch signal lead is connected to the touch sensing electrode, and the second touch signal lead is connected to the touch driving electrode. Details regarding a distinction between touch sensing electrodes and touch driving electrodes were not discussed in the disclosure of Choi.
However, Hwang discloses a display device (the display device shown in FIGS. 1-5, ¶ [0029-0033]), wherein a touch unit (FIGS. 1-2, a unit including one of touch driving electrode TE1 and touch sensing electrode TE2) comprises a touch sensing electrode (FIG. 2, touch sensing electrode TE2, ¶ [0091]) and a touch driving electrode (FIG. 2, touch driving electrode TE1, ¶ [0087]), insulated from each other (FIG. 2, touch insulation layer 511 insulates the sensing and driving electrodes, ¶ [0094]), wherein the first touch signal lead is connected to the touch sensing electrode (FIG. 2, a touch signal lead from second routing lines RL2 connects to touch sensing electrode TE2, ¶ [0097]), and the second touch signal lead is connected to the touch driving electrode (FIG. 2, a touch signal lead of first routing lines RL1 connects to touch driving electrode TE1, ¶ [0090]). Hwang also teaches that their arrangement of touch sensing and touch driving electrodes allows for sensing both touch position and touch force based on a user’s touch (¶ [0087, 0097]), and that their touch sensing and touch driving electrodes are arranged in an interlocking pattern wherein the touch sensing and touch driving electrodes have a same shape (¶ [0093]), allowing for effective coverage of the display area.
Liu, Bang, Choi, Lee, and Hwang all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Liu in view of Bang, Choi, and Lee further in view of Hwang, such that the touch unit comprises a touch sensing electrode and a touch driving electrode, insulated from each other, wherein the first touch signal lead is connected to the touch sensing electrode, and the second touch signal lead is connected to the touch driving electrode, so that the touch sensing and touch driving electrodes could sense both touch position and touch force while having effective coverage of the display area. Additionally, adopting such a configuration would be an obvious design alternative based on what is taught by the prior art.
Regarding claim 9, Liu in view of Bang, Choi, Lee, and Hwang disclose the limitations of claim 8 as detailed above, and they further disclose that the touch signal lead comprises a first sub-lead (Choi FIGS. 1A-4A, touch sensing line TSL1 includes a portion not positioned on the encapsulation layer TFE, represented in part by TSL in FIGS. 3-4A ¶ [0063-0064, 0075, 0114-0119]) and a second sub-lead electrically connected to the first sub-lead (Choi, the touch sensing lines, including TSL1, connect to the touch electrodes in the display area on the encapsulation layer TFE ¶ [0063-0064, 0114]; the portion of the touch sensing line in the display area on the encapsulation layer TFE, as well as the portion between layer TFE and the portion on a lower layer, is the second sub-lead), wherein the first sub-lead and the second sub-lead are disposed on different layers (the second sub-lead is disposed layer TFE, while the first sub-lead is disposed on, for example, layer INS4, FIG. 4A, ¶ [0114]).
Regarding claim 10, Liu in view of Bang, Choi, Lee, and Hwang disclose the limitations of claim 9 as detailed above, and they further disclose that an orthographic projection of the first sub-lead on the substrate is overlapped with an orthographic projection of the second sub-lead on the substrate (orthogonal projections of the second sub-lead and the first sub-lead overlap each other at the interface where the first sub lead ends and the second sub-lead begins, because it is a point where the touch sensing line TSL changes vertical position to move onto the encapsulation layer TFE, Choi ¶ [0114]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Bang, Choi, Lee, and Hwang as applied to claim 9 above, and further in view of US patent publication US 20200019294 A1 (Lee et al hereinafter “Lee 2”).
Regarding claim 11, Liu in view of Bang, Choi, Lee, and Hwang disclose the limitations of claim 9 as detailed above and further disclose a second conductive layer disposed on the packaging layer (Choi FIG. 2, conductive layer comprising IE1/IE2 is disposed on encapsulation TFE, ¶ [0115]; also Hwang FIG. 1, where touch electrode TE1/TE2 are disposed on encapsulation 300, ¶ [0098]); wherein the second conductive layer comprises the second sub-lead, the touch sensing electrode and the touch driving electrode (Hwang FIGS. 1-2, touch driving electrode TE1, touch sensing electrode TE2, and the second sub-lead portion of the touch signal lead that connects to the touch unit on the same layer as the touch electrodes, per Choi ¶ [0063, 0114], are located in the same second conductive layer). Liu in view of Bang, Choi, Lee, and Hwang do not further disclose a first conductive layer, an insulating layer, and the second conductive layer that are disposed on the packaging layer and laminated in a direction perpendicular to and distal from the packaging layer; wherein the first conductive layer comprises the first sub-lead.
However, Lee 2 discloses a display device (the display device of FIGS. 1-7B, ¶ [0011-0019]) comprising a first conductive layer (FIGS. 5A-7B, the conductive layer disposed on encapsulation layer 146 comprising first bridges 152b, via connection electrodes 168, and auxiliary lines 174, ¶ [0039, 0049, 0058]), an insulating layer (FIGS. 5A-7B, touch dielectric film 156, ¶ [0040]), and a second conductive layer (FIGS. 5A-7B, the conductive layer disposed over touch dielectric 156 comprising first touch electrodes 152e, second touch electrodes 154e, first sensing-routing lines 164, and second routing-sensing lines 166, ¶ [0039-0047]) that are disposed on a packaging layer and laminated in a direction perpendicular to and distal from the packaging layer (FIGS. 5A-7B, the layers are laminated in the direction above the encapsulation unit 140, ¶ [0023]); wherein the first conductive layer comprises a first sub-lead (FIG. 7B, auxiliary line 174, ¶ [0058-0060]). Lee 2 also teaches that the inclusion of the auxiliary lines can reduce the line resistance of the first sensing-routing lines (¶ [0060]).
Liu, Bang, Choi, Lee, Hwang, and Lee 2 all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Liu in view of Bang, Choi, Lee, and Hwang further in view of Lee 2 such that it comprises a first conductive layer, an insulating layer, and the second conductive layer that are disposed on the packaging layer and laminated in a direction perpendicular to and distal from the packaging layer; wherein the first conductive layer comprises the first sub-lead (the auxiliary line 174 of Lee 2 may be considered a portion of the first sub-lead), in order to reduce the line resistance in the sensing-routing lines of the device. Such a configuration is also a known alternative in the art that could be achieved with ordinary means for a predictable result.
Regarding claim 12, Liu in view of Bang, Choi, Lee, Hwang, and Lee 2 disclose the limitations of claim 11 as detailed above, and they further disclose that a plurality of touch driving electrodes are arranged in a plurality of rows (Hwang FIG. 2, first touch electrodes TE1, driving electrodes, are arranged in rows, ¶ [0087]), the first conductive layer further comprises a plurality of connecting bridges (Lee 2 FIG. 5A, first bridges 152b are in the first conductive layer, ¶ [0039]; see also Hwang FIG. 2, bridges TE2b); and a plurality of touch sensing electrodes are arranged in a plurality of columns (Hwang FIG. 2, second touch electrodes TE2, sensing electrodes, are arranged in columns, ¶ [0091]).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Bang as applied to claim 14 above, and further in view of Lee.
Regarding claim 15, Liu in view of Bang discloses the limitations of claim 14 as detailed above , but Liu does not disclose that the at least one first power signal lead comprises two first power signal leads, and the two second power signal leads are disposed between the two first power signal leads. The closest analogous feature to two first power signal leads wherein each one of the two first power signal leads comprises features of the first power signal lead as defined in claim 1 in Liu is the second power fan-out line 520 (Liu FIG. 7), but only one line 520 is shown.
However, Lee discloses a display panel (the display panel shown in display device 10 of FIG. 1, ¶ [0031]) wherein two second power signal leads are arranged (FIG. 1, two second wires 52 connect to driving voltage supply line 30, ¶ [0079]), wherein the two second power signal leads are disposed between two first power signal leads (FIG. 1, two fourth wires 54 connect to common voltage supply line 40, which connects to the cathode of the OLED ¶ [0078-0079]; second wires 52 are between fourth wires 54). Further, an increased number of power signal leads would reduce the total current in each lead, reducing the chance of defects arising from sustained performance, and the configuration of the two second power signal leads being between the two first power signal leads is a matter of obvious design choice demonstrated as viable by the prior art.
Liu, Bang, and Lee pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Liu in view of Bang further in view of Lee such that the at least one first power signal lead comprises two first power signal leads, and the two second power signal leads are disposed between the two first power signal leads, in order to reduce the chance of defects arising from sustained performance, and because such a configuration is presented as an obvious design alternative.
Regarding claim 16, Liu in view of Bang and Lee disclose the limitations of claim 15 as detailed above, and they further disclose that at least one the first power signal lead, the power connecting bus and the two second power signal leads are disposed on a same layer (Liu FIGS. 7-8, power signal leads/bus 510/520 are located on substrate 100, ¶ [0026-0029).
In addition, while Liu in view of Lee as described regarding claim 15 didn’t explicitly teach that the at least one first power signal lead, the power connecting bus and the at least one second power signal lead are made of a same material, Lee further teaches that all of the features of the wiring layer may be made of a same material (¶ [0123 or 0134], which includes second and fourth wires 52 and 54). A person of ordinary skill in the art before the effective filing date would have found it obvious to make the at least one first power signal lead, the power connecting bus and the at least one second power signal lead of a same material in order to simplify the manufacturing process of the device.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publication US 20250377744 A1.
Conclusion
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/E.R.C./Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813