Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 5-7, 11, and 12 have been amended. No claims have been added. Claims 4, 13, 16, and 19 have been cancelled. Claims 1-3, 5-12, 14, 15, 17, and 18 are currently pending for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/30/2025 has been entered.
Response to Arguments
As per the applicant’s arguments, pgs.10-11, regarding the rejection of the instant application under 35 USC 112, the examiner has considered these arguments in light of the current amendments. It is believed that the substitution of ‘apparatus’ or ‘device’ for objects purely reflecting functionality overcomes the Claim Interpretation and rejection under 35 USC 112(b), as no structure needs to be disclosed. As such, the Claim Interpretation and rejections under 35 USC 112(b) have been withdrawn.
As per the applicant’s arguments, pgs.11-15, regarding the rejection of the instant application under 35 USC 103, the examiner has considered the arguments. Specifically, regarding the claim that the combination of Degenaro in view Chen in further view of Swaminathan in further view of Yan does not disclose the limitations of the independent claim as amended, the examiner concedes. As such, the new grounds of rejection do not rely upon the previously cited prior art to disclose the amended limitations regarding the software and hardware configuration of the local stream acceleration device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Degenaro (US 20100058036 A1) in view of Chen (US 20180314521 A1) in further view of Mody (US 20200210351 A1) in further view of Kruglick (US 20150261550 A1) in further view of Yan (US 20190108043 A1).
As per claim 1, Degenaro discloses:
A local data stream acceleration method (“A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system.", abstract ; "These singleton services can be co-located on a single processing node or distributed among a collection of processing nodes in communication across one or more local or wide area networks.", 0024)
receiving a raw data stream collected by a data acquirer (“Additionally, acceleration devices are connected to both a source and a destination, usually a network, in order to both receive and transmit data streams.", 0022)
configuring a local data stream acceleration engine (“At least one virtual acceleration device definition capable of configuring an acceleration device in accordance with the computing system resources identified by the inquiry is identified, and at least one of the plurality of identified acceleration devices is configured in accordance with each identified virtual acceleration device definition. Each configured acceleration device is used to process the inquiry.", 0016 ; Examiner Note: an acceleration device equates to a data stream acceleration engine.)
inputting the preliminarily processed raw data stream into the data stream acceleration engine for acceleration processing, and obtaining a result of data stream acceleration processing; and outputting the result of data stream acceleration processing. (“In one embodiment, dynamically routing corresponding data includes configuring the acceleration device to receive packets across a network originating from one or more nodes within the computing system and configuring the acceleration device to produce packets across the network destined to one or more of the nodes.", 0015)
wherein the configuration of the data stream acceleration engine comprises software configuration and hardware configuration (“Suitable managed acceleration devices include FPGAs, Complex Programmable Logic Devices (CPLDs) and ASICs, all known in the art, and other similar hybrid devices which may incorporated features of each… A data stream acceleration device is attached to a general purpose computer directly, e.g., plugged in to an adapter on that computer's motherboard, or is connected via a network interface in order to interrogate and configure it.”, 0022 ; “A plurality of virtual acceleration device definitions is also identified. Each virtual acceleration device definition includes attributes that are used to configure at least one of the plurality of identified acceleration devices.”, 0016 ;)
wherein configuring a local data stream acceleration engine comprises: performing the software configuration and hardware configuration of the data stream acceleration engine (“These acceleration devices include a field programmable gate array, an application specific integrated circuit, a complex programmable logic device and combinations thereof. In one embodiment, the acceleration devices are dynamically detected, and computing system stream data are dynamically routed to and from each identified acceleration device. In one embodiment, dynamically routing corresponding data includes configuring the acceleration device to receive packets across a network originating from one or more nodes within the computing system and configuring the acceleration device to produce packets across the network destined to one or more of the nodes.”, 0015 ; “Virtualization is the ability of the system to allow applications to describe acceleration preferences and requirements abstractly, and for the system to match these user specifications with available acceleration resources, all during runtime.”, 0022 ; Examiner Note: dynamically changing the routing of an FPGA type device necessitates first generating a hardware reconfiguration instruction. Reading and matching user specifications regarding acceleration preferences equates to generating software configuration instructions according to the type of data stream.)
Degenaro discloses the above limitations of claim 1, but does not disclose the performing of preliminary processing upon the data stream.
However, Chen discloses:
performing preliminary processing on the raw data stream (“During operation, the media processor 1702 and vision processor 1704 can work in concert to accelerate computer vision operations. The media processor 1702 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 1705. The vision processor 1704 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation of processing the frames using a trained image recognition model.”, 0240)
The system of Degenaro in view of Chen would be capable of performing preliminary processing operations on a data stream before inputting it into the data stream accelerator. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Degenaro and Chen in order to provide a system which accelerates the processing of ‘intelligently’ preliminarily processed data streams (Chen, 0001), thereby increasing the overall speed and efficiency of the processing of streams.
Degenaro in view of Chen discloses the above limitations of claim 1, but does not disclose a software configuration instruction comprising structural parameters of the data stream acceleration engine.
However, Mody discloses:
generating, according to a type of the data stream, a corresponding software configuration instruction and a corresponding hardware configuration instruction, wherein the software configuration instruction comprises structural parameters of the data stream acceleration engine (“The depth of the circular buffer 332 is software configurable to accommodate the size and format of data transferred and transfer latency between the stream accelerator 204 and memory external to the VPAC 108. For example, configuration information provided to the stream accelerator 204 and the DMA controller 212 by the GPP 106 may set the depth of the circular buffer 332.”, 0035 ; “The depth of the circular buffer 334 is software configurable to accommodate the size and format of data transferred and transfer latency between external memory and the stream accelerator 206.”, 0036 ; Examiner Note: the configuration information provided to the stream accelerator equates to a software configuration instruction. The depth of the circular buffer equates to a structural parameter of the architecture of the data stream acceleration engine)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Degenaro in view of Chen with those of Mody in order to provide a method for data stream acceleration which optimizes the efficiency of both memory transfers and general acceleration processing (Mody, [0052]).
Degenaro in view of Chen in further view of Mody discloses the above limitations of claim 1, but does not disclose the hardware configuration instruction being used for allocating hardware resources required for the structure of the data stream acceleration engine.
However, Kruglick discloses:
the hardware configuration instruction is used for allocating hardware computing resources required for the structure of the data stream acceleration engine (“According to yet other examples, a computer readable medium may store instructions for integrating hardware accelerators in a datacenter. Example instructions may include receiving a customer accelerator block for a hardware accelerator configuration, retrieving the other accelerator block upon determining that the hardware accelerator configuration specifies another accelerator block, forming a hardware accelerator by integrating the customer accelerator block and the other accelerator block at the datacenter according to the hardware accelerator configuration”, 0008 ; Examiner Note : integrating hardware accelerators into the hardware accelerator equates to allocating hardware computing resources required for the structure of the data stream acceleration engine)
The system of Degenaro in view of Chen in further view of Mody in further view of Kruglick would provide a system capable of using a hardware configuration instruction to allocate hardware computing resources required for the data stream acceleration engine of Degenaro or Mody. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Degenaro in view of Chen in view of Mody with those of Kruglick in order to utilize a hardware configuration instruction to take advantage of additional accelerator devices while still maintaining hardware integration (Kruglick, [0003]).
Degenaro in view of Chen in further view of Mody in further view of Kruglick discloses the above limitations of claim 1, but does not disclose transmitting software or hardware configuration instructions via a control channel.
However, Yan discloses:
transmitting, via the control channel, the software configuration instruction and the hardware configuration instruction to perform the software configuration and the hardware configuration on the data stream acceleration engine (“In some embodiments, the apparatus may comprise a controller (e.g., power kernel and controller 270). The controller may be coupled to the interface and/or may be operable to transmit the configuration command set to the interface.”, 0084 ; Examiner Note: the controller interface equates to a control channel)
The system of Degenaro in view of Chen in further view of Mody in further view of Kruglick in further view of Yan would be capable of performing the software and hardware configuration instructions which were transmitted via a control channel. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the system of Degenaro in view of Chen in further view of Mody in further view of Kruglick with that of Yan in order to allow the system to communicate the desired configuration settings over a designated channel, enabling the administrator to operate the data stream acceleration engine in a separate location from, or different processor than the acceleration module.
As per claim 5, Degenaro discloses:
A local data stream acceleration device, comprising: a receiver configured to receive a raw data stream collected by a data acquirer (“A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system.", abstract ; "These singleton services can be co-located on a single processing node or distributed among a collection of processing nodes in communication across one or more local or wide area networks.", 0024 ; "Additionally, acceleration devices are connected to both a source and a destination, usually a network, in order to both receive and transmit data streams.", 0022 ; “The system receives a plurality of inquiries 108, from, for example, applications running on the system. These inquiries 108 result in resource requirements and preferences 107 that are communicated to the scheduler 104.”, 0031 ; Examiner Note: the scheduler which receives inquiries, as well as resulting requirements and preferences equate to a reception module.)
an acceleration configurator configured to configure a local data stream acceleration engine, input the preliminarily processed raw data stream into the data stream acceleration engine for acceleration processing, and obtain a result of data stream acceleration processing (see fig.1- block 111: dynamic FPGA configuration management module, or deployment agent ; “The deployment agent 111 reads the image url and writes the image to the configuration address and port of the appropriate acceleration device. At that point, the acceleration device is ready to process streaming data. Additional steps are undertaken before processing with the acceleration device commences.”, 0037; see fig.1- block 115: real time data flow router ; “Similarly, when the input source address is configurable, the dynamic router controller 112 is configured to signal the real time data flow router 115 to send packets to the specified input data-in addresses and ports.”, 0038 ; see fig.1- block 119: source processing elements ; “During runtime, the network of consumer processing elements 118 have their needs satisfied by the system through dynamic connections to system generated source processing elements 119, which are producing information of the desired types.”, 0040 ; “Certain processing elements may consume data produced by the data stream acceleration devices”, 0041; Examiner Note: the combination of elements 111, 115, and 119 within the system equates to the acceleration module)
an outputter configured to output the result of data stream acceleration processing. ("Additionally, acceleration devices are connected to both a source and a destination, usually a network, in order to both receive and transmit data streams.", 0022 ; see fig.1: block 118: PE networks ; “During runtime, the network of consumer processing elements 118 have their needs satisfied by the system through dynamic connections to system generated source processing elements 119, which are producing information of the desired types.”, 0040)
wherein the configuration of the data stream acceleration engine comprises software configuration and hardware configuration (“Suitable managed acceleration devices include FPGAs, Complex Programmable Logic Devices (CPLDs) and ASICs, all known in the art, and other similar hybrid devices which may incorporated features of each… A data stream acceleration device is attached to a general purpose computer directly, e.g., plugged in to an adapter on that computer's motherboard, or is connected via a network interface in order to interrogate and configure it.”, 0022 ; “A plurality of virtual acceleration device definitions is also identified. Each virtual acceleration device definition includes attributes that are used to configure at least one of the plurality of identified acceleration devices.”, 0016 ; Examiner Note: configuring an FPGA, CPLD, or ASIC equates to hardware configuration. Configuring a virtual acceleration device equates to software configuration)
Degenaro discloses the above functionality of claim 5, but does not disclose the performance of preliminary processing on the raw data stream.
However, Chen discloses:
perform preliminary processing on the raw data stream (“During operation, the media processor 1702 and vision processor 1704 can work in concert to accelerate computer vision operations. The media processor 1702 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 1705. The vision processor 1704 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation of processing the frames using a trained image recognition model”, 0240)
Degenaro in view of Chen discloses the above limitations of claim 5, but does not disclose a software configuration instruction comprising structural parameters of the data stream acceleration engine.
However, Mody discloses:
wherein the acceleration configurator is configured to: generate, according to a type of the data stream, a corresponding software configuration instruction and a corresponding hardware configuration instruction, wherein the software configuration instruction comprises structural parameters of the data stream acceleration engine (“The depth of the circular buffer 332 is software configurable to accommodate the size and format of data transferred and transfer latency between the stream accelerator 204 and memory external to the VPAC 108. For example, configuration information provided to the stream accelerator 204 and the DMA controller 212 by the GPP 106 may set the depth of the circular buffer 332.”, 0035 ; “The depth of the circular buffer 334 is software configurable to accommodate the size and format of data transferred and transfer latency between external memory and the stream accelerator 206.”, 0036 ; Examiner Note: the configuration information provided to the stream accelerator equates to a software configuration instruction. The depth of the circular buffer equates to a structural parameter of the architecture of the data stream acceleration engine)
Degenaro in view of Chen in further view of Mody discloses the above limitations of claim 5, but does not disclose the hardware configuration instruction being used for allocating hardware resources required for the structure of the data stream acceleration engine.
However, Kruglick discloses:
the hardware configuration instruction is used for allocating hardware computing resources required for the structure of the data stream acceleration engine (“According to yet other examples, a computer readable medium may store instructions for integrating hardware accelerators in a datacenter. Example instructions may include receiving a customer accelerator block for a hardware accelerator configuration, retrieving the other accelerator block upon determining that the hardware accelerator configuration specifies another accelerator block, forming a hardware accelerator by integrating the customer accelerator block and the other accelerator block at the datacenter according to the hardware accelerator configuration”, 0008 ; Examiner Note : integrating hardware accelerators into the hardware accelerator equates to allocating hardware computing resources required for the structure of the data stream acceleration engine)
The system of Degenaro in view of Chen in further view of Mody in further view of Kruglick would provide a system capable of using a hardware configuration instruction to allocate hardware computing resources required for the data stream acceleration engine of Degenaro or Mody. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Degenaro in view of Chen in view of Mody with those of Kruglick in order to utilize a hardware configuration instruction to take advantage of additional accelerator devices while still maintaining hardware integration (Kruglick, [0003]).
Degenaro in view of Chen in further view of Mody in further view of Kruglick discloses the above limitations of claim 5, but does not disclose transmitting software or hardware configuration instructions via a control channel.
However, Yan discloses:
transmit, via the control channel, the software configuration instruction and the hardware configuration instruction to perform the software configuration and the hardware configuration on the data stream acceleration engine (“In some embodiments, the apparatus may comprise a controller (e.g., power kernel and controller 270). The controller may be coupled to the interface and/or may be operable to transmit the configuration command set to the interface.”, 0084 ; Examiner Note: the controller interface equates to a control channel)
As per claim 6, Degenaro discloses:
A data stream acceleration system, comprising: a data acquirer configured to collect a data stream, a data memory configured to store the data stream collected by the data acquirer, (see fig.1: block 115 -real time data flow router ; “In one embodiment, the real time data flow router 115 includes a network packet IP router that can be configured in promiscuous mode to send packets both to their original destination, e.g., absent acceleration, and to the one or more configured additional destinations as specified by the dynamic router controller 115. In another embodiment, the packets are strictly redirected to the dynamic router controller 115 configured destinations only. With the completion of this step, streams of information are now flowing from raw streams shown as the workload generator component 116 comprising the real time data flow router 115 and its information supply (not shown), to the configured stream accelerator devices 113.”, 0039 ; Examiner Note: the real time data flow router both collects and stores the data streams which are to be routed to acceleration devices, thus equates to a combined data acquisition and data storage module.)
a data acceleration engine device configured to perform acceleration on the data stream (see fig.1: block 113- FPGAs 1-3 ; “streams of information are now flowing from raw streams shown as the workload generator component 116 comprising the real time data flow router 115 and its information supply (not shown), to the configured stream accelerator devices 113.”, 0039
and a main controller configured to control data acquisition, data storage and data acceleration. (see fig.1 ; Examiner Note: the “System-S Stream Accelerator Management” device equates to a main control module which performs data acquisition, storage, and acceleration)
wherein the main controller is configured to perform the following steps: configuring a local data stream acceleration engine, inputting preliminarily processed raw data stream into the data stream acceleration engine for acceleration processing, and obtaining a result of data stream acceleration processing (“In one embodiment, the data-in and data-out address and ports of the acceleration device are configured…For the configurable embodiments, the dispatcher communicates address and port information to the deployment agent 111 and to a dynamic router controller 112 as appropriate.”, 0038 ; Examiner Note: in the context of inputting a data stream and obtaining a result, the dispatcher functions as the main controller which manages the input of raw data and obtaining of results through the configuration of ports)
wherein the configuration of the data stream acceleration engine comprises software configuration and hardware configuration (“Suitable managed acceleration devices include FPGAs, Complex Programmable Logic Devices (CPLDs) and ASICs, all known in the art, and other similar hybrid devices which may incorporated features of each… A data stream acceleration device is attached to a general purpose computer directly, e.g., plugged in to an adapter on that computer's motherboard, or is connected via a network interface in order to interrogate and configure it.”, 0022 ; “A plurality of virtual acceleration device definitions is also identified. Each virtual acceleration device definition includes attributes that are used to configure at least one of the plurality of identified acceleration devices.”, 0016 ; Examiner Note: configuring an FPGA, CPLD, or ASIC equates to hardware configuration. Configuring a virtual acceleration device equates to software configuration)
Degenaro discloses the above functionality, but does not disclose the performance of preliminary processing.
However, Chen discloses:
perform preliminary processing on the raw data stream (“During operation, the media processor 1702 and vision processor 1704 can work in concert to accelerate computer vision operations. The media processor 1702 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 1705. The vision processor 1704 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation of processing the frames using a trained image recognition model”, 0240)
Degenaro in view of Chen discloses the above limitations of claim 6, but does not disclose the main controller configuring the stream engine.
However, Mody discloses:
wherein the main controller is configured to perform the following steps: configuring a local data stream acceleration engine, inputting preliminarily processed raw data stream into the data stream acceleration engine for acceleration processing, and obtaining a result of data stream acceleration processing; (“For example, configuration information provided to the stream accelerator 204 and the DMA controller 212 by the GPP 106 may set the depth of the circular buffer 332.”, 0035 ; Examiner Note: the GPP equates to the main controller)
the main controller is configured to: perform the software configuration and hardware configuration of the data stream acceleration engine (“For example, configuration information provided to the memory-to-memory accelerator 208 and the DMA controller 212 by the GPP 106 may set the depth of the circular buffer 350. “, 0039)
the main controller is configured to execute performing the software configuration and hardware configuration of the data stream acceleration engine by: generating, according to a type of the data stream, a corresponding software configuration instruction and a corresponding hardware configuration instruction, wherein the software configuration instruction comprises structural parameters of the data stream acceleration engine(“The depth of the circular buffer 332 is software configurable to accommodate the size and format of data transferred and transfer latency between the stream accelerator 204 and memory external to the VPAC 108. For example, configuration information provided to the stream accelerator 204 and the DMA controller 212 by the GPP 106 may set the depth of the circular buffer 332.”, 0035 ; “The depth of the circular buffer 334 is software configurable to accommodate the size and format of data transferred and transfer latency between external memory and the stream accelerator 206.”, 0036 ; Examiner Note: the configuration information provided to the stream accelerator equates to a software configuration instruction. The depth of the circular buffer equates to a structural parameter of the architecture of the data stream acceleration engine)
Degenaro in view of Chen in further view of Mody discloses the above limitations of claim 6, but does not disclose the hardware configuration instruction being used for allocating hardware resources required for the structure of the data stream acceleration engine.
However, Kruglick discloses:
the hardware configuration instruction is used for allocating hardware computing resources required for the structure of the data stream acceleration engine (“According to yet other examples, a computer readable medium may store instructions for integrating hardware accelerators in a datacenter. Example instructions may include receiving a customer accelerator block for a hardware accelerator configuration, retrieving the other accelerator block upon determining that the hardware accelerator configuration specifies another accelerator block, forming a hardware accelerator by integrating the customer accelerator block and the other accelerator block at the datacenter according to the hardware accelerator configuration”, 0008 ; Examiner Note : integrating hardware accelerators into the hardware accelerator equates to allocating hardware computing resources required for the structure of the data stream acceleration engine)
Degenaro in view of Chen in further view of Mody in further view of Kruglick discloses the above limitations of claim 6, but does not disclose transmitting software or hardware configuration instructions via a control channel.
However, Yan discloses:
transmitting, via the control channel, the software configuration instruction and the hardware configuration instruction to perform the software configuration and the hardware configuration on the data stream acceleration engine
As per claim 7, Degenaro in view of Chen fully discloses the limitations of claim 6.
Furthermore, Degenaro discloses:
the main controller device is configured to perform the following steps: receiving a raw data stream collected by the data acquirer (“In one embodiment, the real time data flow router 115 includes a network packet IP router that can be configured in promiscuous mode to send packets both to their original destination, e.g., absent acceleration, and to the one or more configured additional destinations as specified by the dynamic router controller 115. In another embodiment, the packets are strictly redirected to the dynamic router controller 115 configured destinations only. With the completion of this step, streams of information are now flowing from raw streams shown as the workload generator component 116 comprising the real time data flow router 115 and its information supply (not shown), to the configured stream accelerator devices 113.”, 0039)
outputting the result of data stream acceleration processing (see fig.1- block 119: source processing elements ; “During runtime, the network of consumer processing elements 118 have their needs satisfied by the system through dynamic connections to system generated source processing elements 119, which are producing information of the desired types.”, 0040 ; “Certain processing elements may consume data produced by the data stream acceleration devices”, 0041 ; Examiner Note: the source processing elements perform the actions of obtaining and outputting the result of the data stream acceleration processing)
Degenaro discloses the above actions taken by main control module (i.e., System-S), but does not disclose the performance of preliminary processing.
However, Chen discloses:
perform preliminary processing on the raw data stream (“During operation, the media processor 1702 and vision processor 1704 can work in concert to accelerate computer vision operations. The media processor 1702 can enable low latency decode of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip-memory 1705. The vision processor 1704 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation of processing the frames using a trained image recognition model”, 0240)
As per claim 8, Degenaro in view of Chen fully discloses the limitations of claim 7.
Furthermore, Degenaro discloses:
all devices in the system are integrated into a single computer device or distributed to different computer devices to form a distributed data stream acceleration system (“A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by programs executing on the computing system.", abstract ; " These singleton services can be co-located on a single processing node or distributed among a collection of processing nodes in communication across one or more local or wide area networks.", 0024)
As per claim 9, Degenaro in view of Chen fully discloses the limitations of claim 1.
Furthermore, Degenaro discloses:
A computer device, comprising a memory and a processor, wherein the memory stores computer programs, and the processor, when executing the computer programs, performs the local data stream acceleration method of claim 1 (“Suitable data processing systems for storing and/or executing program code include, but are not limited to, at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements include local memory employed during actual execution of the program code, bulk storage, and cache memories, which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.”, 0053)
As per claim 10, Degenaro in view of Chen fully discloses the limitations of claim 1.
Furthermore, Degenaro discloses:
A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer programs, and the computer programs, when executed by a processor, perform the local data stream acceleration method of claim 1 (“A computer-readable medium containing a computer-readable code that when read by a computer causes the computer to perform a method for managing distributed computer data stream acceleration devices”, clm. 13)
Claims 2-3, 11-12, 14-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Degenaro (US 20100058036 A1) in view of Chen (US 20180314521 A1) in further view of Mody (US 20200210351 A1) in further view of Kruglick (US 20150261550 A1) in further view of Yan (US 20190108043 A1) in further view of Swaminathan (US 20170171564 A1) in further view of Dang (US 20180293488 A1).
As per claim 2, Degenaro in view of Chen fully discloses the limitations of claim 1,
Furthermore, Degenaro discloses:
the raw data stream comprises an audio and video data stream and a text data stream (“This silicon-based family of hardware devices employed specifically for processing streams of data (e.g., text, audio, video) is referred to generally as data stream acceleration devices.", 0022)
Degenaro discloses the processing of audio, video, and text streams, but does not disclose the preliminary processes being performed on these streams.
However, Swaminathan discloses:
performing the preliminary processing on the raw data stream comprises: encoding, decoding and vectorizing the audio and video data stream and the text data stream (“Example 1 includes a method for encoding digital video content. The method includes: vectorizing a compressed video stream to provide a plurality of vectors", 0064 ; “As will be appreciated, MPEG compression is used herein in a generic fashion, and is intended to include all typical use cases, including those where the audio and video of a given media file is compressed by one of the standards that the Moving Picture Experts Group (MPEG) has promulgated… the vectorizer 101 can be configured to receive any type of compressed video stream, regardless of the compression standard used.", 0021 ; “For purposes of decoding (which may occur at the transmitting node or the receiving node, as previously explained), the residual vectors are added back to the codebook vector, which can be looked up or otherwise identified using the stored codebook index.”, 0036 ; Examiner Note: vectorizing is a method of encoding- thus Swaminathan is performing encoding and/or vectorizing, and decoding, on video content. The processing of previously encoded data requires decoding the data first- as such Swaminathan teaches encoding, decoding, and vectorizing audio and video streams.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the system of Degenaro in view of Chen with the vectorization of Swaminathan, in order to substantially reduce the bit rate of the data stream being processed.
Degenaro in view of Chen in further view of Swaminathan teaches the vectorization of audio and video data streams, but does not disclose the preliminary processing of text data streams.
However, Dang discloses:
performing the preliminary processing on the raw data stream comprises: encoding, decoding and vectorizing the audio and video data stream and the text data stream (“To apply deep learning based techniques, the natural language texts are transformed into (e.g., well-formed) vectorized data. Such data is also referred to as doc-images. The preliminary processes include text segmentation, also known as morphological analysis or tokenization, and word embedding.”, 0048)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the system of Degenaro in view of Chen in view of Swaminathan with the method of Dang in order to provide the system with the ability to vectorize any form of data stream, including pure text data.
As per claim 3, Degenaro in view of Chen in further view of Swaminathan in further view of Dang fully discloses the limitations of claim 2.
Furthermore, Degenaro discloses:
configuring the local data stream acceleration engine, and inputting the preliminarily processed raw data stream into the data stream acceleration engine for the acceleration processing (“at least one of the plurality of identified acceleration devices is configured in accordance with each identified virtual acceleration device definition. Each configured acceleration device is used to process the inquiry.", 0016 ; Examiner Note: being used to process the ‘inquiry’ necessitates inputting the data to be accelerated into the acceleration device.)
Degenaro in view of Chen discloses the configuration of a data stream acceleration engine, but does not disclose the configuration being performed by transmitting a configuration instruction.
However, Yan discloses:
transmitting, via a control channel, a configuration instruction to the data stream acceleration engine for configuration; and inputting, via a data channel, the raw data stream to the configured data stream acceleration engine for acceleration (“In some embodiments, the apparatus may comprise a controller (e.g., power kernel and controller 270). The controller may be coupled to the interface and/or may be operable to transmit the configuration command set to the interface.”, 0084)
As per claim 11, it is a system claim with substantially the same limitations as claim 2, and as such, it is rejected for substantially the same reasons.
As per claim 12, it is a system claim with substantially the same limitations as claim 3, and as such, it is rejected for substantially the same reasons.
As per claim 14, it is a system- or computer device- claim with substantially the same limitations as claim 2, and as such, it is rejected for substantially the same reasons.
As per claim 15, it is a system- or computer device- claim with substantially the same limitations as claim 3, and as such, it is rejected for substantially the same reasons.
As per claim 17, it is a storage medium claim with substantially the same limitations as claim 2, and as such, it is rejected for substantially the same reasons.
As per claim 18, it is a storage medium claim with substantially the same limitations as claim 3, and as such, it is rejected for substantially the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Boesch (US 11562115 B2) – discloses a configurable accelerator framework which includes a stream switch and a plurality of convolution accelerators.
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/R.M.V./
Examiner, Art Unit 2196
/HIREN P PATEL/Primary Examiner, Art Unit 2196