Prosecution Insights
Last updated: April 19, 2026
Application No. 17/772,643

DISPLAY PANEL AND DISPLAY DEVICE

Non-Final OA §102§103
Filed
Apr 28, 2022
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wuhan China Star Optoelectronics Technology Co., Ltd.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
651 granted / 914 resolved
+3.2% vs TC avg
Strong +19% interview lift
Without
With
+19.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
73 currently pending
Career history
987
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
17.5%
-22.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 914 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 06/30/2025. Response to Arguments Applicant's arguments have been fully considered but they are not persuasive. See rejection below. PNG media_image1.png 680 714 media_image1.png Greyscale HE discloses wherein the first inorganic encapsulation layer defines a protruding structure corresponding to an edge of the first metal structure (the arrow as labeled by examiner above representing corresponding as claimed); and PNG media_image2.png 576 1089 media_image2.png Greyscale PNG media_image3.png 332 1003 media_image3.png Greyscale wherein a difference value between a distance between an upper surface of the insulating layer at the extending portion and an upper surface of the base substrate (labeled as A) and a distance between an upper surface of the insulating layer located between the first metal structure and its adjacent first metal structure, which belongs to another column spacer of the at least one column spacer, and the upper surface of the base substrate (labeled as B) is greater than a thickness of the first metal structure (a thickness as labeled by C - since the incline side of the trapezoid has varying thickness and examiner chose a thickness which examiner labeled as C). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, 9-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HE et al. 20220045300. PNG media_image4.png 660 550 media_image4.png Greyscale Regarding claims 1 and 14, fig. 9 of HE discloses a display device, comprising a photosensitive device (par [0003] - camera, sensor and the like) and a display panel, comprising a photosensitive area 20, a transition area 30 surrounding at least part of the photosensitive area, and a display area 10 surrounding at least part of the transition area, and the display panel further comprising: a base substrate 60; a driver circuit layer (TFT layer) disposed on the base substrate; at least one column spacer 31 disposed on the base substrate and located in the transition area; a light-emitting layer 61 disposed on a side of the driver circuit layer away from the base substrate and covering the transition area, wherein the light-emitting layer is broken at the at least one column spacer; and a first inorganic encapsulation layer 651 disposed on a side of the light-emitting layer away from the base substrate, wherein the first inorganic encapsulation layer covers the display area and extends to the transition area and at least covers the column spacer; wherein the at least one column spacer each comprises a first metal structure 3102, an insulating layer 34/35, and a second metal structure 311, the first metal structure is disposed on the base substrate, the insulating layer is disposed on the first metal structure, the second metal structure is disposed on the insulating layer, and at least one side of the second metal structure defines a notch (region of 3111 is notch between 3112 and 3110); PNG media_image1.png 680 714 media_image1.png Greyscale wherein the first inorganic encapsulation layer defines a protruding structure corresponding to an edge of the first metal structure (the arrow as labeled by examiner above representing corresponding as claimed); wherein the first metal structure comprises a main body portion (the rectangular body) disposed overlapping the second metal structure and an extending portion (the triangular body) extending from the main body portion; PNG media_image2.png 576 1089 media_image2.png Greyscale PNG media_image3.png 332 1003 media_image3.png Greyscale wherein a difference value between a distance between an upper surface of the insulating layer at the extending portion and an upper surface of the base substrate (labeled as A) and a distance between an upper surface of the insulating layer located between the first metal structure and its adjacent first metal structure, which belongs to another column spacer of the at least one column spacer, and the upper surface of the base substrate (labeled as B) is greater than a thickness of the first metal structure (a thickness as labeled by C - since the incline side of the trapezoid has varying thickness and examiner chose a thickness which examiner labeled as C). Regarding claims 3 and 16, fig. 9 of HE discloses wherein a thickness of the insulating layer at the extending portion is greater than a thickness of the insulating layer at the main portion. Regarding claim 9, fig. 9 of HE disclose wherein the display panel comprises a retaining wall 371 disposed on the base substrate and located in the transition area; wherein the at least one column spacer is at least two column spacers, one (left one) or more of the at least two column spacers are disposed relative to a side (left side) of the retaining wall (which is) close to the display area, and another (right one) one or more of the at least two column spacers are disposed relative to a side (right side) of the retaining wall away from the display area. Regarding claim 10, fig. 9 of HE discloses wherein a distance between an upper surface of the one or more column spacers disposed relative to the side of the retaining wall close to the display area and an upper surface of the base substrate is equal to a distance between an upper surface of the another one or more column spacers disposed relative to the side of the retaining wall away from the display area and the upper surface of the base substrate. Regarding claim 11, fig. 9 of HE discloses further comprising an organic encapsulation layer 652 and a second inorganic encapsulation layer 651, the organic encapsulation layer is disposed on the first inorganic encapsulation layer, and the second inorganic encapsulation layer 653 is disposed on the organic encapsulation layer, wherein the organic encapsulation layer is disposed relative to the side of the retaining wall close to the display area; wherein part of the second inorganic encapsulation layer is disposed flat on the organic encapsulation layer relative to the side of the retaining wall close to the display area, and part of the second inorganic encapsulation layer is disposed on the first inorganic encapsulation layer relative to the side of the retaining wall away from the display area, wherein the second inorganic encapsulation layer defines an auxiliary protruding structure (low dip structure of 653/651 between 31) corresponding to the protruding structure. Regarding claim 12, fig. 9 of HE discloses wherein a thickness of the auxiliary protruding structure is less than a thickness of the protruding structure (thickness of 653/651 on the side of 31). Regarding claim 13, fig. 9 of HE discloses wherein the base substrate and the driver circuit layer together define a through hole in the photosensitive area. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over HE Regarding claims 4 and 17, fig. 9 of HE does not discloses wherein a difference value between a distance between an upper surface of the insulating layer at the main body portion and the upper surface of the base substrate and the distance between the upper surface of the insulating layer located between the first metal structure and its adjacent first metal structure and the upper surface of the base substrate is equal to the thickness of the first metal structure. In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. As such it would have been obvious to form a display panel of HE wherein a difference value between a distance between an upper surface of the insulating layer at the main body portion and the upper surface of the base substrate and the distance between the upper surface of the insulating layer located between the first metal structure and its adjacent first metal structure and the upper surface of the base substrate is equal to the thickness of the first metal structure in order to meet the applicant design requirement. Claims 6-8 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over HE in view of Ebisuno et al. 20220069045. Regarding claims 6 and 19, HE discloses claims 1 and 14 He discloses wherein the driver circuit layer comprises, a semiconductor layer (that active layer of 63), a first gate electrode layer, a first gate insulating layer 33, a second gate insulating layer 34, a first metal layer (source electrode layer – par [0022]), and a second metal layer (drain electrode layer), the semiconductor layer is disposed above the base substrate, the first gate insulating layer 33 is disposed on the semiconductor layer, the first gate electrode layer is disposed on the first gate insulating layer, the second gate insulating layer 34 is disposed on the first gate electrode layer. HE does not disclose of a shielding metal layer, a second gate metal layer, the shielding metal layer is disposed on the base substrate, the semiconductor layer is disposed above the shielding metal layer, the second gate metal layer is disposed on the second gate insulating layer, the first metal layer is disposed above the second gate metal layer, and the second metal layer is disposed above the first metal layer; wherein the first metal structure and one of the shielding metal layer, the first gate metal layer, and the second gate metal layer are disposed in a same layer, and the second metal structure is disposed in a same layer as the first metal layer or the second metal layer. PNG media_image5.png 537 749 media_image5.png Greyscale However, fig. 9 of Ebisuno discloses display panel comprising a driver circuit layer comprises a shielding metal layer BML, a semiconductor layer A2, a first gate metal layer G2, a first gate insulating layer 11, a second gate metal layer CE2’, a second gate insulating layer 113, a first metal layer S2/D2 (in IL layer), and a second metal layer (layer on top of 115), the shielding metal layer is disposed on a base substrate 105, the semiconductor layer is disposed above the shielding metal layer, the first gate insulating layer is disposed on the semiconductor layer, the first gate metal layer is disposed on the first gate insulating layer, the second gate insulating layer is disposed on the first gate metal layer, the second gate metal layer is disposed on the second gate insulating layer, the first metal layer is disposed above the second gate metal layer, and the second metal layer is disposed above the first metal layer. In view of such teaching, it would have been obvious to form a display panel of HE further comprising wherein the first gate electrode is a metal layer and a shielding metal layer, a second gate metal layer, the shielding metal layer is disposed on the base substrate, the semiconductor layer is disposed above the shielding metal layer, the second gate metal layer is disposed on the second gate insulating layer, the first metal layer is disposed above the second gate metal layer, and the second metal layer is disposed above the first metal layer such as taught by Ebisuno in order to form a storage capacitor and to shield light from the thin film transistor. The resulting structure would have been one wherein the first metal structure and one of the shielding metal layer, the first gate metal layer, and the second gate metal layer are disposed in a same layer, and the second metal structure is disposed in a same layer as the first metal layer or the second metal layer. Regarding claims 7 and 20, HE and Ebisuno do not disclose of wherein the smaller a distance between the first metal structure and the second metal structure is, the greater a thickness of the protruding structure is. However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. As such it would have been obvious to form a structure of HE comprising wherein the smaller a distance between the first metal structure and the second metal structure is, the greater a thickness of the protruding structure is in order to investigate device size shrinkage. Regard claim 8, fig. 9 of HE discloses wherein the second metal structure 311 comprises a first metal material layer 3110, a second metal material layer 3111, and a third metal material layer 3112 the second metal material layer is disposed on the first metal material layer, and the third metal material layer is disposed on the second metal material layer, wherein a width of the second metal material layer is less than a width of the first metal material layer and a width of the third metal material layer, respectively. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 28, 2022
Application Filed
Sep 30, 2024
Non-Final Rejection — §102, §103
Dec 24, 2024
Response Filed
Mar 27, 2025
Final Rejection — §102, §103
May 28, 2025
Response after Non-Final Action
Jun 30, 2025
Request for Continued Examination
Jul 01, 2025
Response after Non-Final Action
Oct 23, 2025
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604622
DISPLAY SUBSTRATE AND DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
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Patent 12588424
NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12581835
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2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.1%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 914 resolved cases by this examiner. Grant probability derived from career allow rate.

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