DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 11/18/2025 for application number 17/773,477. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant’s Remarks and Amendments.
Examiner Notes the following: Claims 1, 3-6, 7, 10-13, and 15 have been amended. Claims 2, 9, and 16-17 have been canceled. Claim 18 have been newly added. Claims 1, 3-8, 10-15, and 18 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Remarks
Examiner notes with respect to Double Patenting, the applicant did not properly respond to the double patenting rejection. Merely stating that the claim amendments have changed the scope of the claims does not provide specific reasoning explaining why the claims are patentably distinct from the claims in related application 17/773,446. Any response to the final rejection must respond to the double patenting rejection of the claims with a terminal disclaimer or proper arguments.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “the secondary functional circuit is further configured to send the Winograd convolution result of the input data to the main memory circuit” must be shown or the feature canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance
Claim Objections
Claims 1 and 8 objected to because of the following informalities:
In claim 1 and 8, “wherein a count of the plurality of second sub-tensors is same as a count of non-zeros” should read as “wherein a count of the plurality of second sub-tensors is the same as a count of non-zeros” (Emphasis added).
In claim 10, all instances of “first sub-tensor” should read as “second sub-tensor”
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-15 and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, claims 1-7 recites a computing device and, therefore, is a machine. Claims 8-15 recites a computing device and, therefore, is a machine. Claim 18 recites a computing device and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 1 recites
A computing device comprising a main instruction processing circuit, a main memory circuit, and a main functional circuit, wherein
the main instruction processing circuit is configured to, after receiving an input instruction, send a first control signal to the main memory circuit and the main functional circuit according to the input instruction,
the main memory circuit is configured to send input data to the main functional circuit according to the first control signal, and the input data is represented in the form of a tensor, and
the main functional circuit is configured to:
decompose the input data into a plurality of first sub-tensors according to the first control signal, wherein a count of the plurality of first sub-tensors is same as a count of non-zero elements in the input data;
perform a winograd forward transformation on the plurality of first sub-tensors to obtain winograd forward transformation results of the plurality of first sub-tensors; and
perform a summation operation on the winograd forward transformation results of the plurality of first sub-tensors to obtain a winograd forward transformation result of the input data.
The above underlined limitations are related to computing a winograd forward transformation of the input data which amount to mathematical calculations and relationships that falls under the “mathematical concepts” groupings of abstract ideas (see specification pages 3-7). Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a main instruction processing circuit”, “a main memory circuit”, ”a main functional circuit”, “receiving an input instruction”, “send a first control signal… according to the input instruction”, and “send input data… according to the first control signal”. However, the additional elements of “a main instruction processing circuit”, “a main memory circuit”, and ”a main functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; as a generic computer component for storing data; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element(s) of “receiving an input instruction”, “send a first control signal… according to the input instruction”, and “send input data… according to the first control signal” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 1 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a main instruction processing circuit”, “a main memory circuit”, and ”a main functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; as a generic computer component for storing data; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element(s) of “receiving an input instruction”, “send a first control signal… according to the input instruction”, and “send input data… according to the first control signal” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture) Preface p.18, chapter 1, sections 1.1-1.4 and chapter 3, sections 3.1-3.2, which discloses that the control unit provides control signals for the operation and coordination of all processor components. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claims 3-7 recite further steps and details to computing a winograd forward transformation of the input data and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 3, is directed to determining the number of sub-tensors that composes the input data. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 4, is directed to the calculation to determine the winograd forward transformation of the input data by multiplying the sub-tensors elements of the input by a corresponding winograd forward transform of a meta-tensor. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 5, is directed to computing the winograd forward transform of the meta-tensor. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 6, is directed to using a caching unit to hold the result of the functional unit. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 6 recites the following additional elements: “a caching circuit” and “stores the winograd… result of the input data”. However, the additional element of “a caching circuit” is recited at a high-level of generality (i.e., as a generic computer component for storing the output) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “stores the winograd… result of the input data” is merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 6 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “a caching circuit” is recited at a high-level of generality (i.e., as a generic computer component for storing the output) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional element of “stores the winograd… result of the input data” is merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 7, is directed to limiting the input data to specific types of data. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 7 recites the following additional element: “the input data is an input neuron or a weight”. The additional element of “the input data is an input neuron or a weight“ is merely generally linking the use of a judicial exception to a particular technological environment or field of use of Neural Networks by respectfully limiting the input data to contain only weights or neuron data. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 7 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of “the input data is an input neuron or a weight“ is merely generally linking the use of a judicial exception to a particular technological environment or field of use of Neural Networks by respectfully limiting the input data to contain only weights or neuron data. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claim 8 recites
A computing device comprising:
a main instruction processing circuit, a main functional circuit, a secondary instruction processing circuit, and a secondary functional circuit, wherein
the secondary instruction processing circuit is configured to:
receive a second control signal sent by the main instruction processing circuit; and
send the second control signal to the secondary functional circuit, and the secondary functional circuit is configured to:
receive a winograd forward transformation result of input data sent by the main functional circuit, wherein the winograd forward transformation result of the input data includes a winograd forward transformation result of an input neuron; and
perform, based on the second control signal, an element-wise multiplication on the winograd forward transformation result of the input neuron and a winograd forward transformation result of a weight to obtain an element-wise multiplication result;
decompose the element-wise multiplication result into a plurality of second sub-tensors, wherein a count of the plurality of second sub-tensors is same as a count of non-zero elements in the element-wise multiplication result;
perform a winograd backward transformation on the plurality of second sub-tensors to obtain winograd backward transformation results of the plurality of second sub-tensors; and
perform a summation operation on the winograd backward transform results of the plurality of second sub-tensors to obtain a winograd convolution result of the input data.
The above underlined limitations are related to computing a winograd backward transformation of a multiplication of winograd forward transformation of the input data and winograd forward transformation of the weight data with which amount to mathematical calculations and relationships that falls under the “mathematical concepts” groupings of abstract ideas (see specification pages 8-12). Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, “a secondary functional circuit”, “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal”. However, the additional elements of “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, and “a secondary functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, and “a secondary functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture) Preface p.18, chapter 1, sections 1.1-1.4 and chapter 3, sections 3.1-3.2, which discloses that the control unit provides control signals for the operation and coordination of all processor components. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 10-15 recite further steps and details to computing a winograd backward transformation of a multiplication of winograd forward transformation of the input data and winograd forward transformation of the weight data and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 10, is directed to determining the number of sub-tensors that composes the input data. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 11, is directed to the calculation to determine the winograd backward transformation of the multiplication result by multiplying the sub-tensors elements of the multiplication result by a corresponding winograd backward transform of a meta-tensor. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 12, is directed to computing the winograd backward transform of the meta-tensor. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Claim 13, is directed to using a memory circuit to hold the result of the main functional unit. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 13 recites the following additional elements: “a secondary instruction processing circuit”, “send the second control signal”, and “send the winograd… according to the second control signal”. However, the additional elements of “a secondary instruction processing circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “send the second control signal”, and “send the winograd… according to the second control signal” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 13 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a secondary instruction processing circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “send the second control signal”, and “send the winograd… according to the second control signal” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture) Preface p.18, chapter 1, sections 1.1-1.4 and chapter 3, sections 3.1-3.2, which discloses that the control unit provides control signals for the operation and coordination of all processor components. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 14, is directed to outputting the data to a main memory circuit. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 14 recites the following additional elements: “a main memory circuit”, and “send the winograd… to main memory”. However, the additional elements of “a main memory circuit” are recited at a high-level of generality (i.e., as a generic computer component for holding data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “send the winograd… to main memory” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claims are not integrated into a practical application.
Under the Alice Framework Step 2B, claim 13 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a main memory circuit” are recited at a high-level of generality (i.e., as a generic computer component for holding data) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “send the winograd… to main memory” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture) Preface p.18, chapter 1, sections 1.1-1.4 and chapter 3, sections 3.1-3.2, which discloses that the control unit provides control signals for the operation and coordination of all processor components. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 15, is directed to conversion and data rounding. See Gottschalk v. Benson, 409 U.S. 63, 70, 175 USPQ 673, 676 (1972), the conversion of binary-coded-decimal (BCD) numerals into pure binary numbers is directed to “Mathematical Concepts” of abstract ideas. As such, the converting data into another format is directed to “Mathematical Concepts” of abstract ideas. The claim does not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 18 recites
A computing device comprising:
a main instruction processing circuit, a main functional circuit, a secondary instruction processing circuit, and a secondary functional circuit, wherein
the secondary instruction processing circuit is configured to:
receive a second control signal sent by the main instruction processing circuit; and
send the second control signal to the secondary functional circuit, and the secondary functional circuit is configured to:
receive a winograd forward transformation result of input data sent by the main functional circuit, wherein the winograd forward transformation result of the input data includes a winograd forward transformation result of an input neuron; and
perform, based on the second control signal, an element-wise multiplication on the winograd forward transformation result of the input neuron and a winograd forward transformation result of a weight to obtain an element-wise multiplication result;
decompose the element-wise multiplication result into a plurality of second sub-tensors, wherein a count of the plurality of second sub-tensors is same as a count of non-zero elements in the element-wise multiplication result;
obtain a winograd backward transformation result of a second meta-tensor corresponding to a candidate second sub-tensor of the plurality of second subtensors, wherein
for the second meta-tensor corresponding to the candidate second sub-tensor, a value of an element at a second position in the second meta-tensor is 1, and
the second position of the second meta-tensor is the same as a position of non-zero elements in the second sub-tensor;
multiply a non-zero element value in the candidate second sub-tensor, as a coefficient, by the winograd backward transformation result of the second meta-tensor to obtain a winograd backward transformation result of the candidate second sub-tensor; and
add the winograd backward transformation result of each second sub-tensor of the plurality of second sub-tensors to obtain a winograd convolution result of the input data.
The above underlined limitations are related to computing a winograd backward transformation of a multiplication of winograd forward transformation of the input data and winograd forward transformation of the weight data with which amount to mathematical calculations and relationships that falls under the “mathematical concepts” groupings of abstract ideas (see specification pages 8-12). Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 1 recites the following additional elements: “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, “a secondary functional circuit”, “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal”. However, the additional elements of “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, and “a secondary functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 8 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a main instruction processing circuit”, ”a main functional circuit”, “a secondary instruction processing circuit”, and “a secondary functional circuit” are recited at a high-level of generality (i.e., as a generic computer component for controlling other computer components; and as a generic computer component for performing mathematical operations) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “receive a second control signal”, “receive a winograd forward transformation result of the input data”, “send the second control signal”, “send input data”, and “based on the second control signal” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Stallings (NPL: “Computer Organization and Architecture) Preface p.18, chapter 1, sections 1.1-1.4 and chapter 3, sections 3.1-3.2, which discloses that the control unit provides control signals for the operation and coordination of all processor components. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Werner et al. (US 2018/0189237 A1), hereinafter Werner, and in view of Corinthios (US 6,401,189 B1), and further in view of Agrawal et al (US 2018/0275909 A1), hereinafter Agrawal.
Regarding claim 1, Werner discloses:
A computing device comprising a main instruction processing circuit, a main memory circuit, and a main functional circuit [Figure 2B/C; Figure 5, Master Control CPU "MCC" 532, Memory Resource blocks "MRB(s)" 538a, and Slice Engine 536],
wherein the main instruction processing circuit is configured to, after receiving an input instruction, send a first control signal to the main memory circuit and the main functional circuit according to the input instruction ["matrix processing engine 500 may be implemented by...( e.g., matrix processing clusters 230 of matrix processing chip 220 ...)" par. 80; "(MCC) 232 may be configured to control and/or manage matrix operations performed by a matrix processing cluster 230. … CPU 232 may receive instructions from another component... The instruction ... may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238" par. 48; "[MCC] 232 may use slicing engine 236 to break up matrix operands into smaller partial matrices" par. 50; “Code 304, which may be one or more instructions to be executed by processor 300… fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction” par.62],
the main memory circuit is configured to send input data to the main functional circuit according to the first control signal, and the input data is represented in the form of a tensor [“Slice engine 536 may then "slice" the matrix data stored in MRBs 538a to extract the particular matrix operands associated with the convolution operations" Par. 92], and
the main functional circuit is configured:
to apply winograd forward transformation of the input data according to the first control signal, and perform calculation to obtain a winograd forward transformation result of the input data based on Winograd matrix multiplications [Figures 6A/6B, par. 103; "slice engine 536 performs a Winograd transform on the sliced matrix operand in order to generate a transformed matrix operand for the Winograd algorithm." par. 94; “(MCC) 232 may be configured to control and/or manage matrix operations performed by a matrix processing cluster 230” par. 48; “matrix processing engine 500 may perform matrix multiplication operations using an implementation of the Winograd matrix multiplication algorithm” par.81].
However, Werner does not explicitly disclose decompose the input data into a plurality of first sub-tensors according to the first control signal, wherein a count of the plurality of first sub-tensors is same as a count of non-zero elements in the input data; perform a winograd forward transformation on the plurality of first sub-tensors to obtain winograd forward transformation results of the plurality of first sub-tensors; and perform a summation operation on the winograd forward transformation results of the plurality of first sub-tensors to obtain a winograd forward transformation result of the input data.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches that for matrix multiplication to decompose a matrix into a summation operation ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" (i.e. meta-tensors) multiplied by a respective coefficient depending on the position in the matrix]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios discloses decompose the input data into a plurality of first sub-tensors according to the first control signal, perform a winograd forward transformation on the plurality of first sub-tensors to obtain winograd forward transformation results of the plurality of first sub-tensors; and perform a summation operation on the winograd forward transformation results of the plurality of first sub-tensors to obtain a winograd forward transformation result of the input data.
However, Werner and Corinthios does not explicitly disclose wherein a count of the plurality of first sub-tensors is same as a count of non-zero elements in the input data.
In the analogous art of matrix multiplication and data processing, Agrawal teaches avoiding any elements with the value of zero [“Partial Sums Rows 1-2 and 5-7 contribute nothing to the generation of product matrix 106, because each of their elements has a value of zero. Advantageously, this approach facilitates avoiding generation of such rows, thereby conserving computational resources“ par.9; “any elements of first sparse matrix 102 having a value of zero may be safely ignored during sparse matrix multiplication.” Par. 11; “avoiding multiplication with any elements of second sparse matrix 104 having a value of zero.” Par. 12; “storage resources may be conserved based on storing matrices in a compressed format that excludes any elements having a value of zero.” Par.13]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, and Agrawal before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by the combination of Werner and Corinthios to ignore or avoid the considerations of zero-valued elements in a matrix as taught by Agrawal, in order to reduce unnecessary matrix multiplications and conserve computational resources [Agrawal: par. 11-12]. As such, it would have been obvious to one of ordinary skill in the art, to not generate the sub-matrices/tensors with only zero elements. The combination of Werner, Corinthios, and Agrawal disclose wherein a count of the plurality of first sub-tensors is same as a count of non-zero elements in the input data.
Regarding claim 3, Werner, Corinthios, and Agrawal disclose the invention substantially as claimed. See the discussion of claim 1 above. However Werner does not explicitly disclose the additional limitations of claim 3.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches decomposing the input data wherein one element in each first sub-tensor of the plurality of first sub-tensors is the same as an element at a corresponding position in the input data, and other elements in a corresponding first sub-tensor of the plurality of first sub-tensors are 0 ["an "impulse matrix" as the matrix o(i,j) of which all the elements are zero except for the element at position (i,j)," Col. 6 ll. 38-45]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1].
Regarding claim 6, Werner, Corinthios, and Agrawal disclose the invention substantially as claimed. See the discussion of claim 1 above.
Werner discloses wherein the main functional circuit further includes a caching circuit, and wherein the main functional circuit is further configured to store the winograd forward transformation result of the input data into the caching circuit [Fig. 5; "the Winograd operand is stored in MRB 538b" par. 94].
Regarding claim 7, Werner, Corinthios, and Agrawal disclose the invention substantially as claimed. See the discussion of claim 1 above.
Werner discloses wherein the input data is an input neuron or a weight ["500, for example, may apply the Winograd algorithm to a 3x3 filter size," par. 82; "The sliced matrix operand, for example, may be a particular portion of the image data involved in the convolution operations." par. 93].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Werner, and in view of Corinthios, and in further view of Agrawal, and in further view of Stackoverflow-Spektre (NPL: “How do I compose a rotation matrix with human readable angles from scratch?”), hereinafter Spektre.
Regarding claim 4, Werner, Corinthios, and Agrawal disclose the invention substantially as claimed. See the discussion of claim 1 above.
Werner discloses wherein the main functional circuit is configured to perform a winograd forward transformation on the input data, wherein they apply matrix multiplication between matrices[Figures 6A/6B, par. 103; "slice engine 536 performs a Winograd transform on the sliced matrix operand in order to generate a transformed matrix operand for the Winograd algorithm."par.94; “matrix processing engine 500 may perform matrix multiplication operations using an implementation of the Winograd matrix multiplication algorithm” par.81].
However, Werner does not explicitly disclose: obtain a winograd forward transformation result of a first meta-tensor of corresponding to a candidate first sub-tensor of the plurality of first sub-tensors, wherein for the first meta-tensor corresponding to the candidate first sub-tensor a value of an element at a first position in the first meta-tensor is 1, and wherein the first position of the first meta-tensor is the same as a position of non-zero elements in the candidate first sub-tensor; multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the winograd forward transformation result of the first meta-tensor to obtain the winograd forward transformation result of the candidate first sub-tensor; and add the winograd forward transformation results of each first sub-tensors of the plurality of first sub-tensors to obtain the winograd forward transformation result of the input data.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches:
Decomposing the input data into a plurality of sub-tensors wherein each subtensor has a corresponding meta-tensor ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" multiplied by a respective coefficient depending on the position in the matrix];
wherein for the first meta-tensor corresponding to the candidate first sub-tensor a value of an element at a first position in the first meta-tensor is 1, and wherein the first position of the first meta-tensor is the same as a position of non-zero elements in the candidate first sub-tensor ["an "impulse matrix" as the matrix o(i,j) of which all the elements are zero except for the element at position (i,j)," Col. 6 ll. 38-45];
multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the first meta-tensor and add the results to obtain the input data ["An NxN matrix A having elements can be [A]ij=aij written as the sum" Col. 6 ll. 46-51, teaches each impulse matrix multiplied by a coefficient that is a corresponding value to the full matrix].
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios discloses obtaining a winograd forward transformation result of a first meta-tensor corresponding to a first sub-tensor, where for the first meta-tensor corresponding to the first sub-tensor, a value of an element at a first position in the first meta-tensor is 1, the first position of the first meta-tensor is the same as a position of the non-zero elements in the first sub-tensor and adding winograd forward transformation results of the plurality of first sub-tensors to obtain the winograd forward transformation result of the input data.
However Werner, Corinthios, and Agrawal does not explicitly disclose multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the winograd forward transformation result of the first meta-tensor to obtain the winograd forward transformation result of the candidate first sub-tensor;
In the analogous art of matrix multiplication and image/matrix processing, Spektre teaches precomputing the matrix multiplications [“Transformations are cumulative that means: p'=M1*M2*M3*M4*p; is the same as M=M1*M2*M3*M4; p'=M*p So if you have many points to transform then you precompute all transformations to single matrix and use just it. Do not need to multiply points by all subsequent matrices” p. 4, section 7. Usage]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, Agrawal, and Spektre before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by the combination of Werner, Corinthios, and Agrawal to calculate/precompute matrix multiplications taught by Spektre, in order to avoid multiplying multiple matrices to various data points [Spektre: p.4]. As such, It would have been obvious to one of ordinary skill in the art, to precompute the matrix multiplications of the winograd transform which is 2 constant matrices [Werner: Fig 6A] and the constant impulse matrices [Corinthios: Expression 4.1] i.e. “the winograd forward transformation result of the first meta-tensor”. The combination of Werner, Corinthios, Agrawal, and Spektre discloses multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the winograd forward transformation result of the first meta-tensor to obtain the winograd forward transformation result of the candidate first sub-tensor;
Regarding claim 5, Werner, Corinthios, Agrawal, and Spektre disclose the invention substantially as claimed. See the discussion of claim 4 above.
Werner discloses for the input data, multiply the left side of the input data by a forward transformation left-multiply matrix, and multiply the right side of the input data by a forward transformation right-multiply matrix to obtain the winograd forward transformation result of the input data [Figure 6A].
However, Werner does not explicitly disclose: multiply the left side of the first meta-tensor corresponding to the candidate first sub-tensor by a forward transformation left-multiply matrix; and multiply the right side of the first meta-tensor corresponding to the candidate first sub-tensor by a forward transformation right-multiply matrix.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches:
Decomposing the input data into a plurality of sub-tensors wherein each subtensor has a corresponding meta-tensor ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" multiplied by a respective coefficient depending on the position in the matrix];
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios multiply the left side of the first meta-tensor corresponding to the candidate first sub-tensor by a forward transformation left-multiply matrix; and multiply the right side of the first meta-tensor corresponding to the candidate first sub-tensor by a forward transformation right-multiply matrix.
Claims 8, 10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Werner, and in view of Corinthios, in further view of Agrawal and in further view of Lu et al. (NPL: SpWA: An Efficient Sparse Winograd Convolutional Neural Networks Accelerator on FPGAs"), hereinafter Lu.
Regarding claim 8, Werner discloses:
A computing device comprising a secondary instruction processing circuit, a main functional circuit, and a secondary functional circuit [Figure 2B/C; Figure 5, Master Control CPU "MCC" 532, Slice Engine 536, and output engine 537],
wherein the secondary instruction processing circuit is configured to receive a second control signal, and send the second control signal to the secondary functional circuit ["matrix processing engine 500 may be implemented by...( e.g., matrix processing clusters 230 of matrix processing chip 220 ...)" par. 80; "CPU 232 may receive instructions from another component... The instruction ... may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238" par. 48; matrix processing units (MPUs) 234 perform matrix operations based on commands received from master control CPU (MCC) 232" par. 49; “Code 304, which may be one or more instructions to be executed by processor 300… fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction” par.62];
the secondary functional circuit is configured to receive a winograd forward transformation result of input data sent by the main functional circuit, wherein the winograd forward transformation result of the input data includes a winograd forward transformation result of an input neuron ["MPUs 534 may be matrix processing units (MPUs) used to perform matrix operations… may perform matrix operations based on commands or instructions from master control CPU (MCC) 532" par. 87; "Output engine 537 may then perform matrix multiplication using the transformed Winograd operand created by slice engine 536", par. 95];
perform, based on the second control signal, an element-wise multiplication on the winograd forward transformation result of the input neuron and a winograd forward transformation result of a weight to obtain an element-wise multiplication result [ Fig. 5, filters and winograd operands; "matrix processing resources 210 may be configured to perform matrix multiplication operations, convolution operations, element-wise matrix operations (e.g., +,*,/,<,>,==)" par. 38; “Transform engine 531 is used to transform each Winograd output 538e and 538g into the final result for their respective matrix multiplication operations" par. 99; “matrix processing engine 500 may perform matrix multiplication operations using an implementation of the Winograd matrix multiplication algorithm” par.81],
a instruction processing circuit can distribute matrix operation and matrix operands to other instructions processing circuits["master control CPUs (MCCs) 232 may be configured to receive a matrix operation or command, and distribute the matrix operation and matrix operands across matrix processing clusters 230" par. 42]
wherein the secondary functional circuit is configured to perform a winograd backward transformation on the multiplication result to obtain the winograd convolution result of the input data [Figure 6B; The output transform 600B is an operation used to transform the intermediate Winograd output 620b of the Winograd algorithm into the final result 610b of the original matrix multiplication operation that is being performed using the Winograd algorithm” par. 104]
however, Werner does not explicitly disclose: a main instruction processing circuit, wherein the secondary instruction processing circuit is configured to receive a second control signal sent by the main instruction processing circuit, and decompose the element-wise multiplication result into a plurality of second sub-tensors according to the first control signal, wherein a count of the plurality of second sub-tensors is same as a count of non-zero elements in the element-wise multiplication result; perform a winograd backward transformation on the plurality of second sub-tensors to obtain winograd backward transformation results of the plurality of second sub-tensors; and perform a summation operation on the winograd second transformation results of the plurality of second sub-tensors to obtain a winograd convolution result of the input data.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches decompose a matrix into a summation operation for matrix multiplication ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" (i.e. meta-tensors) multiplied by a respective coefficient depending on the position in the matrix]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the output engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the multiplication result’s (i.e. input to the transformation) format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios disclose decompose the element-wise multiplication result into a plurality of second sub-tensors according to the first control signal; perform a winograd backward transformation on the plurality of second sub-tensors to obtain winograd backward transformation results of the plurality of second sub-tensors; and perform a summation operation on the winograd second transformation results of the plurality of second sub-tensors to obtain a winograd convolution result of the input data.
However, Werner and Corinthios does not explicitly disclose a main instruction processing circuit, wherein the secondary instruction processing circuit is configured to receive a second control signal sent by the main instruction processing circuit, and wherein a count of the plurality of second sub-tensors is same as a count of non-zero elements in the element-wise multiplication result
In the analogous art of matrix multiplication and data processing, Agrawal teaches avoiding any elements with the value of zero [“Partial Sums Rows 1-2 and 5-7 contribute nothing to the generation of product matrix 106, because each of their elements has a value of zero. Advantageously, this approach facilitates avoiding generation of such rows, thereby conserving computational resources“ par.9; “any elements of first sparse matrix 102 having a value of zero may be safely ignored during sparse matrix multiplication.” Par. 11; “avoiding multiplication with any elements of second sparse matrix 104 having a value of zero.” Par. 12; “storage resources may be conserved based on storing matrices in a compressed format that excludes any elements having a value of zero.” Par.13]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, and Agrawal before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by the combination of Werner and Corinthios to ignore or avoid the considerations of zero-valued elements in a matrix as taught by Agrawal, in order to reduce unnecessary matrix multiplications and conserve computational resources [Agrawal: par. 11-12]. As such, it would have been obvious to one of ordinary skill in the art, to not generate the sub-matrices/tensors with only zero elements. The combination of Werner, Corinthios, and Agrawal wherein a count of the plurality of second sub-tensors is same as a count of non-zero elements in the element-wise multiplication result
However, Werner, Corinthios, and Agrawal does not explicitly disclose a main instruction processing circuit, wherein the secondary instruction processing circuit is configured to receive a second control signal sent by the main instruction processing circuit,
In the analogous art of Winograd convolution data processing and architecture, Lu teaches distributing the winograd convolution operation into multiple processing elements [Figure 5; "Figure 5 shows an overview of SpWA architecture, which mainly consists of pre-processing element (pre-PE), computing processing element (com-PE) and post-processing element (post-PE)." Section 5.1 Architecture overview]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, Agrawal, and Lu before him before the effective filing date of the claimed invention to distribute the slice engine and output engine disclosed by Werner [Werner: figures 6A/6B] to other processing elements as taught by Lu, in order to implement pipelining, improve performance and minimize latency of the winograd convolution [Lu: 5 SPWA ARCHITECTURE DESIGN, and 6 EFFICIENT ALGORITHM]. The combination of Werner and Lu discloses a main instruction processing circuit, wherein the secondary instruction processing circuit is configured to receive a second control signal sent by the main instruction processing circuit.
Regarding claim 10, Werner, Corinthios, Agrawal, and Lu disclose the invention substantially as claimed. See the discussion of claim 8 above.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches one element in each first sub-tensor of the plurality of second sub-tensors is same as an element at a corresponding position corresponding to the element-wise multiplication result, and other elements in a corresponding first-sub are 0 ["an "impulse matrix" as the matrix o(i,j) of which all the elements are zero except for the element at position (i,j)," Col. 6 ll. 38-45]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the output engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the multiplication result format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1].
Regarding claim 13, Werner, Corinthios, Agrawal, and Lu disclose the invention substantially as claimed. See the discussion of claim 8 above.
Werner discloses wherein the computing device further includes a secondary memory circuit, the secondary instruction processing circuit is further configured to send the second control signal to the secondary memory circuit and the secondary memory circuit is configured to send the winograd forward transformation result of the weight to the secondary functional circuit according to the second control signal [Fig 5, MRB 538b; "matrix processing engine 500 may be implemented by...( e.g., matrix processing clusters 230 of matrix processing chip 220 ...)" par. 80; "CPU 232 may receive instructions from another component... The instruction ... may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238" par. 48; matrix processing units (MPUs) 234 perform matrix operations based on commands received from master control CPU (MCC) 232" par. 49; "Output engine 537 may then perform matrix multiplication using the transformed Winograd operand created by slice engine 536", par. 95].
Regarding claim 14, Werner, Corinthios, Agrawal, and Lu disclose the invention substantially as claimed. See the discussion of claim 8 above.
Werner discloses wherein the computing device further includes a main memory circuit, and the secondary functional circuit is further configured to send the winograd convolution result of the input data to the main memory circuit [Fig 5, MRB 538f/h; "transform engine 531 may then store the final result for each matrix multiplication operation in MRB 538f and MRB 538h, respectively." par. 99].
Claims 11, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Werner, Corinthios, Agrawal, and Lu, and in further view of Stackoverflow-Spektre (NPL: “How do I compose a rotation matrix with human readable angles from scratch?”), hereinafter Spektre.
Regarding claim 11, Werner, Corinthios, Agrawal, and Lu disclose the invention substantially as claimed. See the discussion of claim 8 above.
Werner discloses wherein the secondary instruction processing circuit is configured to receive a second control signal, and send the second control signal to the secondary functional circuit ["matrix processing engine 500 may be implemented by...( e.g., matrix processing clusters 230 of matrix processing chip 220 ...)" par. 80; "CPU 232 may receive instructions from another component... The instruction ... may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238" par. 48; matrix processing units (MPUs) 234 perform matrix operations based on commands received from master control CPU (MCC) 232" par. 49; “Code 304, which may be one or more instructions to be executed by processor 300… fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals that reflect the original code instruction” par.62];
wherein the secondary functional circuit is configured to perform a winograd backward transformation on the multiplication result to obtain the winograd convolution result of the input data [Figure 6B; The output transform 600B is an operation used to transform the intermediate Winograd output 620b of the Winograd algorithm into the final result 610b of the original matrix multiplication operation that is being performed using the Winograd algorithm” par. 104]
However, Werner does not explicitly disclose: Obtain a winograd backward transformation result of a second meta-tensor corresponding to a candidate second sub-tensor of the plurality of second sub-tensors, wherein for the second meta-tensor corresponding to the candidate second sub-tensor, a value of an element at a second position in the second meta-tensor is 1, and the second position of the second meta-tensor is the same as a position of non-zero elements in the candidate second sub-tensor; multiply a non-zero element value in the candidate second sub-tensor, as a coefficient, by the winograd backward transformation result of the second meta-tensor to obtain a winograd backward transformation result of the candidate second sub-tensor; and add the winograd backward transformation result of each second sub-tensor of the plurality of second sub-tensors to obtain the winograd convolution result of the input data.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches:
Decomposing the input data into a plurality of sub-tensors wherein each subtensor has a corresponding meta-tensor ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" multiplied by a respective coefficient depending on the position in the matrix];
wherein for the first meta-tensor corresponding to the candidate first sub-tensor a value of an element at a first position in the first meta-tensor is 1, and wherein the first position of the first meta-tensor is the same as a position of non-zero elements in the candidate first sub-tensor ["an "impulse matrix" as the matrix o(i,j) of which all the elements are zero except for the element at position (i,j)," Col. 6 ll. 38-45];
multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the first meta-tensor and add the results to obtain the input data ["An NxN matrix A having elements can be [A]ij=aij written as the sum" Col. 6 ll. 46-51, teaches each impulse matrix multiplied by a coefficient that is a corresponding value to the full matrix].
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios discloses obtain a winograd backward transformation result of a second meta-tensor corresponding to a candidate second sub-tensor of the plurality of second sub-tensors, wherein for the second meta-tensor corresponding to the candidate second sub-tensor, a value of an element at a second position in the second meta-tensor is 1, and the second position of the second meta-tensor is the same as a position of non-zero elements in the candidate second sub-tensor; and add the winograd backward transformation result of each second sub-tensor of the plurality of second sub-tensors to obtain the winograd convolution result of the input data.
However Werner, Corinthios, Agrawal, and Lu does not explicitly disclose multiply a non-zero element value in the candidate second sub-tensor, as a coefficient, by the winograd backward transformation result of the second meta-tensor to obtain the winograd backward transformation result of the candidate second sub-tensor;
In the analogous art of matrix multiplication and image/matrix processing, Spektre teaches precomputing the matrix multiplications [“Transformations are cumulative that means: p'=M1*M2*M3*M4*p; is the same as M=M1*M2*M3*M4; p'=M*p So if you have many points to transform then you precompute all transformations to single matrix and use just it. Do not need to multiply points by all subsequent matrices” p. 4, section 7. Usage]
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, Agrawal, Lu, and Spektre before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by the combination of Werner, Corinthios, and Agrawal to calculate/precompute matrix multiplications taught by Spektre, in order to avoid multiplying multiple matrices to various data points [Spektre: p.4]. As such, It would have been obvious to one of ordinary skill in the art, to precompute the matrix multiplications of the winograd transform which is 2 constant matrices [Werner: Fig 6A] and the constant impulse matrices [Corinthios: Expression 4.1] i.e. “the winograd forward transformation result of the first meta-tensor”. The combination of Werner, Corinthios, Agrawal, Lu, and Spektre discloses multiply a non-zero element value in the candidate second sub-tensor, as a coefficient, by the winograd backward transformation result of the second meta-tensor to obtain the winograd backward transformation result of the candidate second sub-tensor;
Regarding claim 12, Werner, Corinthios, Agrawal, Lu, and Spektre disclose the invention substantially as claimed. See the discussion of claim 11 above.
Werner discloses for the input data, multiply the left side of the input data by a backward transformation left-multiply matrix, and multiply the right side of the input data by a backward transformation right-multiply matrix to obtain the winograd convolution result of the input data [Figure 6B].
However, Werner does not explicitly disclose: multiply the left side of the second meta-tensor corresponding to the candidate second sub-tensor by a backward transformation left-multiply matrix; and multiply the right side of the second meta-tensor corresponding to the candidate second sub-tensor by a backward transformation right-multiply matrix.
In the analogous art of matrix multiplication and image/matrix processing, Corinthios teaches:
Decomposing the input data into a plurality of sub-tensors wherein each subtensor has a corresponding meta-tensor ["For the multiprocessing of matrix multiplications it is convenient to effect a decomposition of a matrix into the sum of matrices" Col. 6, ll. 35-55, teaches matrices can be broken down into a sum of "impulse matrices" multiplied by a respective coefficient depending on the position in the matrix];
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner and Corinthios before him before the effective filing date of the claimed invention to modify the slice engine’s Winograd transform matrix multiplication disclosed by Werner [Werner: figures 6A/6B] to apply the matrix decomposition techniques to change the data input format before applying the matrix multiplication as taught by Corinthios, in order to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. The combination of Werner and Corinthios multiply the left side of the second meta-tensor corresponding to the candidate second sub-tensor by a backward transformation left-multiply matrix; and multiply the right side of the second meta-tensor corresponding to the candidate second sub-tensor by a backward transformation right-multiply matrix.
Regarding claim 18, claim 18 is directed to claim 11. Claim 18 is rejected for the reasons given in claim 11 and it’s dependency on claim 8
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Werner, Corinthios, Agrawal, and Lu, in further view of Na et al. (US 2021/0056423 A1), hereinafter Na.
Regarding claim 15, Werner, Corinthios, Agrawal, and Lu disclose the invention substantially as claimed. See the discussion of claim 8 above. However, Werner, Corinthios, Agrawal, and Lu does not explicitly disclose the additional limitations of claim 15.
In the analogous art of convolution Neural Network data processing and formatting, Na teaches perform post-processing on the operation result of the input data, the post-processing includes a bitwise rounding operation and a conversion operation [“the output of the matrix multiplication 430 may not comprise thirty-two bits of precision. To the extent that the output of the matrix multiplication 430 comprises greater precision than that of the reduced-precision format in which inputs and outputs are to be exchanged, the round to nearest 730 can still perform some form of rounding to reduce a quantity of bits and, thereby, reduce the precision of the format in which the values output by the matrix multiplication 430” par. 61].
It would have been obvious to one of ordinary skill in the art, having the teachings of Werner, Corinthios, Lu, and Na before him before the effective filing date of the claimed invention to modify the output engine’s Winograd transform matrix multiplication disclosed by the combination of Werner and Corinthios to include rounding and conversion methodology taught by Na, in order to, represent data more efficiently, control the number of bits to improve memory consumption, and improve Neural network based operations [Na: par. 2, 22, 58, and 61]. The combination of Werner, Corinthios, Lu, and Na discloses the additional limitations of claim 15.
Allowable Subject Matter
The reasons for withdrawal of allowable subject matter on claim 11 and 12:
As discussed in the prior Office Action, the use of both the winograd forward and winograd backwards transformations on the multiplication result has been removed from claim 11. Now claim 11 relies only on winograd backward transformation. As such, the reasons for allowable subject matter on claim 11 has been withdrawn.
Claim 12 reasons for allowable subject matter was based on its dependency on claim 11. As such, the reasons for allowable subject matter on claim 12 has been withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,547,670 B2, hereinafter Reference Application, in view of Werner.
Regarding claim 1:
Instant Application (17/773,477)
Claim 1
Reference Application,
Claim 5/4/1
A computing device comprising a main instruction processing circuit, a main memory circuit, and a main functional circuit,
Claim 1: operation apparatus comprising: a control circuit; a storage circuit…; a compute circuit…
wherein the main instruction processing circuit is configured to, , send a first control signal to the main memory circuit and the main functional circuit according to the input instruction;
Claim 1: the control circuit is configured to extract a plurality of control instructions from the storage circuit… includes a first instruction… the first instruction includes a forward transformation instruction which is executable by the first compute circuit,
the main memory circuit is configured to send input data to the main functional circuit according to the first control signal, r; and
Claim 1: a storage circuit configured to store data related to an image… the storage circuit is configured to store the data for the winograd convolution operation
Claim 1: obtain a result of weight transformation based on the execution of the forward transformation instruction on the weight data
the main functional circuit is configured to
decompose the input data into a plurality of first sub-tensors according to the first control signal, wherein a count of the plurality of first sub-tensors is same as a count of non-zero elements in the input data
Claim 1: each of the first instruction… is to perform the winograd convolution operation…
wherein the compute circuit is further configured to:
parse the data to obtain a plurality of sub-tensors;…
wherein each sub-tensor of the plurality of sub-tensors has a non-zero element, and the non-zero element in each sub-tensor of the plurality of sub-tensors is the same as a non-zero element in a corresponding position in the data.
Perform a winograd forward transformation on the plurality of second sub-tensors to obtain winograd forward transformation results of the plurality of second sub-tensors; and
Perform a summation operation on the winograd forward transformation results of the plurality of second sub-tensors to obtain a winograd convolution result of the input data
Claim 1: the first compute circuit is configured to perform for each convolution layer of the neural network:
execute the forward transformation instruction on the weight data, execute the forward transformation instruction on the feature data,
obtain a result of weight transformation based on the execution of the forward transformation instruction on the weight data, and
store the result of the weight transformation in the storage circuit,
wherein the compute circuit is further configured to:
parse the data to obtain a plurality of sub-tensors;
Perform a transformation operation on the plurality of sub-tensors and sum results of the transformation operations
Obtain a winograd transformation result of the data according to a result of the summation
Claim 5: wherein the winograd transformation type includes a winograd transformation type of the forward transformation instruction and a winograd transformation type of the inverse transformation instruction.
However, the Reference Application does not explicitly disclose: after receiving an input instruction and the input data is represented in the form of a tensor
In the analogous art of winograd convolution processing architecture, Werner discloses the use of a control CPU that receives an input instruction and the input data is represented in the form of a tensor ["matrix processing engine 500 may be implemented by...( e.g., matrix processing clusters 230 of matrix processing chip 220 ...)" par. 80; "CPU 232 may receive instructions from another component... The instruction ... may also indicate how the matrices should be stored in memory resource blocks (MRBs) 238" par. 48;"232 may use slicing engine 236 to break up matrix operands into smaller partial matrices" par. 50;]
It would have been obvious to one of ordinary skill in the art, having the teachings of Reference Application and Werner before him before the effective filing date of the claimed invention to modify the control circuit and data disclosed by the Reference Application to include the ability to receive instructions for Winograd convolution operations taught by Werner, in order to, implement winograd operations, implement more distributive processing and utilize improvements for winograd convolutions [Werner: par. 14, 42, and 81].
Regarding claim 3, the Reference Application and Werner teaches the invention substantially as claimed. See the discussion of claim 2 above.
Instant Application (17/773,477)
Claim 3
Reference Application,
Claim 5/4/1
The computing device of claim 1, wherein, one element in each first sub-tensor of the plurality of first sub-tensors is same as an element at a corresponding position in the input data, and other elements in a corresponding first sub-tensor of the plurality of first sub-tensors are 0.
Claim 1: wherein each sub-tensor of the plurality of sub-tensors has a non-zero element, and the non-zero element in each sub-tensor of the plurality of sub-tensors is the same as a non-zero element in a corresponding position in the data.
Regarding claim 4, the Reference Application and Werner teaches the invention substantially as claimed. See the discussion of claim 3 above.
Instant Application (17/773,477)
Claim 4
Reference Application,
Claim 5/4/1
The computing device of claim 1, wherein to obtain the winograd forward transformation result of the input data, the main functional circuit is configured to:
Claim 1: the first compute circuit is configured to perform for each convolution layer of the neural network:
execute the forward transformation instruction on the weight data, execute the forward transformation instruction on the feature data,
obtain a result of weight transformation based on the execution of the forward transformation instruction on the weight data, and
store the result of the weight transformation in the storage circuit,
wherein the compute circuit is further configured to:
parse the data to obtain a plurality of sub-tensors;
Perform a transformation operation on the plurality of sub-tensors and sum results of the transformation operations
Obtain a winograd transformation result of the data according to a result of the summation
obtain a winograd forward transformation result of a first meta-tensor corresponding to a candidate first sub-tensor of the plurality of first sub-tensors, wherein for the first meta-tensor corresponding to the candidate first sub-tensor, a value of an element at a first position in the first meta-tensor is 1, and wherein the first position of the first meta-tensor is the same as a position of non-zero elements in the candidate first sub-tensor;
Claim 1: wherein each sub-tensor of the plurality of sub-tensors has a non-zero element, and the non-zero element in each sub-tensor of the plurality of sub-tensors is the same as a non-zero element in a corresponding position in the data.
Claim 4: wherein the compute circuit is further configured to:
obtain a winograd transformation result of a meta-tensor corresponding to each sub- tensor, wherein the meta-tensor is a tensor with the non-zero element of the sub-tensor set to 1;
multiply a non-zero element value in the candidate first sub-tensor, as a coefficient, by the winograd forward transformation result of the first meta-tensor to obtain the winograd forward transformation result of the candidate first sub-tensor;
Claim 4: multiply a value of the non-zero element of the sub-tensor as a coefficient by the winograd transformation result of the corresponding meta-tensor to obtain the winograd transformation result of the sub- tensors;
and add the winograd forward transformation result of each first sub-tensor of the plurality of first sub-tensors to obtain the winograd forward transformation result of the input data.
Claim 4: sum winograd transformation results of the plurality of sub-tensors obtain the winograd transformation result of the data.
Claim 5: wherein the winograd transformation type includes a winograd transformation type of the forward transformation instruction and a winograd transformation type of the inverse transformation instruction.
Regarding claim 5, the Reference Application and Werner teaches the invention substantially as claimed. See the discussion of claim 1 above.
Instant Application (17/773,477)
Claim 5
Reference Application, No. 17/773,446
Claim 5/4/1
The computing device of claim 4, wherein to obtain the winograd forward transformation result of the first meta-tensor corresponding to the candidate first sub-tensor, the main functional circuit is configured to:
Claim 5: wherein the compute circuit is specifically configured to multiply… to obtain the winograd transformation result of the meta-tensor,… wherein the winograd transformation type includes a winograd transformation type of a forward transformation
multiply the left side of the first meta-tensor corresponding to the candidate first sub-tensor by a forward transformation left-multiply matrix, and
Claim 5: multiply, for each sub-tensor, a left side of the meta-tensor corresponding to the sub- tensor by a left multiplication matrix; and
wherein the left multiplication matrix and the right multiplication matrix are both determined by a size of the sub-tensor … wherein the winograd transformation type includes a winograd transformation type of the forward transformation instruction…
multiplying the right side of the first meta-tensor corresponding to the first sub-tensor by a forward transformation right-multiply matrix to obtain the winograd forward transformation result of the first meta-tensor.
Claim 5: multiply a right side of the meta-tensor corresponding to the sub-tensor by a right multiplication matrix to obtain the winograd transformation result of the meta-tensor,… the right multiplication matrix are … determined by a size of the sub-tensor and a winograd transformation type, wherein the winograd transformation type includes a winograd transformation type of a forward transformation
Regarding claim 6, the Reference Application and Werner teaches the invention substantially as claimed. See the discussion of claim 1 above. However, Reference Application does not disclose the additional limitation of claim 6. More specifically, the main functional circuit further includes a caching circuit, and wherein the main functional circuit is further configured to store the winograd forward transformation result of the input data into the caching circuit.
In the analogous art of winograd convolution processing architecture, Werner discloses the main functional circuit further includes a caching circuit, and wherein the main functional circuit is further configured to store the winograd forward transformation result of the input data into the caching circuit. ["the Winograd operand is stored in MRB 538b" par. 94].
It would have been obvious to one of ordinary skill in the art, having the teachings of Reference Application and Werner before him before the effective filing date of the claimed invention to modify the compute circuit disclosed by the Reference Application to include the memory system to receive the results of the Winograd forward transformation taught by Werner, in order to, handle matrix data efficiently [Werner: par. 51].
Regarding claim 7, the Reference Application and Werner teaches the invention substantially as claimed. See the discussion of claim 1 above.
Instant Application (17/773,477)
Claim 7
Reference Application,
Claim 5/4/1
The computing device of claim 1, wherein the input data is an input neuron or a weight
Claim 1: the data includes feature data and weight data,
In the analogous art of winograd convolution processing architecture, Werner also discloses wherein the input data is an input neuron or a weight ["500, for example, may apply the Winograd algorithm to a 3x3 filter size," par. 82; "The sliced matrix operand, for example, may be a particular portion of the image data involved in the convolution operations." par. 93].
Response to Arguments
Applicant’s arguments, see pages 12-13, filed 11/18/2025, with respect to Specification Objections have been fully considered and are persuasive. The Specification Objections of the Office Action mailed 08/22/2025 has been withdrawn.
Applicant's arguments, see page 12, filed 11/18/2025, with respect to Drawing objections have been fully considered but they are not persuasive. Applicant did not respond to the objection listed above that was also in the prior Office Action mailed 08/22/2025. Drawing objection has been maintained.
Applicant's arguments, see page 32, filed 11/18/2025, with respect to Double Patenting have been fully considered but they are not persuasive. Applicant did not properly respond to the Double Patenting of the prior Office Action mailed 08/22/2025. See Examiner’s Remarks above. Double Patenting Rejection has been maintained.
Applicant's arguments, see page 13-32, filed 11/18/2025, with respect to Rejections under 35 U.S.C. 101 have been fully considered but they are not persuasive.
On page 14, the applicant argues that claim 1 does not recite a mathematical formula or equation. However, the argument is nor applying the proper analysis as required nor it is directed to the rejection as made. See MPEP 2106.04(a)(2). As Mathematical concepts also includes Mathematical Relationships that was used in the prior Office Action.
On pages 15, and 17 (for claims 1 and 8 respectively), the applicant argues that the decomposition of data into a plurality of sub-tensors is not a mathematical expression. However, the arguing is inconsistent with the specification nor would explain how this as an additional element would integrate into a practical application or amount to significantly more than the abstract idea. When considered as an additional element it would merely be receiving the data in a format to be computed by the abstract idea. Wherein, the recited decomposition of data is based on mathematical relationships that is required for the math to be computed. See specification p.5-7 and p.9-12.
On pages 16, and 17 (for claims 1 and 8 respectively), the applicant argues that the mathematical transform merely informs the circuit’s behavior and defines a practical hardware realization of the mathematical transform. However, the claim has to recite some improvement in technology that isn’t a natural consequence of the math as the improvement cannot come from the abstract idea. See MPEP 2106.05(a).
On pages 16, and 17 (for claims 1 and 8 respectively), the applicant argues that the claim as a whole does not recite a mathematical concept. However, the argument is not directed to a proper analysis of MPEP 2106.04 Step 2A. the claim does not need to recite the mathematical concept as a whole, but needs to recite a mathematical concept, such as the winograd transform.
On pages 16, and 17 (for claims 1 and 8 respectively), the applicant argues that the claim preempt a mathematical concept. However, preempt is not the sole test for determining eligibility. See MPEP 2106.04(I).
On pages 20-21 and 24-25, and 22-23 and 26-27 (for claims 1 and 8 respectively), the applicant argues the circuit components providing the benefits with respect to pages 3-5 and 8-13. However, the argument does not address the rejection as made, because they’ve not explained that these circuits are something more then mere instructions to apply the math in hardware. Page 3 describes the abstract idea and how the abstract idea provides the benefits argued. Pages 8-12 describes the decomposing of the data to be used by the math. Wherein an improvement/layout comes from the abstract idea, however the improvement to the technology can not come from the abstract idea. pages 4-5, 8, and 13 describe the use of the various units/circuits to compute the abstract idea. Wherein these units are described at a high level of generality.
On pages 20-21 and 24-25, and 22-23 and 26-27 (for claims 1 and 8 respectively), the applicant argues the circuit components as combined is a specialized device that integrates the application. However, the applicant is not addressing the rejection as made and the combination of the circuitry is merely a function of the abstract idea. The applicant has not described a technical improvement other than the abstract idea, wherein the layout of the circuitry is merely applying the function of the abstract idea as disclosed in the specification. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reason given above.
Applicant's arguments, see page 32-39, filed 11/18/2025, with respect to Rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. Applicant argues that Corinthios fails to disclose any decomposition being performed under the control of a signal generated. However, the argument is not directed to the rejection as made. The combination of Werner and Corinthios discloses the limitation, wherein Werner discloses controlling and processing matrix data formats and how they are stored. See par.48, 50, and 62.
Applicant also argues Agrawal provides no motivation to match the count of non-zero elements of the sparse matrix. However, the argument is not directed to the rejection as made. Agrawal discloses avoiding generating data with respect to any elements of the matrix having a value of zero as they may be safely ignored as it would just result in zero values. See Par. 11. Agrawal provides motivation for reducing unnecessary multiplications and conserve computational resources [Agrawal: par. 11-12].
Applicant also argues the combination distorts the intended operation of each reference. However, the argument is not directed to the rejection as made. Corinthios merely provides an alternative matrix multiplication and Agrawal provides the reasons to avoid dealing with zero-valued elements. It would’ve been obvious to one of ordinary skill in the art, to use the alternative matrix multiplication from Corinthios to improve parallelism and processing efficiency for matrix multiplication [Corinthios: Col. 6 and Col. 1]. Which is also improved by Agrawal to reduce the need for zero-valued elements as they contribute nothing to the final result to reduce unnecessary multiplications and conserve computational resources [Agrawal: par. 11-12]. The combination of Werner, Corinthios, and Agrawal still outputs the same results of as Werner’s use of matrix multiplication. The examiner respectfully disagrees with the applicant’s assertion to the contrary for at least the reason given above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182