DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are:
Control unit in claim 1, applicant discloses corresponding structure in paragraphs [0099 – 0104] of the specification.
Processing unit in claim 12, applicant discloses corresponding structure in paragraphs [0079, 0084, and 0086] of the specification
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4, 6-9, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20150087991 A1) in view of Langford (US 20200159045 A1).
Regarding claim 1, Chen teaches an ultrasound imaging system comprising an ultrasound imaging catheter ([0004] An ultrasonic imaging system; [0128] system can be mounted onto the tip of a catheter)
an ultrasound transducer array ([0061] an ultrasonic transducer array 120)
provided at a distal end of the ultrasound imaging catheter ([0128] system can be mounted onto the tip of a catheter)
and adapted to transmit and receive ultrasound signals ([0062] The transceiver element 140 includes a transmitter pulser circuit 141, a receiver low noise amplifier (LNA) 142, and selection logic 143)
wherein the ultrasound transducer array comprises a plurality of transducer elements ([0061] transducer elements 121 of the transducer array 120)
and a control unit provided at the distal end of the ultrasound imaging catheter ([0068] a CMUT array 200 can be stacked on a programmable ASIC 210 having a column input/output (I/O) logic 220 and row I/O logic 230)
configured to generate a control signal for the ultrasound transducer array ([0071] Since transmitter mode and receiver mode are independent and similar, the receiver mode can be used as an illustration of an operation of the transceiver channel. In this illustration, the control inputs are: i-th column (Rc[i]) and j-th row (Rd[j]) select signals from the sides; and per-element enable bit (R_en). The resultant local control signals are shown in FIG. 3B. As shown in FIG. 3B for the example implementation of the per-element logic block 310, the per-element logic can include a plurality of AND logic gates, where Tc[i] and T_en are used to provide Tc; Tr[j] and T_en are used to provide Tr, Rc[i]+Rr[j] and R_en are used to provide RxSw; Rc[i] and R_en are used to provide Rc; and Rr[j] and R_en are used to provide Rr. In this manner, the enable bits are used to control whether a particular element on a row and column is selected for activation; [0072] FIG. 4A illustrates control logic for a column-row-parallel ASIC architecture. Referring to FIG. 4A, a 2D array of transceivers 400 receive control signals (bits) for column selection 401 (e.g., Tc[i], Rc[i]), row selection 402 (e.g., Tr[j], Rr[j]), and per-element enable 410 (e.g., T_en, R_en). Column and row logic 420 provides the bits for column selection 401 and row selection 402 and can include at least one bank with registers 421 for storing a transmit or receive pattern. In the illustrated example, two banks 422, 424 are included, which in some implementations may be alternatingly selected using a "bankSel" control signal (which may be a clocked signal). For implementations using consolidated row and column select signals (e.g., where N I/O signals are available for the N.times.N (or N.times.M where N>M), a set of MUXes can be included as part of the column and row logic 420. A "mode" signal, provided by a controller, can select whether column or row selection is taking place)
a plurality of registers, each register comprising a plurality of bits ([0071] the control inputs are: i-th column (Rc[i]) and j-th row (Rd[j]) select signals from the sides; and per-element enable bit (R_en))
wherein each bit is associated with a transducer element of the plurality of transducer elements ([0071] the per-element logic can include a plurality of AND logic gates, where Tc[i] and T_en are used to provide Tc; Tr[j] and T_en are used to provide Tr, Rc[i]+Rr[j] and R_en are used to provide RxSw; Rc[i] and R_en are used to provide Rc; and Rr[j] and R_en are used to provide Rr. In this manner, the enable bits are used to control whether a particular element on a row and column is selected for activation)
and manipulate the plurality of bits to activate deactivated transducer elements of the plurality of transducer elements and/or deactivate activated transducer elements of the plurality of transducer elements based on the control signal ([0072] Column and row logic 420 provides the bits for column selection 401 and row selection 402 and can include at least one bank with registers 421 for storing a transmit or receive pattern. In the illustrated example, two banks 422, 424 are included, which in some implementations may be alternatingly selected using a "bankSel" control signal (which may be a clocked signal). For implementations using consolidated row and column select signals (e.g., where N I/O signals are available for the N.times.N (or N.times.M where N>M), a set of MUXes can be included as part of the column and row logic 420. A "mode" signal, provided by a controller, can select whether column or row selection is taking place)
Chen fails to teach a local oscillator configured to perform manipulation of the plurality of registers without a free running clock in the ultrasound imaging catheter.
However, Langford teaches a local oscillator configured to perform manipulation of the plurality of registers without a free running clock in the ultrasound imaging catheter ([0069] The receive amplifier 120 and the analog signal processor 118 in at least one embodiment are turned on with the oscillator 112 or turned on after a predetermined delay after the oscillator 112 is started. When there is a predetermined delay, power for contact lens operation may be lowered during the period of delay)
Chen and Langford are considered analogous because both disclose diagnostic applications of ultrasound. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the pending invention to utilize an oscillator for control of the diagnostic device in order to allow for a control system that is safe, low-cost, and reliable, has a low rate of power consumption and is scalable (Langford [0006]).
Regarding claim 4, Chen teaches the local oscillator is adapted to operate at a frequency that is greater than a bandwidth of the plurality of transducer elements ([table II] Bandwidth 10.2 MHz; [0073] the programming time…a 100 MHz clock)
Regarding claim 6, Chen teaches wherein the plurality of bits comprises a first bit and a second bit, wherein the plurality of registers are arranged into a plurality of register groups, each register group comprising a first register, comprising a first register bit; a second register, comprising a second register bit; and wherein a transducer element is associated with the first register bit, which is adapted to control whether the transducer element is activated or deactivated during the transmit period, and the second register bit, which is adapted to control whether the transducer element is activated or deactivated during the receive period ([0071] the control inputs are: i-th column (Rc[i]) and j-th row (Rd[j]) select signals from the sides; and per-element enable bit (R_en). The resultant local control signals are shown in FIG. 3B. As shown in FIG. 3B for the example implementation of the per-element logic block 310, the per-element logic can include a plurality of AND logic gates, where Tc[i] and T_en are used to provide Tc; Tr[j] and T_en are used to provide Tr, Rc[i]+Rr[j] and R_en are used to provide RxSw; Rc[i] and R_en are used to provide Rc; and Rr[j] and R_en are used to provide Rr. In this manner, the enable bits are used to control whether a particular element on a row and column is selected for activation)
Regarding claim 7, Chen teaches a plurality of output channels ([0072] For implementations using consolidated row and column select signals (e.g., where N I/O signals are available for the N.times.N (or N.times.M where N>M), a set of MUXes can be included as part of the column and row logic 420)
and wherein the plurality of bits comprises a third bit, wherein each register group further comprises a third register, comprising a third register bit, and wherein the transducer element is further associated with the third register bit, which is adapted to control which of the plurality of output channels a signal received at the transducer element is output to ([0071] the control inputs are: i-th column (Rc[i]) and j-th row (Rd[j]) select signals from the sides; and per-element enable bit (R_en). The resultant local control signals are shown in FIG. 3B. As shown in FIG. 3B for the example implementation of the per-element logic block 310, the per-element logic can include a plurality of AND logic gates, where Tc[i] and T_en are used to provide Tc; Tr[j] and T_en are used to provide Tr, Rc[i]+Rr[j] and R_en are used to provide RxSw; Rc[i] and R_en are used to provide Rc; and Rr[j] and R_en are used to provide Rr. In this manner, the enable bits are used to control whether a particular element on a row and column is selected for activation; [0073] The column-row-parallel architecture is both scalable and flexible. The columns and rows are reprogrammable for flexible 3D beam-formation (e.g., the select logic for the columns (column selection 401) and the select logic for the rows (row selection 402) can be reprogrammed quickly and frequently to activate different rows or columns for 3D beamforming))
Regarding claim 8, Chen teaches the plurality of register groups are connected in a daisy chain, wherein each register group is connected in series with an adjacent register group (see fig. 4a)
Regarding claim 9, Chen teaches a signal conditioning unit provided at the distal end of the ultrasound imaging catheter adapted to apply signal conditioning to the received ultrasound signals ([0062] The receiver LNA 142 is selectively connected (via connection 144) to the transducer element 121 in order to output a received signal to a shared variable gain amplifier (VGA) buffer 160. Similar to the configuration for the pulser gate drivers 150, the VGAs 160 are connected to the rows and the columns of transceiver elements 140).
Regarding claim 12, Chen teaches a processing unit in communication with the ultrasound imaging catheter ([0005] An ultrasonic imaging system with column-row-parallel architecture includes a N.times.M array of transducer elements; and a plurality of transceiver circuits. Each transceiver circuit is connected to a corresponding one transducer element of the N.times.M array of transducer elements. Each row and column of transceiver circuits share a common transmitter driver and a common variable gain amplifier (VGA) buffer, which can include an automatic offset cancelation feature)
and configured to generate an ultrasound image based on the received ultrasound signals ([0115] Using the delay-and-sum beamforming values, 3D images in complex value are formed for every Tx angle (1241-1 through 1241-p and 1242-1 through 1241-q). Coherent compounding is then carried out across all angles, by adding voxel values in complex domain (1250). The final compounded 3D image 1270 is obtained by taking the magnitude of the complex value voxels (envelope detection) (1260). Steps 1220, 1230, 1250, and 1260 may be carried out as a software process. The software process may be carried out at a computing device that processes the data received via the ASIC (e.g., at PC 1080 of FIG. 10B after being collected by a data acquisition unit 1070))
and a display adapted to display the ultrasound image ([0110] output from the CMUT-ASIC 1000/1010 is acquired by a data acquisition unit 1070 and provided to a computer 1080 for analysis and display); [0031] The volumetric images are displayed at 20 dB dynamic range).
Regarding claim 16, Chen teaches a local memory provided at the distal end of the ultrasound imaging catheter adapted to store a plurality of activation patterns ([0072] Column and row logic 420 provides the bits for column selection 401 and row selection 402 and can include at least one bank with registers 421 for storing a transmit or receive pattern)
wherein each activation pattern corresponds to a number of transducer elements of the plurality of transducer elements to be activated and a number of transducer elements of the plurality of transducer elements to be deactivated ([0072] two banks 422, 424 are included, which in some implementations may be alternatingly selected using a "bankSel" control signal (which may be a clocked signal). For implementations using consolidated row and column select signals (e.g., where N I/O signals are available for the N.times.N (or N.times.M where N>M), a set of MUXes can be included as part of the column and row logic 420. A "mode" signal, provided by a controller, can select whether column or row selection is taking place)
and wherein the control unit is further adapted to access the local memory ([0068] a CMUT array 200 can be stacked on a programmable ASIC 210 having a column input/output (I/O) logic 220 and row I/O logic 230)
select any one of the plurality of activation patterns; and generate a control signal to activate or deactivate the plurality of transducer elements of the transducer array according to the selected activation pattern during an imaging phase of the ultrasound imaging catheter, the imaging phase comprising a transmit period and a receive period ([0071] Since transmitter mode and receiver mode are independent and similar, the receiver mode can be used as an illustration of an operation of the transceiver channel. In this illustration, the control inputs are: i-th column (Rc[i]) and j-th row (Rd[j]) select signals from the sides; and per-element enable bit (R_en). The resultant local control signals are shown in FIG. 3B. As shown in FIG. 3B for the example implementation of the per-element logic block 310, the per-element logic can include a plurality of AND logic gates, where Tc[i] and T_en are used to provide Tc; Tr[j] and T_en are used to provide Tr, Rc[i]+Rr[j] and R_en are used to provide RxSw; Rc[i] and R_en are used to provide Rc; and Rr[j] and R_en are used to provide Rr. In this manner, the enable bits are used to control whether a particular element on a row and column is selected for activation; [0072] FIG. 4A illustrates control logic for a column-row-parallel ASIC architecture. Referring to FIG. 4A, a 2D array of transceivers 400 receive control signals (bits) for column selection 401 (e.g., Tc[i], Rc[i]), row selection 402 (e.g., Tr[j], Rr[j]), and per-element enable 410 (e.g., T_en, R_en). Column and row logic 420 provides the bits for column selection 401 and row selection 402 and can include at least one bank with registers 421 for storing a transmit or receive pattern. In the illustrated example, two banks 422, 424 are included, which in some implementations may be alternatingly selected using a "bankSel" control signal (which may be a clocked signal). For implementations using consolidated row and column select signals (e.g., where N I/O signals are available for the N.times.N (or N.times.M where N>M), a set of MUXes can be included as part of the column and row logic 420. A "mode" signal, provided by a controller, can select whether column or row selection is taking place)
Response to Arguments
Applicant's arguments filed 7/8/2026 have been fully considered but they are not persuasive. Applicant alleges that the office action fails to adequately address the limitations regarding the local oscillator configuration to activate and deactivate elements based on a control signal. Applicant addresses this point by first explaining what the inventor considers to be ‘active’ and ‘inactive’ based on the specification of the pending application and further cites the specification of the pending application to describe the function of the oscillator in the current invention. Applicant then further describes their interpretation of the oscillator disclosed in the Langford reference and the perceived differences between Langford’s disclosure and the specification of the pending application. Applicant concludes this argument by alleging that Langford’s oscillator performs burst generation rather than manipulation of a plurality of register bits. Paragraph [0069] of Langford reads “the receive amplifier 120 and the analog signal processor 118 are started with the oscillator 112, the receive amplifier 120 will receive an output from the receive ultrasound transducer 121 proximate to when the sound pressure wave is output by the transmit ultrasound transducer 116. This output from the receive ultrasound transducer 121 can be used to reset the counter in the digital signal processor 111”, and from this citation it is evident that the oscillator performs a manipulation of a system counter. Further, Paragraph [0094] reads “the ultrasound module 110 sends a signal to the system controller 130 to start the counter. When the counter has a time less than a predetermined time (or predetermined sampling period or time), the system controller 130 determines a blink has occurred” and paragraph [0095] reads “The system controller 130 in at least one embodiment stores the output in memory including in a further embodiment storing the output in a register”. When these citations are all read in tandem it appears that the oscillator causes a downstream effect on the registers of the Langford reference, and without a more concrete distinction of the particular “manipulation” being performed on the register bits, it could be understood that the oscillator in Langford plays a role in such a manipulation of registers.
It is crucial to note that the claim language as it is currently presented is significantly broader than the applicant seems to believe, and features from the specification are not meant to be read into the claims. It is noted that the features upon which applicant relies (i.e., the functionality of transducer element 0 in ultrasonic transmission and pulse reception; changing the stored transducer selection information that determines what elements are operational; the location of the local oscillator on the master die started by the HS unit) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
While the office appreciates the applicant’s explanation of the specification as it pertains to specific claim limitations, in order to differentiate the current application from the prior art, applicant is advised to incorporate some of these features listed in their remarks into the claims themselves. As the claim is currently drafted, the prior art is required to disclose a local oscillator that receives a signal command to manipulate bits and the only limitation on said signal is that it cannot be a free running clock, the particulars of this function is not required in addressing this claim limitation as it is currently drafted. Applicant is reminded that ‘based on the control signal’ is broad limitation and any manner of signal could be considered analogous to the control signal as it is claimed. Given that the Langford reference discloses a local oscillator which performs bit manipulation in response to a received signal, and further that there is nothing in the Langford reference to suggest this signal is a free running clock, then when taken into consideration with the primary Chen reference, the invention as claimed in the independent claim is obviated to one of ordinary skill in the art. For at least the aforementioned reasons, the claims remain rejected under 35 USC 103.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL VICTOR POPESCU whose telephone number is (571)272-7065. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Anne Kozak can be reached at (571) 270-0552. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GABRIEL VICTOR POPESCU/Examiner, Art Unit 3797
/SERKAN AKAR/Primary Examiner, Art Unit 3797
