DETAILED ACTION
Claim 16 has been cancelled.
Claims 1-15 and 17-20 are currently pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/31/26 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-15 and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 12-14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibuya US Publication 2013/0141403 (hereafter “Shibuya”).
Referring to claim 1, Shibuya discloses a gain modification device, comprising:
a plurality of gain modification circuitries whose number corresponds to a number of a plurality of channels of a plurality of signals, wherein the plurality of signals are simultaneously input in parallel to the plurality of gain modification circuitries (paragraph 115, the present invention can also be applied to a digital circuit for simultaneously outputting a plurality of digital data pieces through a plurality of signal lines arranged in parallel), each gain modification circuit of the plurality of gain modification circuitries is configured to modify a gain value used to amplify a corresponding signal of the plurality of signals based on a signal level of the corresponding signal (paragraph 9, the amplifier circuit 103 has four groups of amplifier circuits 103-1 to 103-240, 103-241 to 103-480, 103-481 to 103-720, and 103-721 to 103-960); and
a plurality of gain reflection control circuitries configured to sequentially perform gain adjustment for the plurality of signals by changing a timing at which the gain value is switched by the plurality of gain modification circuitries selectively for each channel of the plurality of channels (paragraph 9, The delay circuit 104 has four groups of delay circuits 104-1 to 104-240, 104-241 to 104-480, 104-481 to 104-720, and 104-721 to 104-960) such that:
the gain value of a first signal, of the plurality of signals and affecting a signal level of a second signal of the plurality of signals due to a load change during switching of the gain value (paragraph 14, the slope of the rising current waveform (dI/dt) causes noise in other signal lines due to the capacitive coupling (parasitic capacitance) and the mutual induction), is switched at a first timing (paragraph 10, At this time, the amplifier circuits 103-1 and 103-960 output the output voltage first), and
the gain value of the second signal is switched at a second timing different from the first timing which reduces changes in the signal level of the second signal (paragraph 10, the amplifier circuits 103-241 and 103-720 output the output voltage halfway), wherein
each gain reflection control circuit is further configured to set a variable degree of delay for the gain switching depending on a length of time during which the load change occurs when the gain value is switched (paragraph 85, In this embodiment, the time difference (delay time) of the delay circuit is controlled by the value of the capacitive load due to the length of the liquid crystal display panel signal line 12 on the film carrier, so that the drive timing of the amplifier circuit 3 is delayed).
Referring to claim 2, Shibuya discloses wherein the plurality of gain reflection control circuitries is further configure to determine that the gain value of the first signal is not to be switched by the plurality of gain modification circuitries (paragraph 21, Each of the output circuits (3-1 to 3-960) outputs the output voltage in response to each of the delay control signals).
Referring to claim 3, Shibuya discloses wherein the plurality of gain reflection control circuitries delays a timing at which the gain value of the first signal is to be switched by the plurality of gain modification circuitries (paragraph 21, Each of the output circuits (3-1 to 3-960) outputs the output voltage in response to each of the delay control signals).
Referring to claim 4, Shibuya discloses a signal processing unit comprising
the gain modification device according to claim 1,
wherein each one of the plurality of signals is a picture signal that is input for each one of a plurality of processing systems (paragraph 11, The outputs of the amplifier circuits 103-1 to 103-960 are coupled to data lines of the liquid crystal display panel coupled to nodes 105-1 to 105-960 through the signal lines 112, respectively).
Referring to claim 9, Shibuya discloses a method, comprising:
receiving a plurality of signals simultaneously in parallel by a plurality of gain modification circuitries whose number corresponds to a number of a plurality of channels of the plurality of signals (paragraph 115, the present invention can also be applied to a digital circuit for simultaneously outputting a plurality of digital data pieces through a plurality of signal lines arranged in parallel);
modifying, by each gain modification circuit of the plurality of gain modification circuitries, a gain value used to amplify a corresponding signal of the plurality of signals based on a signal level of the corresponding signal (paragraph 9, the amplifier circuit 103 has four groups of amplifier circuits 103-1 to 103-240, 103-241 to 103-480, 103-481 to 103-720, and 103-721 to 103-960); and
sequentially performing gain adjustment for the plurality of signals by changing a timing at which the gain value is to be switched in the modifying selectively for each channel of the plurality of channels (paragraph 9, The delay circuit 104 has four groups of delay circuits 104-1 to 104-240, 104-241 to 104-480, 104-481 to 104-720, and 104-721 to 104-960) such that:
the gain value of a first signal, of the plurality of signals and affecting a signal level of a second signal of the plurality of signals due to a load change during switching of the gain value (paragraph 14, the slope of the rising current waveform (dI/dt) causes noise in other signal lines due to the capacitive coupling (parasitic capacitance) and the mutual induction), is switched at a first timing (paragraph 10, At this time, the amplifier circuits 103-1 and 103-960 output the output voltage first), and
the gain value of the second signal is switched at a second timing different from the first timing which reduces changes in the signal level of the second signal (paragraph 10, the amplifier circuits 103-241 and 103-720 output the output voltage halfway),
wherein the changing the timing includes setting a variable degree of delay for the gain switching depending on a length of time during which the load change occurs when the gain value is switched (paragraph 85, In this embodiment, the time difference (delay time) of the delay circuit is controlled by the value of the capacitive load due to the length of the liquid crystal display panel signal line 12 on the film carrier, so that the drive timing of the amplifier circuit 3 is delayed).
Referring to claim 12, Shibuya discloses wherein the plurality of gain reflection control circuitries changes the timing by determining that the gain value of the first signal is not to be switched while the gain value of the second signal is switched (paragraph 10, the amplifier circuits 103-241 and 103-720 output the output voltage halfway).
Referring to claim 13, Shibuya discloses wherein after the gain value of the second signal is switched, the plurality of gain reflection control circuitries determines that the gain value of the second signal is not to be switched while the gain value of the first signal is switched (paragraph 10, At this time, the amplifier circuits 103-1 and 103-960 output the output voltage first [the amplifier 103-1 will output in a repeated manner to output the next screen to drive the display panel]).
Referring to claim 14, Shibuya discloses wherein the plurality of gain reflection control circuitries changes the timing by delaying the switching of the gain value of the first signal relative to the switching of the gain value of the second signal (paragraph 7, The delay unit 141 outputs the control signal CTR1 in order with a uniform delay to the first group of the amplifier circuits 136-1 to 136-(N/2)).
Referring to claim 17, Shibuya discloses wherein a variation between a ground and a power supply of the plurality of gain modification circuitries is based on the load change (paragraph 13, For this reason, when the output voltage is supplied to the panel load (the data line of the liquid crystal display panel) from AMP (amplifier circuit 103) through the tape shaped signal line (signal line 112), the load will increase as the signal line increases due to the influence of the parasitic capacitance Ci. Thus, the signal line 112 in the group of the range A is relatively long, so that the load is relatively large).
Referring to claim 18, Shibuya discloses a level detection circuit configured to detect a level of digital data output from an analog-to-digital converter coupled to an output of each of the plurality of gain modification circuitries, wherein
the gain value is determined based on the detected level (paragraph 76, The amplifier drive signal CTR controls the amplifier circuit 3 so that the amplifier circuit 3 amplifies the input signal (the output gradation voltage corresponding to the display data output from the D/A converter)).
Referring to claim 19, Shibuya discloses wherein changing the timing comprises deactivating switching of the gain value for the first signal while switching the gain value for the second signal (paragraph 10, the amplifier circuits 103-241 and 103-720 output the output voltage halfway).
Referring to claim 20, Shibuya discloses wherein changing the timing comprises delaying the switching of the gain value for the first signal for a predetermined length of time relative to the switching of the gain value for the second signal (paragraph 7, The delay unit 141 outputs the control signal CTR1 in order with a uniform delay to the first group of the amplifier circuits 136-1 to 136-(N/2)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya US Publication 2013/0141403 as applied to claim 4 above, and further in view of Kudo et al. US Publication 2018/0302571 (hereafter “Kudo”).
Referring to claim 5, Shibuya discloses the signal processing device according to claim 4, but does not disclose expressly the signal processing device being in a imaging device with a photoelectric converter.
Kudo discloses an imaging device comprising:
a photoelectric converter a photoelectric converter configured to convert an incident light into a signal and output the signal; and
the signal processing device,
wherein the signal output from the photoelectric conversion element is a picture signal of each color (paragraph 29-32, The image sensor 116 performs photoelectric conversion to the R light and generates an R-imaging signal that is an electrical signal. The image sensor 117 performs photoelectric conversion to the G light and generates a G-imaging signal that is an electrical signal. The image sensor 118 performs photoelectric conversion to the B light and generates a B-imaging signal that is an electrical signal. In the following description, the R-imaging signal, G-imaging signal, and B-imaging signal are also referred integrally to as RGB imaging signals that are electrical signals obtained by receiving white light. The image sensor 119 performs photoelectric conversion to the IR light and generates an IR imaging signal that is an electrical signal).
Before the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to use the signal processing device with a photoelectric converter. The motivation for doing so would have been to apply the noise reduction of Shibuya to an image reading device of Kudo capable of producing a scanned image. Therefore, it would have been obvious to combine Kudo with Shibuya to obtain the invention as specified in claim 5.
Referring to claim 6, Kudo discloses wherein the picture signal of each color includes:
a picture signal output upon receiving a visible light (paragraph 29-31, The image sensor 116 performs photoelectric conversion to the R light and generates an R-imaging signal that is an electrical signal. The image sensor 117 performs photoelectric conversion to the G light and generates a G-imaging signal that is an electrical signal. The image sensor 118 performs photoelectric conversion to the B light and generates a B-imaging signal that is an electrical signal. In the following description, the R-imaging signal, G-imaging signal, and B-imaging signal are also referred integrally to as RGB imaging signals that are electrical signals obtained by receiving white light), and
a picture signal output upon receiving an invisible light (paragraph 32, The image sensor 119 performs photoelectric conversion to the IR light and generates an IR imaging signal that is an electrical signal).
Referring to claim 7, Shibuya discloses an image reading device, comprising:
a light source to emit light (paragraph 4, In the liquid crystal display panel, the alignment of liquid crystal molecules varies according to the voltage applied to the liquid crystal capacitance from the outputs of the amplifier circuits. Thus, the transmittance of light varies accordingly); and
the imaging device according to claim 5.
Referring to claim 10, Shibuya discloses wherein the first and second signals are picture signals, but does not disclose expressly wherein the signals are output upon receiving light.
Kudo discloses wherein the first signal is a picture signal output upon receiving an invisible light, and
the second signal is a picture signal output upon receiving a visible light (paragraph 75 76, Specifically, in time period 301, the white light source 20 is turned on (white light is output), and the IR source 22 is turned off (IR light is not output). In time period 302 subsequent to the time period 301, the white light source 20 is turned off, and the IR source 22 is turned on).
Before the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to output a picture signal upon receiving visible and invisible light. The motivation for doing so would have been to enable receiving fluorescent pixels that are excited by infrared light that are common in medical images. Therefore, it would have been obvious to combine Kudo with Shibuya to obtain the invention as specified in claim 10.
Referring to claim 11, Kudo discloses wherein the invisible light is infrared light and the visible light includes red, green, and blue light (paragraph 21, The prism 111 is, for example, a dichroic prism which splits the reflective light and fluorescence from the subject P into three primary colors light, R (red) light, G (green) light, and B (blue) light).
Claims 5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Shibuya US Publication 2013/0141403 as applied to claim 4 above, and further in view of Asaba et al. US Publication 2016/0006961 (hereafter “Asaba”).
Referring to claim 5, Shibuya discloses the signal processing device according to claim 4, but does not disclose expressly the signal processing device being in a imaging device with a photoelectric converter.
Asaba discloses a photoelectric converter a photoelectric converter configured to convert an incident light into a signal and output the signal (paragraph 29, FIG. 1 is a diagram illustrating a photoelectric conversion element 10); and
the signal processing device according to claim 4,
wherein the signal output from the photoelectric conversion element is a picture signal of each color (paragraph 36, A plurality of pixels (three pixels of red, green, and blue) constitute a single column, and are connected to the shared PGA 140 via the switching elements).
Before the effective filing date of the claimed invention, it would have obvious to a person of ordinary skill in the art to use the signal processing device with a photoelectric converter. The motivation for doing so would have been to apply the noise reduction of Shibuya to an image reading device of Asaba capable of producing a printed scanned image. Therefore, it would have been obvious to combine Asaba with Shibuya to obtain the invention as specified in claim 5.
Referring to claim 8, Asaba discloses an image forming apparatus, comprising:
a printer (paragraph 65, The image forming unit 70 includes a processing unit 80 and a printer engine 82); and
the image reading device according to claim 7.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shibuya US Publication 2013/0141403 as applied to claim 14 above, and further in view of well known prior art.
Referring to claim 15, Shibuya discloses storing a value defining a length of the delay (paragraph 85, In this embodiment, the time difference (delay time) of the delay circuit is controlled by the value of the capacitive load due to the length of the liquid crystal display panel signal line 12 on the film carrier, so that the drive timing of the amplifier circuit 3 is delayed), but does not disclose expressly storing the value in a register.
Official Notice is taken that it is well known and obvious in the art to use a register to store data (See MPEP 2144.03). The motivation for doing so would have been to use standardized components that are cheap and widely available in order to efficiently store the value. Therefore, it would have been obvious to combine well known prior art with Shibuya to obtain the invention as specified in claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER K HUNTSINGER whose telephone number is (571)272-7435. The examiner can normally be reached Monday - Friday 8:30 - 5:00.
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/PETER K HUNTSINGER/Primary Examiner, Art Unit 2682
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