Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claims 1-30 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/05/2026 has been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, an initialed and dated copy of Applicant's IDS form SB08 filed 02/05/2026 is attached to the instant Office action.
Response to Amendment
This action is in response to the Amendment filled on 02/05/2026. No claims have been amended by Applicants.
Response to Arguments
Applicant's Arguments/Remarks filed on 02/05/2026 on page 7-9 regarding
35 U.S.C. 101 rejections have been fully considered and are found unpersuasive in view of presented Arguments/Remarks by the Applicants.
Applicant stated in page 9 in Arguments/Remarks: “insertion of the reflow modeling step at a specific point in the process sequence enables the improvement in the technical field of semiconductor device fabrication, … Applicant respectfully submits that the claims, as a whole, recite an improvement to a technical field,”.
Examiner respectfully disagrees with this argument/remark. Applicants argued about “an improvement to a technical field” in claim 1. However, no such technical improvement has been recited in claim limitations. Therefore, Applicant's Arguments/Remarks is not persuasive, accordingly the previous rejections
regarding 35 U.S.C.101 are being amended in this current office action. (See analysis below Claim Rejections-35 U.S.C. §101).
Applicant's Arguments/Remarks filed on 02/05/2026 on page 9-10 regarding
35 U.S.C. 103 rejections have been fully considered and are found persuasive in view of presented Arguments/Remarks by the Applicants. Specifically, the citation (Section 2.1 in Esfandyari disclosure being used in last office action to teach the limitation “the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed”.
In response to applicant's arguments/remarks, Examiner agrees that the previous citation Section 2.1 in Esfandyari disclosure doesn’t teach the abovementioned limitation. However, Esfandyari teaches this limitation in page 567 section 3.2. Please note, Under BRI Examiner would construe the claim element “a point during the process sequence for reflow modeling” as a constraint or threshold to perform the reflow modeling.
Esfandyari disclosed in page 567-568 section 3.2: “Initially (at t=0 sec) the PCB has a temperature of 300 K which is equal to the ambient temperature. To simulate the real process conditions, further settings and parameters have to be determined. Therefor the heat transfer coefficient (h) was calculated for each zone in the reflow oven, which are the preheating, the peak and the cooling zone (referring to the schematic process diagram). In each zone, a varying amount of heat is transferred. In reflow process, heat transfer occurs in combination of convection and radiation. The amount of heat transfer by convection can be described by equation 2. … The concluding step for the definition of boundary conditions was to implement the thermal profile in each zone over the process time.” The disclosure above “heat transfer coefficient (h) was calculated for each zone in the reflow oven” corresponds to claim limitation “the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed”.
However, a new ground of rejections is necessitated in this scenario, therefore, the previous rejections regarding 35 U.S.C.103 are being amended in this current office action. (See analysis below Claim Rejections-35 U.S.C. §103).
Examiner Notes
6. Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The entire reference is considered to provide disclosure relating to the claimed invention. The claims & only the claims form the metes & bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner's Notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent & spirit of compact prosecution.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a mental process or mathematical concept without significantly more.
Step 1
Claims 1-20 are directed to a non-transitory medium, which is a manufacture and is a statutory invention. Claims 21-28 are directed to a method, which is a process and is a statutory category invention. Claims 29-30 are directed to a system, which is a system and is a statutory invention. Therefore, claims 1-30 are directed to patent eligible categories of invention.
Step 2A, Prong 1
Independent claims 1, 21, and 29 as drafted, is a process that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “one or more processors,” “computing device,” and “non-transitory machine-readable medium,” nothing in the claim element precludes the step from practically being performed in the mind.
Accordingly, independent claims 1, 21, and 29 similarly recite perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run, which is an abstract idea and covers mental processes of assessing a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device, as described in [005] of the specification, because the claims are derived from Mental Processes based on concepts performed in the human mind or with the aid of pencil and paper.
Independent claims 1, 21, and 29 similarly recite performing the reflow modeling step within a region of the 3D structural model, the reflow modeling step generating reflow data, which is an abstract idea and covers mental processes of assessing predictive of a result of a physical fabrication of the semiconductor device structure, as described in [005] of the specification, because the claims are derived from Mental Processes based on concepts performed in the human mind or with the aid of pencil and paper.
Independent claims 1, 21, and 29 similarly recite performing the reflow modeling step within a region of the 3D structural model, the reflow modeling step generating reflow data, which is an abstract idea and covers mental processes of assessing predictive of a result of a physical fabrication of the semiconductor device structure, as described in [005] of the specification, because the claims are derived from Mental Processes based on concepts performed in the human mind or with the aid of pencil and paper.
Thus, the claims recite the abstract idea of a mental process performed in the human mind, or with the aid of pencil and paper.
Dependent claims 2-20, 22-28 and 30 further narrow the abstract ideas, identified in the independent claims. See analysis below.
Step 2A, Prong 2
The judicial exception is not integrated into a practical application. Claims 1, 21, and 29 similarly recite the additional limitation “non-transitory machine-readable medium,” as in independent claim 1 and dependent claims 2-20, “one or more processors,” as in independent claim 29, and “computing device,” as in independent claims 1, 21, and 29, this limitation does not integrate the judicial exception into a practical application because it is nothing more than generally linking the use of the judicial exception to a particular technological environment. See MPEP 2106.05(h). Alternatively, this additional element merely uses a computer device as a tool to perform the abstract idea. (MPEP 2106.05(f)).
The additional claim 1 limitation of receiving patient data, and a treatment plan comprising one or more appliances designed for treating a patient, only amounts to use of a computer or other machinery in its ordinary capacity for performing the steps of the abstract idea or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., mental process or certain methods of organizing human activity) does not integrate a judicial exception into a practical application. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed, only amounts to use of a computer or other machinery in its ordinary capacity for performing the steps of the abstract idea or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., mental process or certain methods of organizing human activity) does not integrate a judicial exception into a practical application. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of executing the process sequence up until the reflow modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, these additional elements are mere instructions to implement an abstract idea using a computer in its ordinary capacity, or merely uses the computer as a tool to perform the identified abstract idea. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of outputting the reflow data generated from the reflow modeling step, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and is not sufficient to integrate the judicial exception into a practical application. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception is not integrated into a practical application.
The additional claim 20 limitation of wherein the output reflow data is displayed in a 3D view, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and is not sufficient to integrate the judicial exception into a practical application. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception is not integrated into a practical application.
The additional claim 28 limitation of displaying the output reflow data in a 3D view, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and is not sufficient to integrate the judicial exception into a practical application. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception is not integrated into a practical application.
The additional claim 30 limitation of a display surface in communication with the at least one computing device, the display surface configured to display the reflow data, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and is not sufficient to integrate the judicial exception into a practical application. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception is not integrated into a practical application.
Dependent claims 2-20, 22-28 and 30 further narrow the abstract ideas, identified in the independent claims, and do not introduce further additional elements for consideration beyond those addressed above. The additional elements have been considered both individually and as an ordered combination in to determine whether they integrate the exception into a practical application. Therefore, the dependent claims do not integrate the claimed invention into a practical application.
Step 2B:
The claims do not amount to significantly more. The judicial exception does not amount to significantly more. Claims 1, 21, and 29 similarly recite the additional limitation “non-transitory machine-readable medium,” as in independent claim 1 and dependent claims 2-20, “one or more processors,” as in independent claim 29, and “computing device,” as in independent claims 1, 21, and 29, this limitation does not amount to significantly more because it is nothing more than generally linking the use of the judicial exception to a particular technological environment. See MPEP 2106.05(h). Alternatively, this additional element merely uses a computer device as a tool to perform the abstract idea. (MPEP 2106.05(f)).
The additional claim 1 limitation of receiving patient data, and a treatment plan comprising one or more appliances designed for treating a patient, only amounts to use of a computer or other machinery in its ordinary capacity for performing the steps of the abstract idea or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., mental process or certain methods of organizing human activity) and does not amount to significantly more. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed, only amounts to use of a computer or other machinery in its ordinary capacity for performing the steps of the abstract idea or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., mental process or certain methods of organizing human activity) and does not amount to significantly more. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of executing the process sequence up until the reflow modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, these additional elements are mere instructions to implement an abstract idea using a computer in its ordinary capacity, or merely uses the computer as a tool to perform the identified abstract idea and does not amount to significantly more. See MPEP 2106.05(f).
The additional claim 1 and similarly recited claims 21 and 29 limitation of outputting the reflow data generated from the reflow modeling step, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and does not amount to significantly more. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception does not amount to significantly more.
The additional claim 20 limitation of wherein the output reflow data is displayed in a 3D view, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and does not amount to significantly more. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception does not amount to significantly more.
The additional claim 28 limitation of displaying the output reflow data in a 3D view, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and does not amount to significantly more and is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception does not amount to significantly more.
The additional claim 30 limitation of a display surface in communication with the at least one computing device, the display surface configured to display the reflow data, can be viewed as is insignificant extra-solution activity, specifically pertaining to mere data gathering/output necessary to perform the abstract idea (MPEP 2106.05(g)) and does not amount to significantly more. This is akin to selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display, which has been identified as extra solution activity. Therefore, the judicial exception does not amount to significantly more.
Dependent claims 2-20, 22-28 and 30 further narrow the abstract ideas, identified in the independent claims, and do not introduce further additional elements for consideration beyond those addressed above. The additional elements have been considered both individually and as an ordered combination in to determine whether they integrate the exception into a practical application. Therefore, the dependent claims do not integrate the claimed invention into a practical application.
Therefore, the claims as a whole does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, when considered alone or in combination, do not amount to significantly more than the judicial exception.
As stated in Section I.B. of the December 16, 2014 101 Examination Guidelines, “[t]o be patent-eligible, a claim that is directed to a judicial exception must include additional features to ensure that the claim describes a process or product that applies the exception in a meaningful way, such that it is more than a drafting effort designed to monopolize the exception.”
The dependent claims include the same abstract ideas recited as recited in the independent claims, and merely incorporate additional details that narrow the abstract ideas and fail to add significantly more to the claims.
Dependent claim 2 recites “wherein, the reflow modeling step performs interface recognition,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 3 recites “wherein, the reflow modeling step performs surface curvature calculation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 4 a recites “wherein, the reflow modeling step performs net recognition,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 5 recites “wherein the reflow modeling step further performs voxel replacement in the 3D structural model,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 6 recites “wherein the reflow modeling step includes user-specified parameters indicative of a wafer to be operated on and a material for reflow,” which further narrows the abstract idea identified in the independent claim, which is directed to “Mental Process.”
Dependent claim 7 recite “wherein the reflow modeling step includes a user-specified parameter indicative of a radius to be used for surface curvature calculation,” which further narrows the abstract idea identified in the independent claim, which is directed to “Mental Process” or in the alternative “Mathematical Concepts.”
Dependent claim 8 recites “wherein the reflow modeling step includes a user-specified parameter indicative of a surface contact angle,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claims 9 recites “wherein the reflow modeling step is iteratively performed and includes a user-specified parameter defining a reflow total volume for each cycle,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 10 recites “wherein the reflow modeling step simulates metal reflow to repair a void in a via or trench caused by metal deposition,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 11 recites “wherein the reflow modeling step simulates metal reflow for bump/solder ball formation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 12 recites “wherein the reflow modeling step simulates Si reflow for Si nanowire formation,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 13 recites “wherein the reflow modeling step simulates thermal reflow for lense formation or surface smoothing for planarization material,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 14 recites “wherein the reflow modeling step performs local distance control of reflow modeling,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 15 recites “wherein the reflow modeling step includes a user-specified parameter for local distance control of reflow modeling,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 16 recites “wherein the reflow modeling step simulates the effect of gravity during reflow,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 17 recites “wherein the reflow modeling step includes a user-specified gravity parameter,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 18 recites “wherein the reflow modeling step includes multiple contact angles for multiple materials,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 19 recites “wherein the reflow modeling step includes user-specified parameters for multiple contact angles for multiple materials,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 22 recites “wherein the reflow modeling step further performs voxel replacement in the 3D structural model,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 23 recites “wherein the reflow modeling step includes one or more of user-specified parameters indicative of a wafer to be operated on and a material for reflow, a user-specified parameter indicative of a radius to be used for surface curvature calculation, and a user-specified parameter indicative of a surface contact angle,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 24 recites “wherein the reflow modeling step is iteratively performed and includes a user-specified parameter defining a reflow total volume for each cycle,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 25 recites “wherein the reflow modeling step includes a user-specified parameter for local distance control of reflow modeling,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 26 recites “wherein the reflow modeling step includes a user-specified gravity parameter to simulate the effect of gravity during reflow,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process.”
Dependent claim 27 recites “wherein the reflow modeling step includes user-specified parameters for multiple contact angles for multiple materials,” which further narrows the abstract idea identified in the independent claim, which is directed to a “Mental Process”.
Therefore, the claim 1-30 is not patent eligible under 35 USC 101.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham, v. John Deere Co., 383 U.S.1.148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
8. Claims 1,2,4-6,10,11,21,22, and 29 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over GREINER et al. (WO 2014159190 A1), (hereinafter GREINER) and in view of an NPL by A. Esfandyari et al. (Simulation, optimization and experimental verification of the over-pressure reflow soldering process) (hereinafter Esfandyari).
Regarding Claim 1, GREINER teaches a non-transitory medium holding computer-executable instructions for performing reflow modeling in a virtual fabrication environment, the instructions when executed causing at least one computing device (GREINER disclosed in para [007]: “An execution of the virtual metrology measurement step of a virtual fabrication run for semiconductor device structure generates virtual metrology measurement data.” In para [00107] “Portions or all of the embodiments of the present invention may be provided as one or more computer-readable programs or code embodied on or in one or more non-transitory mediums.”).
GREINER teaches receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated, (GREINER disclosed in para [0055]: “In one embodiment a computing device-implemented method of virtually fabricating a semiconductor device structure includes receiving a selection of a process sequence in a process editor for a structure to be virtually fabricated and adding a user supplied measurement locator shape to a layer in 2D design data for the structure.”).
GREINER teaches perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, (GREINER disclosed in para [0042-0043] “The measurement may be taken using a locator shape previously added to a layer in the 2D design data 30. In an alternative embodiment the measurement location may be specified by alternate means such as (x, y) coordinates in the 2D design data or some other means of specifying a location in the 2D design data 30 instead of through the use of a locator shape. This virtual metrology measurement capability is provided by embodiments of the present invention during the processing sequence to extract a critical physical dimension at the correct point in the integrated process flow.”).
GREINER teaches material addition and/or material removal steps performed to physically fabricate the semiconductor device structure, the virtual fabrication run: (GREINER disclosed in para [003]: “Attempts have been made to use conventional mechanical computer-aided design (CAD) tools and specialized technology CAD (TCAD) tools to model semiconductor device structures, with the goal of reducing the efforts spent on fabricating experimental wafers. General-purpose mechanical CAD tools have been found inadequate because they do not automatically mimic the material addition, removal, and modification processes that occur in an actual fab. TCAD tools, on the other hand, are physics-based modeling platforms (virtual fabrication run) that simulate material composition changes that occur during diffusion and implant processes, but not all of the material addition and removal effects (material addition and/or material removal steps) that occur during other processes that comprise an integrated process flow.” In para [0071] “Sputter behavior refers to direct physical removal of material through bombardment by energetic ions and results in preferential removal of protruding edges (convex edges) (physically fabricate the semiconductor device structure)) and in some cases corners. Sputtering may be modeled with two parameters: the angle of maximum sputter yield, and the rate of sputter relative to the rate of vertical etching.” Please see para [0043]).
GREINER teaches executing the process sequence up until the reflow modeling step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure, (GREINER disclosed in para [0090]: “The virtual fabrication run builds a 3D structural model with a crystalline substrate seed surface by executing the process sequence prior to an epitaxial growth step (step 2004)…If the epitaxial growth is complete (step 2011), the remainder of the 3D model is built by executing the process sequence that follows the epitaxial growth step (step 2012). If the epitaxial growth rate is not complete, the growth rates on the growing surface are recomputed and the growing surface is further advanced. The growing surface may be evolved in a time-based manner or a non-time based manner.”).
GREINER teaches outputting the reflow data generated from the reflow modeling step. (GREINER disclosed in para [0043]: “The output data from this virtual metrology measurement can be used to provide quantitative comparison to other modeling results or to physical metrology measurements (input and output data related to the physical or numerical simulation of the reflow process). This virtual metrology measurement capability is provided by embodiments of the present invention during the processing sequence to extract.”).
However, GREINER does not explicitly teach the limitation “the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed, or performing the reflow modeling step within a region of the 3D structural model, the reflow modeling step generating reflow data”.
Esfandyari teaches the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed; (Esfandyari disclosed in page 567-568 section 3.2: “Initially (at t=0 sec) the PCB has a temperature of 300 K which is equal to the ambient temperature. To simulate the real process conditions, further settings and parameters have to be determined. Therefor the heat transfer coefficient (h) was calculated for each zone in the reflow oven, which are the preheating, the peak and the cooling zone (referring to the schematic process diagram). In each zone, a varying amount of heat is transferred. In reflow process, heat transfer occurs in combination of convection and radiation. The amount of heat transfer by convection can be described by equation 2. … The concluding step for the definition of boundary conditions was to implement the thermal profile in each zone over the process time.” The disclosure above “heat transfer coefficient (h) was calculated for each zone in the reflow oven” corresponds to claim limitation “the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed”.
Esfandyari teaches performing the reflow modeling step within a region of the 3D structural model, the reflow modeling step generating reflow data; (Esfandyari disclosed in page 566 under heading ‘Introduction’ (left col.): “Thus, maintaining temperature uniformity across the board is important so that the solder joints at different positions in the package can be simultaneously reflowed. Inoue and Koyanagawa built the FEM model to obtain the temperature distribution of a BGA package for the reflow process. The average heat-transfer coefficient havg was calculated using experimental equations. However, the experimental results obtained by Illés showed that the heat transfer coefficient (h) was inconsistent within the reflow oven. This paper presents an attempt to simulate the heating process in an over-pressure convection oven by finite element model. This model can be used to predict the temperature distribution for the components on PCB substrates. Experimental design has been carried out to investigate the temperature profile for selected thermal points on the PCB components. The void fraction in solder material is investigated by the X-Ray analysis and hence, the optimized relation between the process set-up parameters in the oven and the created voids in the solder material are derived.”).
GREINER and Esfandyari are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER and Esfandyari, to modify the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed in GREINER’s teaching, to include the benefits of doing so ensures absolutely reproducible, virtually void-free solder joints Esfandyari’s teaching. The suggestion/motivation for doing so would have been obvious by Esfandyari because “An over-pressure reflow oven as shown in Fig. 1 is used to perform the experiments. his new concept ensures absolutely reproducible, virtually void-free solder joints. This innovative concept forces the residual gases i.e. voids to escape the solder connections.” (Esfandyari disclosed in page 566 Section 2.1 heading ‘Over-pressure reflow soldering process’ (right col.)).
Regarding Claim 2, GREINER and Esfandyari teach the medium of claim 1 wherein, GREINER teaches the reflow modeling step performs interface recognition. (GREINER disclosed in para [0052] “The virtual metrology data 80 may be exported to a automatic data analysis tool for further processing or may be displayed to a user through a user interface such as the tabular and graphical metrology results view 124 or other view (step 512b).”).
Regarding Claim 4, GREINER and Esfandyari teach the medium of claim 1 wherein, GREINER teaches the reflow modeling step performs net recognition. (GREINER disclosed in para [0055] “As explained further below, process sequence 240 may include one or more electrical behavior modeling steps 245, 249 that indicate a point in the process sequence during a virtual fabrication run at which a determination of electrical behavior in a designated region of a 3D structural model will be made by the electrical modeling engine 279.” In para [0058] “Areas enclosed by shapes or polygons on each layer may represent regions where a photoresist coating on a wafer may be either exposed to light or protected from light during a photolithography step in the integrated process flow. The shapes on one or more layers may be combined (booleaned) to form a mask that is used in a photolithography step.” Further, in para [0062] “Some steps in the process sequence may be used to identify regions in the 3D virtual fabrication model that are relevant to electrical behavior modeling. In one embodiment the 3D modeling engine may automatically divide the partially built 3D structural model into electrical 'nets' of connected conductive material. These nets may, for instance, connect ports for individual devices such as transistors, capacitors, resistors, memory etc. that are located in the designated region of the 3D structural model.”).
Regarding Claim 5, GREINER and Esfandyari teach the medium of claim 1 wherein GREINER teaches the reflow modeling step further performs voxel replacement in the 3D structural model. (GREINER disclosed in para [0066] “In an illustrative embodiment, the 3D modeling engine 75 represents the underlying structural model in the form of voxels. Voxels are essentially 3D pixels. Each voxel is a cube of the same size, and may contain one or more materials, or no materials. Most of the operations performed by the 3D modeling engine in the embodiment are voxel modeling operations (inclusive of voxel replacements). Those skilled in the art will recognize that the 3D modeling engine 75 may also represent the structural model in other formats. For instance, the 3D modeling engine could use a conventional NURBS-based solid modeling kernel such as is used in 3D mechanical CAD tools, although modeling operations based on a digital voxel representation are far more robust than the corresponding operations in a conventional analog solid modeling kernel. Such solid modeling kernels generally rely on a large number of heuristic rules to deal with various geometric situations (inclusive of voxel replacements), and modeling operations may fail when the heuristic rules do not properly anticipate a situation. Aspects of semiconductor structural modeling that cause problems for NURBS-based solid modeling kernels include the very thin layers produced by deposition processes and propagation of etch fronts that results in merging faces and/or fragmentation of geometry”).
Regarding Claim 6, GREINER and Esfandyari teach the medium of claim 1 wherein GREINER teaches the reflow modeling step includes user-specified parameters indicative of a wafer to be operated on and a material for reflow. (GREINER disclosed in para [0026] “Figure 17 depicts an exemplary process editor displaying input parameters for a silicon wafer that defines the orientation of the crystalline lattice within the wafer relative to the 3D coordinate system used in the virtual fabrication environment of the present invention.” In para [0087] “Figure 17 depicts an exemplary process editor displaying input parameters for a silicon wafer that defines the orientation of the crystalline lattice within the wafer relative to the 3D coordinate system used in the virtual fabrication environment of the present invention. The crystalline orientation has an essential impact on subsequent selective epitaxy processes. The process editor accepts input defining parameters associated with the silicon wafer. The input parameters surface plane 1702, notch vector 1704 and notch design direction 1706 together define the orientation of the crystalline lattice relative to the 3D model coordinate system.” Please see Figure 17:
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Regarding Claim 10, GREINER and Esfandyari teach the medium of claim 1, however, GREINER does not explicitly teach the limitation “the reflow modeling step simulates metal reflow to repair a void in a via or trench caused by metal deposition”.
wherein Esfandyari teaches the reflow modeling step simulates metal reflow to repair a void in a via or trench caused by metal deposition. (Esfandyari disclosed in page 565 heading ‘Introduction’ (left col.): “The reflow thermal profile can be divided into four stages namely preheating, soaking, peak, and cooling stages. An adequate set-up i.e. proper heating and cooling gradients during the process stages will avoid several soldering defects. A minimized soaking zone for example can lead to reduced voiding, good wetting, reduces solder balling and open connections.”).
GREINER and Esfandyari are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER and Esfandyari, to modify the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed in GREINER’s teaching, to include the benefits of doing so ensures absolutely reproducible, virtually void-free solder joints Esfandyari’s teaching. The suggestion/motivation for doing so would have been obvious by Esfandyari because “An over-pressure reflow oven as shown in Fig. 1 is used to perform the experiments. his new concept ensures absolutely reproducible, virtually void-free solder joints. This innovative concept forces the residual gases i.e. voids to escape the solder connections.” (Esfandyari disclosed in page 566 Section 2.1 heading ‘Over-pressure reflow soldering process’ (right col.)).
Regarding Claim 11, GREINER and Esfandyari teach the medium of claim 1, however, GREINER does not explicitly teach the limitation “the reflow modeling step simulates metal reflow for bump/solder ball formation”.
wherein Esfandyari teaches the reflow modeling step simulates metal reflow for bump/solder ball formation. (Esfandyari disclosed in page 565 heading ‘Introduction’ (2nd para): “The reflow thermal profile can be divided into four stages namely preheating, soaking, peak, and cooling stages. An adequate set-up i.e. proper heating and cooling gradients during the process stages will avoid several soldering defects. A minimized soaking zone for example can lead to reduced voiding, good wetting, reduces solder balling and open connections. The use of low peak temperature lessens charring, delamination, intermetallic formations, leaching and void building. A rapid cooling rate helps reducing intermetallics, charring, leaching and grain size.”).
GREINER and Esfandyari are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER and Esfandyari, to modify the process sequence including a user-specified reflow modeling step, the reflow modeling step indicating a point during the process sequence for reflow modeling to be performed in GREINER’s teaching, to include the benefits of doing so ensures absolutely reproducible, virtually void-free solder joints Esfandyari’s teaching. The suggestion/motivation for doing so would have been obvious by Esfandyari because “An over-pressure reflow oven as shown in Fig. 1 is used to perform the experiments. his new concept ensures absolutely reproducible, virtually void-free solder joints. This innovative concept forces the residual gases i.e. voids to escape the solder connections.” (Esfandyari disclosed in page 566 Section 2.1 heading ‘Over-pressure reflow soldering process’ (right col.)).
Regarding Claim 21, the same ground of rejection is made as discussed in claim 1 for substantially similar rationale, therefore claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER and Esfandyari as discussed above for substantially similar rationale. In addition, claim 21 recites following limitation:
GREINER teaches a computing device-implemented method for performing reflow modeling in a virtual fabrication environment, (GREINER disclosed in para [006]: “In one embodiment a computing device-implemented method of virtually fabricating a semiconductor device structure includes receiving a selection of a process sequence in a process editor for a structure to be virtually fabricated and adding a user supplied measurement locator shape to a layer in 2D design data for the structure.” [007]: “An execution of the virtual metrology measurement step of a virtual fabrication run for semiconductor device structure generates virtual metrology measurement data.”).
Regarding Claim 22, GREINER and Esfandyari teach the method of claim 21, is incorporating the rejections of claim 5, because claim 22 has substantially similar claim language as claim 5, therefore claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER and Esfandyari as discussed above for substantially similar rationale.
Regarding Claim 29, the same ground of rejection is made as discussed in claim 1 for substantially similar rationale, therefore claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER and Esfandyari as discussed above for substantially similar rationale. In addition, claim 29 recites following limitation:
GREINER teaches a system for performing reflow modeling in a virtual fabrication environment, (GREINER disclosed in para [007]: “In another embodiment, a virtual fabrication system includes a computing device equipped with a processor and configured to receive input data for a 3D modeling engine. … An execution of the virtual metrology measurement step of a virtual fabrication run for semiconductor device structure generates virtual metrology measurement data.”).
Claims 3,7,16,17, and 26 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over GREINER and Esfandyari, in further view of a journal “A reflow process for glass microlens array fabrication by use of precision compression molding”, by Yang Chen et al. (hereinafter Chen).
Regarding Claim 3, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step performs surface curvature calculation”.
wherein, Chen teaches the reflow modeling step performs surface curvature calculation. (Chen disclosed in page 4 section 3 (right col.): “The geometry and the boundary conditions used in the reflow model are shown in figure 8. It was assumed that the surface tension induced deformation is local to the microlens. The fluid domain (i.e., glass) is axisymmetric. Due to this axis symmetry, only half a cross-section is shown in the model. The boundary conditions on the symmetries are zero normal velocity and zero tangential stress, i.e., vn = ˆn · v = 0 and fs = ˆn · σ · ˆs = 0, where ˆn and ˆs are unit normal and tangential vectors and σ is the total stress tensor.”).
GREINER, Esfandyari and Chen are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Chen, to modify reflow modeling in GREINER’s teaching, to include the reflow modeling step by performing surface curvature calculation in Chen’s teaching. The suggestion/motivation for doing so would have been obvious by Chen because “A new method for high-volume microlens array production using P-SK57 glass was presented by combining the glass compression molding and thermal reflow processes. According to the experimental results, a desirable microlens curve could be obtained within the temperature range with a 400 s holding time. The method presented in this study may be used for fabricating glass microlens arrays with controllable diameters and sagittal height with good optical performance and, the new process is suitable for mass production of various micro glass optical elements at a low cost”. (Chen disclosed in page 7 section 5).
Regarding Claim 7, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes a user-specified parameter indicative of a radius to be used for surface curvature calculation”.
wherein Chen teaches the reflow modeling step includes a user-specified parameter indicative of a radius to be used for surface curvature calculation. (Chen disclosed in page 4 section 3 (right col.): “The geometry and the boundary conditions used in the reflow model are shown in figure 8. It was assumed that the surface tension induced deformation is local to the microlens. The fluid domain (i.e., glass) is axisymmetric. Due to this axis symmetry, only half a cross-section is shown in the model. The boundary conditions on the symmetries are zero normal velocity and zero tangential stress, i.e., vn = ˆn · v = 0 and fs = ˆn · σ · ˆs = 0, where ˆn and ˆs are unit normal and tangential vectors and σ is the total stress tensor.”).
GREINER, Esfandyari and Chen are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Chen, to modify reflow modeling in GREINER’s teaching, to include the reflow modeling step by performing surface curvature calculation in Chen’s teaching. The suggestion/motivation for doing so would have been obvious by Chen because “A new method for high-volume microlens array production using P-SK57 glass was presented by combining the glass compression molding and thermal reflow processes. According to the experimental results, a desirable microlens curve could be obtained within the temperature range with a 400 s holding time. The method presented in this study may be used for fabricating glass microlens arrays with controllable diameters and sagittal height with good optical performance and, the new process is suitable for mass production of various micro glass optical elements at a low cost”. (Chen disclosed in page 7 section 5).
Regarding Claim 16, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “wherein the reflow modeling step simulates the effect of gravity during reflow”.
wherein Chen teaches the reflow modeling step simulates the effect of gravity during reflow. (Chen disclosed in page 4 section 3 (1st para left col.): “Reflow of a molten glass article can be driven by gravity and/or surface tension. The relative importance of each factor depends on the size of the flow domain”).
GREINER, Esfandyari and Chen are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Chen, to modify reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step by performing surface curvature calculation in Chen’s teaching. The suggestion/motivation for doing so would have been obvious by Chen because “A new method for high-volume microlens array production using P-SK57 glass was presented by combining the glass compression molding and thermal reflow processes. According to the experimental results, a desirable microlens curve could be obtained within the temperature range with a 400 s holding time. The method presented in this study may be used for fabricating glass microlens arrays with controllable diameters and sagittal height with good optical performance and, the new process is suitable for mass production of various micro glass optical elements at a low cost”. (Chen disclosed in page 7 section 5).
Regarding Claim 17, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes a user- specified gravity parameter”.
wherein Chen teaches the reflow modeling step includes a user- specified gravity parameter. (Chen disclosed in page 4 section 3 (1st para left col.): “Reflow of a molten glass article can be driven by gravity and/or surface tension. The relative importance of each factor depends on the size of the flow domain”).
GREINER, Esfandyari and Chen are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Chen, to modify reflow modeling in GREINER’s teaching, to include the reflow modeling step by performing surface curvature calculation in Chen’s teaching. The suggestion/motivation for doing so would have been obvious by Chen because “A new method for high-volume microlens array production using P-SK57 glass was presented by combining the glass compression molding and thermal reflow processes. According to the experimental results, a desirable microlens curve could be obtained within the temperature range with a 400 s holding time. The method presented in this study may be used for fabricating glass microlens arrays with controllable diameters and sagittal height with good optical performance and, the new process is suitable for mass production of various micro glass optical elements at a low cost”. (Chen disclosed in page 7 section 5).
Regarding Claim 26, GREINER and Esfandyari teach the method of claim 21, is incorporating the rejections of claim 16, because claim 26 has substantially similar claim language as claim 16, therefore claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER, Esfandyari and in view of Chen as discussed above for substantially similar rationale.
Claims 8, 9, 12, 13, 18-20, 24, 27, 28, and 30 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over GREINER, and Esfandyari, in further view of an NPL paper “3D Resist Reflow Compact Model for Imager Microlens Shape Optimization” by Bergery et al. (hereinafter Bergery).
Regarding Claim 8, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes a user-specified parameter indicative of a surface contact angle”.
wherein Bergery teaches the reflow modeling step includes a user-specified parameter indicative of a surface contact angle. (Bergery disclosed in page 3 section 2.2.1 heading ‘Physical Limitations’: “The resist reflow process could be seen, in simple term, as a process in which the vertical walls and edges of a resist pattern are smoothed to create a spherical structure. … since some physical constraints occur in the process of forming such complex 3D profiles. Result might as well be a hemisphere or an intermediate, transient state. This could depend on materials properties such as adhesion forces, wettability at the interfaces or the critical contact angle value at the intersection resist – substrate – ambient air.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 9, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step is iteratively performed and includes a user-specified parameter defining a reflow total volume for each cycle”.
wherein Bergery teaches the reflow modeling step is iteratively performed and includes a user-specified parameter defining a reflow total volume for each cycle. (Bergery disclosed in page 1 heading ‘Abstract’: “The method consists in melting previously patterned photoresist dots in order to form the lenses. But the resist shaping into a microlens is not as straight forward, since the final microlens needs to match shaping criteria to maximize the device optical efficiency. The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work.” In page 4 section 2.2.2 (1st para): “Given all of these listed elements, one can envisioned that the melt of a resist pattern is a much more complex process as it first seems. From one photoresist polymer, one technological stack, one melt process and one initial resist pattern, all of them combined will lead to one particular and fix final shape. That is why the knowledge and definition of the initial resist blocks is a crucial point when manufacturing microlens. The determination of this optimized starting point is classically an empirical work in the fab.”
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GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 12, GREINER and Esfandyari teach the medium of claim 1 however, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step simulates Si reflow for Si nanowire formation”.
wherein Bergery teaches the reflow modeling step simulates Si reflow for Si nanowire formation. (Bergery disclosed in page 9 section 3.4: “To be predictive, the morphing operator implemented is 3D sensitive in a sense that it is actually varying throughout the pattern height. Indeed, it has to correctly represent the resist contraction on top of the pattern as well as the spreading of its bottom line. In order to accurately reproduce such considerations, the thermal resist reflow was approached like a diffusion type problem to be solved in the spectral domain.” In same page section 4.1: “All the experimental data presented in this paper have been obtained on 300mm short-loop wafers using a simplified lithography stack. A 300nm thickness of bottom anti-reflective has been spin-coated on a silicon substrate. … The compact model in the reflow simulation tool is calibrated on experimental data collected after lithography and melt steps.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 13, GREINER and Esfandyari teach the medium of claim 1 wherein GREINER teaches for lense formation or surface smoothing for planarization material. (GREINER disclosed in para [0094]: “it is apparent that many additional 2D DRCs are required to satisfy a criterion that is very simple to state in 3D: that the contact area between metal lines and vias must exceed a specified threshold value. The 2D DRC situation becomes even more complex when one considers that multiple manufacturing variations can affect the contact area, including over or under-exposure during lithography steps, mis-registration of the masks, planarization (via chemical mechanical polishing (CMP)) (lense formation or surface smoothing for planarization material) of the via layer, and the sidewall tapers produced by plasma etching.”).
However, GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step simulates thermal reflow”.
Bergery teaches the reflow modeling step simulates thermal reflow (Bergery disclosed in page 2 Section 2.1: “The formation of microlenses has been a large and active field of study for years. Many fabrication methods exist to manufacture microlens [2] - [5]. The most widely used by the semiconductor industry is the photoresist reflow method, as proposed by Popovic [6]. It is a cost effective process solution since it is a combination of photolithography and annealing steps, requiring an exposure tool and a hot plate – quite common tools in a production fab environment. The resist thermal reflow (thermal reflow) is a phenomenon …”. In page 7 Section 3.2 (2nd para): “To be compatible with an industrial production context where a fine and fast optimization is needed, a reflow modelling software must quickly give simulation outputs” (reflow modeling step simulates). Further, in page 14 Section 5.1: “A total of 200 CD-SEM images have been used for characterizing the lithography state for the above patterns (25 dies inspected), as well as 32 AFM scans (4 dies scanned for each of them). Octagon shapes (regular or not) are classical designs when defining microlens arrays, which is why this particular pattern has been included.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 18, GREINER and Esfandyari teach the medium of claim 1 however GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes multiple contact angles for multiple materials”.
wherein Bergery teaches the reflow modeling step includes multiple contact angles for multiple materials. (Bergery disclosed in page 3 section 2.2.1 (1st para): “The resist reflow process could be seen, in simple term, as a process in which the vertical walls and edges of a resist pattern are smoothed to create a spherical structure. … since some physical constraints occur in the process of forming such complex 3D profiles. Result might as well be a hemisphere or an intermediate, transient state. This could depend on materials properties such as adhesion forces, wettability at the interfaces or the critical contact angle value at the intersection resist – substrate – ambient air.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 19, GREINER and Esfandyari teach the medium of claim 18 however GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes user-specified parameters for multiple contact angles for multiple materials”.
wherein Bergery teaches the reflow modeling step includes user-specified parameters for multiple contact angles for multiple materials. (Bergery disclosed in page 3 section 2.2.1 (1st para): “The resist reflow process could be seen, in simple term, as a process in which the vertical walls and edges of a resist pattern are smoothed to create a spherical structure. … since some physical constraints occur in the process of forming such complex 3D profiles. Result might as well be a hemisphere or an intermediate, transient state. This could depend on materials properties such as adhesion forces, wettability at the interfaces or the critical contact angle value at the intersection resist – substrate – ambient air.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claim 20, GREINER and Esfandyari teach the medium of claim 1 however GREINER and Esfandyari do not explicitly teach the limitation “the output reflow data is displayed in a 3D view”.
wherein Bergery teaches the output reflow data is displayed in a 3D view. (Bergery disclosed in page 16 section 5.2: “Figure 20 displays some of the graphical representations obtained at the end of the verification flow for the octagons patterns, with a progressive increment in CD.” Please see Figure 20 and Figure 22).
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GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Regarding Claims 24,27 and 28, GREINER and Esfandyari teach the method of claim 21, are incorporating the rejections of claims 9,19 and 20 respectively, because claims 24,27 and 28 have substantially similar claim language as claims 9,19 and 20, therefore claims 24,27 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over GREINER, Esfandyari and in view of Bergery as discussed above for substantially similar rationale.
Regarding Claim 30, GREINER and Esfandyari teach the system of claim 29 however GREINER and Esfandyari do not explicitly teach the limitation “a display surface in communication with the at least one computing device, the display surface configured to display the reflow data”.
further Bergery teaches a display surface in communication with the at least one computing device, the display surface configured to display the reflow data. (Bergery disclosed in page 2 heading ‘Introduction’: “Image sensors comprise large pixel arrays, themselves composed of thousands of unitary pixels. The pixel is thus the main component of a CMOS image sensor. A pixel consists of a silicon photodiode area responsible of the photon collection, and a second neighboring transistors area which measures the charges generated by and transferred from the photodiode. The photodiode is the only light-sensitive element of the pixel, which means not all the pixel surface actively participates in the photon collection.” In page 16 Section 5.2: “While performing a verification, we are interested in checking if our compact model solution is able to correctly predict the 3D shaping of patterns either through shapes and/or CD variations. Figure 20 displays some of the graphical representations obtained at the end of the verification flow for the octagons patterns, with a progressive increment in CD.”).
GREINER, Esfandyari and Bergery are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Bergery, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step includes user-specified parameter related to surface contact angle in Bergery’s teaching. The suggestion/motivation for doing so would have been obvious by Bergery because “The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps.” (Bergery disclosed in page 1 heading ‘Abstract’).
Claim 23 is rejected under are rejected under 35 U.S.C. 103 as being unpatentable over GREINER, Esfandyari, Chen and Bergery.
Regarding Claims 23, GREINER and Esfandyari teach the method of claim 21, is incorporating the rejections of claims 6,7 and 8, because claim 23 has substantially similar claim language/limitations as claims 9,19 and 20, therefore claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER, Esfandyari, Chen and Bergery as discussed above for substantially similar rationale.
Claims 14, 15, and 25 are rejected under are rejected under 35 U.S.C. 103 as being unpatentable over GREINER and Esfandyari and in further view of an NPL paper “Improvement of Process Control using Wafer Geometry for Enhanced Manufacturability of Advanced Semiconductor Devices” by H. Lee et al. (hereinafter Lee).
Regarding Claim 14, GREINER and Esfandyari teach the medium of claim 1 however GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step performs local distance control of reflow modeling”.
wherein Lee teaches the reflow modeling step performs local distance control of reflow modeling. (Lee disclosed in page 2 heading ‘Introduction’: “Thus by controlling the IPD contribution of the upstream processes, it is possible to control the overlay at downstream lithography operations. Also, when controlling the IPD contribution of upstream processes is challenging, it may be possible to generate scanner corrections based on the IPD data for feeding forward to the scanner to be applied at the downstream lithography operation, likely in combination with the typical scanner corrections. Another key metric is local shape curvature (LSC), which qualifies the stress within a localized region on a wafer from shape changes within that localized region of the wafer.”
GREINER, Esfandyari and Lee are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Lee, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step performs local distance control of reflow modeling in Lee’s teaching. The suggestion/motivation for doing so would have been obvious by Lee because “Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM.” (Lee disclosed in page 1 heading ‘Abstract’).
Regarding Claim 15, GREINER and Esfandyari teach the medium of claim 15 however GREINER and Esfandyari do not explicitly teach the limitation “the reflow modeling step includes a user- specified parameter for local distance control of reflow modeling”.
wherein Lee teaches the reflow modeling step includes a user- specified parameter for local distance control of reflow modeling. (Lee disclosed in page 94240M-9 heading ‘Conclusion’: “We used high-resolution wafer geometry measurements and the in-plane distortion (IPD) metric to monitor process induced overlay errors in a production flow. The technique provided sufficient throughput for monitoring wafers in a high volume manufacturing setting. Process steps that induced significant overlay errors and those that led to substantial wafer-to-wafer variation were identified using wafer geometry monitoring. A PECVD process step that led to significant overlay errors was selected for process optimization. Tool-to-tool and station-to-station variability was characterized using the local shape curvature (LSC) metric that relates to stress non-uniformities induced by wafer processing. Process settings that enable optimized overlay contribution from the PECVD process were determined using IPD and LSC monitoring.”).
GREINER, Esfandyari and Lee are analogous art because they are related to deal with experimental wafers that are used in a trial-and-error scheme to develop individual processes for the fabrication of a device structure and also to develop the total, integrated process flow in a virtual fabrication environment. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of GREINER, Esfandyari and Lee, to modify the reflow modeling in GREINER and Esfandyari’s teaching, to include the reflow modeling step performs local distance control of reflow modeling in Lee’s teaching. The suggestion/motivation for doing so would have been obvious by Lee because “Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM.” (Lee disclosed in page 1 heading ‘Abstract’).
Regarding Claim 25, GREINER and Esfandyari teach the method of claim 21, is incorporating the rejections of claim 15, because claim 25 has substantially similar claim language as claim 15, therefore claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over GREINER, Esfandyari and in view of Lee as discussed above for substantially similar rationale.
Conclusion
9. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure. An NPL paper “CFD Aided Reflow Oven Profiling for PCB Preheating in a Soldering Process” by Ilja Belov et al. focused on the development and application of a reflow oven profile prediction algorithm, which combines both the analytic approach and computational fluid dynamics. Modelling results for preheating of a populated PCB with non-uniform distribution of component thermal mass in an air convection reflow oven. The algorithm provides reliable prediction of both the reflow oven profile and the PCB preheating profile, provided that the validated CFD model of the solder reflow oven and a high-quality PCB model are availabe as the input. The main idea of the algorithm is to fit the one dimensional function for the temperature rise in a material during the heat cycle to the CFD calculated temperature data for the coldest and the hottest reference points on the PCB, with the local time constant as the curve fitting parameter.
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/NUPUR DEBNATH/Examiner, Art Unit 2186
/RENEE D CHAVEZ/Supervisory Patent Examiner, Art Unit 2186
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