DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim Objections
Applicant has amended the claims at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Prior Art Rejections
Applicant's arguments filed 12/28/2025 have been fully considered but they are not persuasive.
Applicant asserts Onufryk is silent that “integer portions of OSC CONFIG signals are coprime”, discussing the number of fan-out circuits and number of generated oscillating signals are not coprime. Examiner respectfully disagrees. The scope of the claim language does not require the integer portions of the control words to only/always be coprime, but rather comprises when the control words are coprime. Thus, prior art may apply to the claim, provided that it teaches and suggests scenarios when the control signals are coprime, regardless as to whether the control signals are always coprime. As an example, Onufryk bit source operators may be 5 stages each as shown in Fig. 5 (N = {1, 3, 5} and fan-out = {1, 2, 3}), thus when OSC CONFIG sends control signals such that each bit oscillator is a different frequency, OSC CONFIG will be coprime between each pair of bit oscillator. It follows that for bit oscillators with more than 5 stages, there will be at least one set of OSC CONFIG values such that they are coprime to each other. Therefore, Onufryk does teach when control words are coprime.
Applicant asserts Onufryk is silent to each of the random bit streams includes a first frequency signal and a second frequency signal, and OSC CONFIG signals can control the occurrence probability of the first frequency signal and the second frequency signal. Examiner respectfully disagrees. Onufryk teaches selecting a higher frequency signal susceptible to jitter (col 3 lines 60-64) along with a relative jitter-free lower frequency signal (col 5 lines 31-36). It follows that a frequency with jitter will have a different occurrence probability than one without jitter. Thus, the act of selecting a higher frequency signal, for the multiplexer, influences the occurrence probability of the output multiplexer frequency, while selecting the lower frequency signal is controlled to be fifty percent duty cycle.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: storage module, processing module, operation module in claim 9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
As to claim 9’s storage module, the examiner interprets the means plus function limitation to the corresponding structure: shift register as disclosed in [00148], Fig. 11 of the applicant’s specification.
As to claim 9’s processing module, the examiner interprets the means plus function limitation to the corresponding structure: demultiplexer as disclosed in [00150], Fig. 11 of the applicant’s specification.
As to claim 9’s operation module, the examiner interprets the means plus function limitation to the corresponding structure: exclusive-OR operator as disclosed in [00150], Fig. 11 of the applicant’s specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, 10-11, 14, 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onufryk et al. (US 7587439 B1, hereinafter “Onufryk”).
As per claim 1, Onufryk teaches A random number generator, comprising: a control word providing circuit, configured to generate a plurality of control words in response to a first rule, wherein integer portions of the plurality of control words are coprime (Onufryk: col 3 line 65 – col 4 line 4; circuitry that provides the OSC CONFIG signals corresponding to control word providing circuit);
a pulse generating circuit, connected to the control word providing circuit and configured to output a plurality of pulse signals in response to the plurality of control words (Onufryk: Fig. 4 elements 401-404; col 3 line 65 – col 4 line 4; wherein all the bit sources combined correspond to a pulse generating circuit), wherein each of the pulse signals comprises a first frequency signal and a second frequency signal, wherein an occurrence probability of the first frequency signal in the pulse signal is controlled by a control word corresponding to the first frequency signal, and an occurrence probability of the second frequency signal in the pulse signal is controlled by a control word corresponding to the second frequency signal (Onufryk: Fig. 5; col 5 lines 5-13; wherein the OSC CONFIG signal is able to configure the effective length of an oscillator using MUX 509);
and a random number generating circuit, connected to the pulse generating circuit and configured to generate a random number sequence by performing a logical operation on the plurality of pulse signals (Onufryk: Fig. 4 elemnt 406; col 4 lines 10-16).
As per claim 2, Onufryk further teaches The random number generator according to claim 1, wherein the pulse generating circuit comprises a plurality of pulse sub-circuits, the plurality of pulse sub-circuits being connected to the control word providing circuit and the random number generating circuit; and each of the plurality of pulse sub-circuits being configured to generate one of the plurality of pulse signals based on one of the plurality of control words (Fig. 4 elements 401-404; col 3 line 65 – col 4 line 16; wherein each bit source corresponds to a pulse sub-circuit).
As per claim 8, Onufryk further teaches The random number generator according to claim 1, further comprising: a post-processing circuit, connected to the random number generating circuit and configured to perform a probability deviation correction on the random number sequence output by the random number generating circuit (Onufryk: Fig. 4 element 407; col 4 lines 16-19).
As per claim 10, Onufryk further teaches The random number generator according to claim 1, wherein each of the plurality of control words is a numerical value and integer portions of the plurality of control words are coprime (Onufryk: col 3 line 65 – col 4 line 4; col 5 lines 5-13; It follows that OSC CONFIG is a numerical value as it is greater than one bit for a MUX with more than two inputs, and thus interpreted as an integer with integer portion. Additionally, OSC CONFIG sends signals to individual oscillators and can configure each oscillator to different stages such that they are coprime, such as 3 and 5 based on Fig. 5.).
As per claims 11, 14, 18 the claims are directed to a method that implements the same or similar features as the random number generator of claims 1, 8, 10 respectively, and are therefore rejected for at least the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 12, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Onufryk in view of Xiu (All digital FPGA-implementable time-average-frequency direct period synthesis for IoT applications, hereinafter “Xiu”).
As per claim 3, Onufryk further teaches The random number generator according to claim 2, wherein each pulse sub-circuit of the plurality of pulse sub-circuits comprises: a signal generator (Onufryk: Fig. 5 elements 501-505; col 4 lines 62-65), wherein the signal generator is configured to generate reference pulse signals with phases evenly spaced in response to an initial pulse signal (Onufryk: col 5 lines 37-39);
However, while Onufryk discloses a frequency divider circuit (Fig. 5 element 511; col 5 lines 27-29), Onufryk does not explicitly disclose a frequency synthesizer that generates pulse signals in response to a reference pulse and control words. Thus, Onufryk does not teach and a frequency synthesizer, wherein the frequency synthesizer is connected to the signal generator, the control word providing circuit, and the random number generating circuit; the frequency synthesizer is configured to generate the pulse signal in response to the reference pulse signals and the control word; wherein the control word comprises a first coefficient and a second coefficient; and the pulse signal comprises the first frequency signal generated based on the reference pulse signals and the first coefficient and the second frequency signal generated based on the reference pulse signals and the second coefficient, and proportions of the first frequency signal and the second frequency signal in the pulse signal are controlled by the second coefficient.
Xiu teaches and a frequency synthesizer, wherein the frequency synthesizer is connected to the signal generator, the control word providing circuit, and the random number generating circuit (Xiu: Fig. 3; pg. 2 left col first paragraph);
the frequency synthesizer is configured to generate the pulse signal in response to the reference pulse signals and the control word (Xiu: Fig. 3; pg. 2 left col first paragraph);
wherein the control word comprises a first coefficient and a second coefficient (Xiu: Fig. 1; pg. 1 right col first paragraph; variable I and r corresponding to coefficients);
and the pulse signal comprises the first frequency signal generated based on the reference pulse signals and the first coefficient and the second frequency signal generated based on the reference pulse signals and the second coefficient, and proportions of the first frequency signal and the second frequency signal in the pulse signal are controlled by the second coefficient (Xiu: Fig. 3; pg. 2 left col first paragraph).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the frequency divider of Onufryk with the flying-adder of Xiu. One would have been motivated to combine these references because both references disclose circuits modifying input frequencies, and the TAF-DPS architecture allows small frequency granularity (Xiu: pg. 1 right col first paragraph) as the finer granularity can better show the jitter Onufryk uses for random number generation (Onufryk: col 5 lines 37-40).
As per claim 4, Onufryk/Xiu further teaches The random number generator according to claim 3, wherein the frequency synthesizer comprises: a first processing unit, a second processing unit and an output unit; wherein the first processing unit is connected to the control word providing circuit and configured to generate a first control signal and a second control signal based on the control word; the second processing unit is connected to the first processing unit and configured to select a first pulse signal from the reference pulse signals with phases evenly spaced based on the first control signal, select a second pulse signal from the reference pulse signals based on the second control signal, and select one of the first pulse signal and the second pulse signal as an output signal; and the output unit is connected to the second processing unit and configured to generate the pulse signal based on the output signal of the second processing unit (Xiu: Fig. 3; section II A; wherein the accumulator-register section of Fig. 3 corresponds to the first processing unit, the three-multiplexer section of Fig. 3 corresponds to the second processing unit, and the flip-flop circuit corresponds to the output unit).
As per claims 12, 16 the claims are directed to a method that implements the same or similar features as the random number generator of claims 3, 4, respectively, and are therefore rejected for at least the same reasons therein.
Claims 5-7, 13, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Onufry in view of Wilber (US 20100281088 A1, hereinafter “Wilber”).
As per claim 5, Onufryk further teaches The random number generator according to claim 2.
However, while Onufryk discloses a mixing circuit (Fig. 4 element 406; col 4 lines 10-16)), Onufryk does not explicitly disclose details of the mixing circuit. Thus, Onufryk does not teach wherein the random number generating circuit comprises: a first processing sub- circuit and a second processing sub-circuit; wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND; and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing; wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit.
Wilber teaches wherein the random number generating circuit comprises: a first processing sub- circuit (Wilber: Fig. 4 elements 162; [0031]) and a second processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND (Wilber: Fig. 4 elements 162; [0031]);
and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the mixing circuit of Onufryk with the combiner-sampler of Wilber. One would have been motivated to combine these references because both references disclose combining a plurality of pulse signals, and the conbiner-sampler circuit of Wilber increases the rate of entropy of the outputs (Wilber: [0031] last sentence).
As per claim 6, Onufryk/Wilber further teaches The random number generator according to claim 5, wherein the random number generating circuit further comprises: a clock sub-circuit, wherein the clock sub-circuit is connected to the second processing sub-circuit and configured to provide the clock signal to the second processing sub-circuit (Wilber: Fig. 4 element 172; [0031]; The PLL multiplier is not shown but is disclosed as an independent oscillator that supplies clock signal 172).
As per claim 7, Onufryk/Wilber further teaches The random number generator according to claim 6, wherein the clock sub-circuit is configured to take an output of the clock sub-circuit is configured to take an output of an external clock as the clock signal (Wilber: Fig. 9 element 544; [0052]; discloses the external clock signal is multiplied by the PLL multiplier).
As per claims 13, 17 the claims are directed to a method that implements the same or similar features as the random number generator of claims 5, 7, respectively, and are therefore rejected for at least the same reasons therein.
Claims 9, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Onufryk in view of Addabbo et al. (Efficient Post-Processing Module for a Chaos-based Random Bit Generator, hereinafter “Addabbo”).
As per claim 9, Onufryk further teaches The random number generator according to claim 8.
However, while Onufryk discloses a bias corrector (Fig. 4 element 407), Onufryk does not explicitly disclose details of the bias corrector circuit. Thus, Onufryk does not teach wherein the post- processing circuit comprises: a storage module, configured to store a random sequence; a processing module, connected to the random number generating circuit and the storage module, and configured to generate a first random number based on a random number output by the random number generating circuit and one bit in the random sequence of the storage module; and an operation module, connected to the processing module and configured to output a third random number by performing a logical operation on the first random number output by the processing module and a second random number output by the operation module in the last period.
Addabbo teaches wherein the post- processing circuit comprises: a storage module, configured to store a random sequence; a processing module, connected to the random number generating circuit and the storage module, and configured to generate a first random number based on a random number output by the random number generating circuit and one bit in the random sequence of the storage module; and an operation module, connected to the processing module and configured to output a third random number by performing a logical operation on the first random number output by the processing module and a second random number output by the operation module in the last period (Addabbo: Fig. 2; section III; wherein the shift register corresponds to the storage module, the DEMUX corresponds to the processing module, and the Whitening Block (WB) corresponds to the operation module).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the bias corrector of Onufryk with the post-processing module of Addabbo. One would have been motivated to combine these references because both references disclose adjusting the output of a random bit generator, and Addabbo balances the statistical characteristic of the random sequence (Addabbo: section I).
As per claim 15, the claim is directed to a method that implements the same or similar features as the random number generator of claim 9 and is therefore rejected for at least the same reasons therein.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Onufryk in view of Xiu in further view of Wilber.
As per claim 19, Onufryk/Xiu further teaches The random number generator according to claim 3.
However, while Onufryk discloses a mixing circuit (Fig. 4 element 406; col 4 lines 10-16)), Onufryk does not explicitly disclose details of the mixing circuit. Thus, Onufryk/Xiu does not teach wherein the random number generating circuit comprises: a first processing sub-circuit and a second processing sub-circuit; wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND; and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing; wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit.
Wilber teaches wherein the random number generating circuit comprises: a first processing sub- circuit (Wilber: Fig. 4 elements 162; [0031]) and a second processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND (Wilber: Fig. 4 elements 162; [0031]);
and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]).
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the mixing circuit of Onufryk with the combiner-sampler of Wilber, for at least the same reasons as discussed above in claim 5.
As per claim 20, Onufryk/Xiu further teaches The random number generator according to claim 4.
However, while Onufryk discloses a mixing circuit (Fig. 4 element 406; col 4 lines 10-16)), Onufryk does not explicitly disclose details of the mixing circuit. Thus, Onufryk/Xiu does not teach wherein the random number generating circuit comprises: a first processing sub-circuit and a second processing sub-circuit; wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND; and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing; wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit.
Wilber teaches wherein the random number generating circuit comprises: a first processing sub- circuit (Wilber: Fig. 4 elements 162; [0031]) and a second processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the first processing sub-circuit is connected to the pulse generating circuit and configured to perform a first processing on the plurality of pulse signals, the first processing comprising at least one of exclusive-OR, inclusive-OR, or NAND (Wilber: Fig. 4 elements 162; [0031]);
and the second processing sub-circuit is connected to the first processing sub-circuit and configured to perform a second processing on a plurality of pulse signals performed with the first processing (Wilber: Fig. 4 elements 170, 175; [0031]);
wherein the second processing comprises acquiring the random number sequence by sampling, based on a clock signal, the signals output by the first processing sub-circuit (Wilber: Fig. 4 elements 170, 175; [0031]).
It would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the mixing circuit of Onufryk with the combiner-sampler of Wilber, for at least the same reasons as discussed above in claim 5.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Ihor et al. (US 20140250160 A1) discloses a random number generator wherein the two oscillator frequencies are chosen to be coprime to increase the quality of generated random numbers [0023], [0057].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182