Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group III, claims 12-18 in the reply filed on 07/09/2025 is acknowledged.
Claims 1-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12, 13, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over WATANABE (JP 2010-166634) in view of MA (US 6,366,483).
Regarding claim 12, WATANABE teaches an induction heating or melting system (see Fig. 1), comprising: an induction heating coil (6); an active rectifier (2) having thyristors (21-26); a DC link circuit (3, 7) coupled to an output of the active rectifier (as shown in Fig. 1); an inverter (4) having inverter transistors (44) and an input coupled to the DC link circuit (as shown in Fig. 1); a resonant tank circuit (5, 6) coupled to an output of the inverter and having the induction heating coil (as shown in Fig. 1); a rectifier controller (performed by 9) and an inverter controller (performed by 9).
WATANABE fails to disclose the active rectifier has rectifier transistors; the rectifier controller is configured to control the rectifier transistors at a generally constant angle between triggering of the rectifier transistors relative to an AC input phase voltage using sinusoidal pulse width modulation (SPWM) with modulation index (Ml) control to control a system output power; and an input filter coupled to an input of the active rectifier.
MA teaches a power conversion system (Fig. 1-2) comprising an active rectifier (24) having rectifier transistors (W1-W6; as shown in Fig. 2; Col. 2, lines 8-13); a rectifier controller (26) is configured to control the rectifier transistors at a generally constant angle between triggering of the rectifier transistors relative to an AC input phase voltage using sinusoidal pulse width modulation (SPWM) with modulation index (Ml) control to control a system output power (Col. 2, lines 9-41); and an input filter (Ci, Cia, Cib, Cic) coupled to an input of the active rectifier (as shown in Fig. 1-2).
Therefore, it would have it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the active rectifier and controller of WATANABE, with MA, by providing transistors instead of thyristors, and control them as claimed, to assure easier control. POSITA would have known that using transistors instead of thyristors in the active rectifier would have a reasonable expectation of success and predictable results such as easier control.
Regarding claim 13, WATANABE and MA combined teach the induction heating or melting system of claim 12, wherein the system is a current source inverter system (WATANABE; para. 0003), the DC link circuit includes a DC link reactor (WATANABE; 3) coupled to the output of the active rectifier (WATANABE; as shown in Fig. 1), and the resonant tank circuit is a parallel resonant circuit (WATANABE; as shown in Fig. 1).
Regarding claim 15, WATANABE and MA combined teach the induction heating or melting system of claim 12, wherein the inverter controller is configured to control the inverter transistors to provide an inverter output voltage to the resonant tank circuit at an inverter output frequency higher than a resonant frequency of the resonant tank circuit (WATANABE; para. 0036).
Regarding claim 18, WATANABE and MA combined teach the induction heating or melting system of claim 12, wherein the rectifier transistors are IGBTs (WATANABE; para. 0017).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over WATANABE and MA as set forth above in claim 12, and further in view of MIYAUCHI (US 2010/0230401).
Regarding claim 14, WATANABE and MA combined teach the induction heating or melting system of claim 12, wherein the system is a voltage source inverter system (WATANABE, as shown in Fig. 1, the inverter supplies voltage to the resonant circuit).
WATANABE and MA combined fail to disclose wherein the DC link circuit includes a DC link capacitor coupled to the output of the active rectifier, and the resonant tank circuit is a series resonant circuit.
MIYAUCHI teaches an induction heating apparatus (Fig. 1) comprising a DC link circuit (78, 79) includes a DC link capacitor (78) coupled to the output of a rectifier (52), and a resonant tank circuit (59, 60) is a series resonant circuit (as shown in Fig. 1).
Therefore, it would have it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the DC link circuit of WATANABE and MA, with MIYAUCHI, by providing a DC link capacitor, to reduce voltage fluctuation, and a series resonant circuit if the application requires maximum current flow. POSITA would have known that providing a DC link capacitor and a series resonant circuit would have a reasonable expectation of success and predictable results, such as voltage fluctuation reduction and maximum current flow.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over WATANABE and MA as set forth above in claim 12, and further in view of HIRAISHI (JP 2007-159175).
Regarding claim 16, WATANABE and MA combined teach the induction heating or melting system of claim 12, wherein the inverter controller is configured to control the inverter transistors to provide an inverter output voltage to the resonant tank circuit (WATANABE, para. 0026-0028).
WATANABE and MA combined fail to disclose wherein the inverter controller is configured to hold an inverter phase angle between the inverter output voltage and an inverter output current at a fixed value.
HIRAISHI teaches a power conversion system (Fig. 1) comprising an inverter controller configured to hold an inverter phase angle between the inverter output voltage and an inverter output current at a fixed value (para. 0016-0017; 0033-0042).
Therefore, it would have it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inverter controller of WATANABE and MA, with HIRAISHI, by holding inverter phase angle between the inverter output voltage and an inverter output current at a fixed value, so the oscillation frequency approaches the resonant frequency (para. 0033) and therefore, achieve maximum efficiency and effectiveness. POSITA would have known that holding inverter phase angle between the inverter output voltage and an inverter output current at a fixed value would have a reasonable expectation of success and predictable results such as, maximum efficiency and effectiveness.
Regarding claim 17, WATANABE, MA and HIRAISHI combined teach the induction heating or melting system of claim 16, wherein the inverter controller is configured to control the inverter phase angle to approach zero (HIRAISHI; para. 0033-0042).
WATANABE, MA and HIRAISHI combined fail to disclose wherein the inverter controller is configured to control the inverter phase angle at approximately 15 degrees.
Therefore, it would have it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the claimed inverter phase angle, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: CN 109068428, US 2018/0212537 and KR 101308411.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBA T ROSARIO-APONTE whose telephone number is (571)272-9325. The examiner can normally be reached M to F; 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Crabb can be reached at 571-270-5095. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALBA T ROSARIO-APONTE/Examiner, Art Unit 3761 08/07/2025
/STEVEN W CRABB/Supervisory Patent Examiner, Art Unit 3761