DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed January 2nd, 2025. Claims 1-5, 7-10, 12-17, 19-22, and 25 are pending, of which claims 1-5, 7-10, 12-17 19-22, and 25 are currently rejected. Claims 6, 11, 18, and 23-24 have been cancelled by Applicant.
Response to Arguments
The amendment filed January 2nd, 2025 has been entered. Claims 1-5, 7-10, 12-17, 19-22, and 25 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every specification and claim objection as well as 112(b) rejection as previously set forth in the Non-Final Office Action mailed October 2nd, 2025.
Specification Objections
Applicant has amended the specification to address the objections as previously set forth in the Office Action mailed October 2nd, 2025. Therefore, the previous objection to the Specification has been withdrawn.
Claim Objections
Applicant has amended the claims to address the objections as previously set forth in the Office Action mailed October 2nd, 2025. Therefore, the previous objections to the Claims have been withdrawn.
Claim Rejections – 35 USC § 112
Applicant has amended claims and resolved the antecedent basis issues. Therefore, the previous rejections under 35 U.S.C. 112(b) as set forth in the Office Action mailed September 25th, have been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Applicant alleges that Yang (11126403) (hereinafter “Yang”) does not teach claim 1, more specifically the limitation reciting “generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations” for the following reasons:
Point 1: The mechanism of generating the random number in Yang is totally different from that in the pending application (Pg. 14 Applicant Remarks).
Point 2: Yang does not disclose or suggest generating a random bit string based on the number of pulses applied to the diffusive memristor (Pg. 15 Applicant Remarks).
Point 3: The pulse applied to the diffusive memristor to change the resistance is a single pulse (Pg. 16 Applicant Remarks).
Examiner respectfully disagrees and sustains previous rejections under 35 USC § 102 and 35 USC § 103 for the following reasons:
With regards to Point 1, Examiner points out that claim 1 does not claim the mechanism for generating the random number, rather it is claiming the method by which the random number is generated. In response to applicant’s argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the mechanism used for changing the conductance value by random amounts) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding Point 2, Applicant points to Figs. 2a-2b to prove that that the random number in Yang is not generated based on the number of pulses applied to the diffusive memristor as claimed. However, Examiner points out that the n writing operation pulse numbers are never specified anywhere in the claims to be analogous to or correspond to the at least one writing operation pulse of line 3 in claim 1. While the claim does recite generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations, the generation of the random number is carried out in Yang based on n writing operation pulse numbers (from the clock Fig. 2a element 230), and the random number generated would be corresponding to the n writing operations i.e., the writing operation pulse as provided to the AND gate (Fig. 2A 220) and the counter (Fig. 2A element 240) from the memristor (Fig. 2A 260) for final random number generation. Hence, the random number generated by Yang is in fact still being output respectively corresponding to n writing operation pulse numbers as generated by the clock (Fig. 2a element 230) and as described in Col. 7 Lines 31-50 and Col. 3 Lines 4-9. Therefore, Yang does in fact teach generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations.
Regarding Point 3, Applicant points out that the pulse applied to the diffusive memristor to change the resistance is a single pulse, differing from the claim. However, on line 3 of claim 1 it is recited “each of the n writing operations comprises applying at least one writing operation pulse”. The singe pulse V1 as indicated by Applicant does therefore meet the requirement of at least one writing operation pulse. Therefore, Yang does in fact teach claim 1.
See Claim Rejections - 35 USC § 102 and 35 USC § 103.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, 13 and 21 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yang et al. (11126403) (hereinafter “Yang”).
Yang teaches:
A method for generating a random number, comprising:
performing n writing operations on at least one analog resistive random access memory (Abstract TRNG based on memristor i.e., analog RRAM based on application of pulses i.e., writing operation), wherein each of the n writing operations comprises applying at least one writing operation pulse to change a conductance value of an operated analog resistive random access memory (Abstract TRNG based on memristor i.e., analog resistive memory driven by a pulse generator, pulses applied to memristor and based on these random pulses Col. 7 Lines 31-50; Col. 9 Lines 19-31 and Col. 10 Lines 28-30 pulses change conductance value); and
generating the random number based on n writing operation pulse numbers respectively corresponding to the n writing operations, wherein n is a positive integer (Col. 3 Lines 4-9 generating a random bit string output signal i.e., random number).
Regarding claim 13, Yang teaches:
A random number generator, comprising:
at least one analog resistive random access memory (Yang: Abstract TRNG based on memristor i.e., analog RRAM based on application of pulses i.e., writing operations);
a writing circuit, coupled to the at least one analog resistive random access memory and configured to perform n writing operations on the at least one analog resistive random access memory, wherein each of the n writing operations comprises applying at least one writing operation pulse to change a conductance value of an operated analog resistive random access memory (Yang: Abstract TRNG based on memristor i.e., analog resistive memory driven by pulse generator i.e., writing circuit and pulses are applied to memristor, the random number being based on these random pulses Col. 7 Lines 31-50; Col. 9 Lines 19-31 and Col. 10 Lines 28-30 pulses change conductance values);
a counter, coupled to the writing circuit and configured to count writing operation pulses corresponding to the n writing operations to obtain n writing operation pulse numbers corresponding to the n writing operations, respectively (Yang: Col. 2 Line 67 and Col. 3 Lines 1-3 counter coupled to writing circuit in order to receive a number of pulses and generate a random bit string output signal i.e., random number); and
an output circuit, coupled to the counter and configured to generate a random number based on the n writing operation pulse numbers, wherein n is a positive integer (Yang: Abstract discusses outputting a random bit string output signal i.e., random number based on pulses i.e., writing operations).
Regarding claim 9, Yang in view of Han further teaches generating a random number based on n writing operation pulse numbers, and obtaining intermediate numbers corresponding to the pulses i.e., writing operation pulse numbers (Yang: Col. 8 Lines 5-43 pulse numbers used to determine random number output).
Claim 21 recites the random number generator that practices the method of claim 9 and is therefore rejected for the same reasons therein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, further in view of Han (US 2017/0301399 A1) (hereinafter “Han”).
Regarding claim 2, while Yang teaches having an m-th writing operation of the n writing operations and writing pulses (Yang: Col. 7 Lines 47-67; Col. 8 Lines 18-43) as well as having these writing operations applied to an analog resistive access memory (Yang: Col. 7 Lines 31-50), Yang does not explicitly teach a set operation to have the conductance value of the analog resistive random access memory being gradually increased form a set initial conductance value to a set state conductance value.
However, Han teaches:
wherein an m-th writing operation of the n writing operations comprises a set operation (Han: ¶ 0040 discusses set operation comprising of writing set pulses),
sequentially applying the at least one set pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value (Han: ¶ 0040 teaches completing the set operation until Vsinitial i.e., initial conductance value reaches the Vset i.e., set state conductance value).
It would be obvious to combine the set operation as taught by Han with the writing pulses and analog resistive random access memory as taught by Yang as both teachings are directed towards pulse generation for resistive random access memory. The improvement of Han lies in improving service life and reducing power consumption of the writing operations (Han: ¶ 0015).
Therefore, Yang in view of Han teaches:
The method according to claim 1, wherein an m-th writing operation of the n writing operations comprises a set operation, and at least one writing operation pulse corresponding to the m-th writing operation comprises at least one set pulse, m is a positive integer, and 1 ≤ m ≤ n and the set operation comprises:
sequentially applying the at least one set pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value.
Regarding claim 3, while Yang teaches having an m-th writing operation of the n writing operations and writing pulses (Yang: Col. 7 Lines 47-67; Col. 8 Lines 18-43) as well as having these writing operations applied to an analog resistive access memory (Yang: Col. 7 Lines 31-50), Yang does not explicitly teach a set operation to have the conductance value of the analog resistive random access memory being gradually increased form a set initial conductance value to a set state conductance value or the quantity of the set pulse reaching the set pulse number threshold.
However, Han teaches:
wherein an m-th writing operation of the n writing operations comprises a set operation (Han: ¶ 0040 discusses set operation comprising of writing set pulses),
obtaining a set pulse number threshold (Han: ¶ 0088 P as set pulse number threshold and set signal i.e., counter of set pulses must be less than P); and
sequentially applying the at least one set pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value (Han: ¶ 0040 teaches completing the set operation until Vsinitial i.e., initial conductance value reaches the Vset i.e., set state conductance value) or a quantity of the at least one set pulse reaches the set pulse number threshold (Han: ¶ 0088 once sent signal gets to P’s value, the set operation stops).
The motivation to combine with respect to claim 2 applies equally to claim 3.
Therefore, Yang in view of Han teaches:
The method according to claim 1, wherein an m-th writing operation of the n writing operations comprises a set operation, and at least one writing operation pulse corresponding to the m-th writing operation comprises at least one set pulse, m is a positive integer, and 1 ≤ m ≤ n and the set operation comprises:
obtaining a set pulse number threshold; and
sequentially applying the at least one set pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value or a quantity of the at least one set pulse reaches the set pulse number threshold.
Claims 4-5, 7-8, 10, 14-17, 19-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Han, further in view of S. Balatti et al. (“Physical Unbiased Generation of Random Numbers With Coupled Resistive Switching Devices”, 2016) (hereinafter “Balatti”).
Regarding claim 4, while Yang in view of Han teaches the method according to claim 2 as well as m-th writing operation comprising a reset operation with writing operations comprising at least one reset pulse (Han: ¶ 0038 reset pulse operation with reset state conductance value Vrinitial, and completion of reset operation until the conductance values reaches the reset target conductance value Vreset), Yang in view of Han does not explicitly teach sequentially applying the reset pulse to the RRAM until the conductance value of the RRAM is gradually decreased from the set state conductance value to a reset target conductance value.
However, Balatti teaches:
sequentially applying the at least one reset pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Balatti: Pg. 2030 Fig. 1 shows the decreasing from V set i.e., set stand conductance value to V reset or reset state conductance and vice versa).
It would be obvious to combine the gradual decreasing from the set state conductance value to a reset target conductance value as taught by Balatti with the method and reset operation as taught by Yang in view of Han as all teachings are directed towards pulse generation for RRAM devices. The improvement of Balatti lies in accelerating the decrease or increase of conductance values, thereby increasing operation speed (Balatti: Pg. 2031 Col. 2 Section B Lines 15-19).
Regarding claim 5, while Yang in view of Han teaches the method according to claim 2 as well as m-th writing operation comprising a reset operation with writing operations comprising at least one reset pulse (Han: ¶ 0038 reset pulse operation with reset state conductance value Vrinitial, and completion of reset operation until the conductance values reaches the reset target conductance value Vreset), and a reset pulse number threshold as well as performing a reset operation until the threshold is reached (Han: ¶ 0088 P as reset pulse number threshold and rent signal i.e., counter of reset pulses must be less than P, once rent signal gets to P’s value, the reset operation stops), Yang in view of Han does not explicitly teach sequentially applying the reset pulse to the RRAM until the conductance value of the RRAM is gradually decreased from the set state conductance value to a reset target conductance value.
However, Balatti teaches:
sequentially applying the at least one reset pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Balatti: Pg. 2030 Fig. 1 shows the decreasing from V set i.e., set stand conductance value to V reset or reset state conductance and vice versa).
The motivation to combine with respect to claim 4 applies equally to claim 5.
Regarding claim 7, while Yang in view of Han teaches the method according to claim 1 as well as m-th writing operation comprising a reset operation with writing operations comprising at least one reset pulse (Han: ¶ 0038 reset pulse operation with reset state conductance value Vrinitial, and completion of reset operation until the conductance values reaches the reset target conductance value Vreset), Yang in view of Han does not explicitly teach sequentially applying the reset pulse to the RRAM until the conductance value of the RRAM is gradually decreased from the set state conductance value to a reset target conductance value.
However, Balatti teaches:
sequentially applying the at least one reset pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Balatti: Pg. 2030 Fig. 1 shows the decreasing from V set i.e., set stand conductance value to V reset or reset state conductance and vice versa).
The motivation to combine with respect to claim 4 applies equally to claim 7.
Regarding claim 8, while Yang in view of Han teaches the method according to claim 1 as well as m-th writing operation comprising a reset operation with writing operations comprising at least one reset pulse (Han: ¶ 0038 reset pulse operation with reset state conductance value Vrinitial, and completion of reset operation until the conductance values reaches the reset target conductance value Vreset), and a reset pulse number threshold as well as performing a reset operation until the threshold is reached (Han: ¶ 0088 P as reset pulse number threshold and rent signal i.e., counter of reset pulses must be less than P, once rent signal gets to P’s value, the reset operation stops), Yang in view of Han does not explicitly teach sequentially applying the reset pulse to the RRAM until the conductance value of the RRAM is gradually decreased from the set state conductance value to a reset target conductance value.
However, Balatti teaches:
sequentially applying the at least one reset pulse to the operated analog resistive random access memory until the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Balatti: Pg. 2030 Fig. 1 shows the decreasing from V set i.e., set stand conductance value to V reset or reset state conductance and vice versa).
The motivation to combine with respect to claim 4 applies equally to claim 8.
Regarding claim 10, while Yang teaches taking the pulse train from the number of pulses and converting it into random number (Yang: Col. 8 Lines 18-27; Col. 2 Lines 66-67 and Col. 3 Lines 1-3), Yang does not explicitly teach respective computation operations for each of a reset or set operation.
However, Han teaches a respective computation i.e., first computation for set pulses (Han: ¶ 0040) and a respective computation i.e., second computation for reset pulses (Han: ¶ 0038).
The motivation to combine with respect to claim 2 applies equally to claim 10.
Yang in view of Han does not explicitly teach a third computation occurring for both set and reset pulses and a fourth computation being carried out on the third computation result.
However, Balatti teaches reset and set pulses occurring and having a third computation i.e., reading pulses through a voltage divider occur, after which a fourth computation i.e., bimodal distribution via a comparator occurs on the pulses (Balatti: Pg. 2031 Fig. 3 Caption first reading through voltage divider and afterwards bimodal distribution through comparator; Col. Pg. 2031 Col. 1 Lines 4-11 set and reset pulses occur upon which a bimodal distribution is executed through comparator as discussed Pg. 2031 Col. 2 Lines 6-8).
It would be obvious to combine the third and fourth computations as taught by Balatti with the respective first and second computations and pulse train as taught by Yang as all teachings are directed towards randomization. The improvement of Balatti lies in increasing variability and thus entropy from cycle to cycle (Balatti: Pg. 2031 Col. 2 Lines 18-20).
Regarding claim 14, while Yang teaches the random number generator of claim 13, the writing circuit and m writing operations for generation of pulse numbers and therethrough random numbers (Yang: Col. 7 Lines 47-67; Col. 8 Lines 18-43), a counter for purposes of counting the number of pulses and outputting a random number through an output circuit using the count of pulses generated (Yang: Col. 12 Lines 34-36; Col. 2 Lines 67 and Col. 3 Lines 1-3), Yang does not explicitly teach the writing circuit having a pulse generation circuit, a comparator, and controller, a set operation, or a set state conductance threshold.
However, Han teaches:
wherein the writing circuit comprises a pulse generation circuit, a comparator, and a controller (Han: Fig. 2 as writing circuit, element 213 as controller, elements 215 and 217 as pulse generation circuits, and element 212 as comparators),
wherein an m-th writing operation of then writing operations comprises a set operation (Han: ¶ 0040 pulses generated by set operation from writing operations),
the controller is configured to control the pulse generation circuit to generate and apply the at least one set pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value (Han: ¶ 0040 teachings completing the set operation until Vsinitial i.e., initial conductance value reaches the Vset i.e., set state conductance value; ¶ 0090 enables set operation i.e., set operation pulses) , and configured to control the counter to count the at least one set pulse to obtain an m-th set pulse number, and the m0th writing operation pulse number comprises the m-th set pulse number (Han: ¶ 0017 set counter produces scounter signal and counts the number of set pulses; Fig. 2 element 214).
The motivation to combine with respect to claim 2 applies equally to claim 14.
While Han does teach a comparator (Han: Fig. 2 Element 212), Han does not explicitly teach:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result; and
the controller is further configured to control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value.
However, Balatti teaches:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output); and
the controller is further configured to control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output).
It would be obvious to combine the comparator as taught by Balatti with the method and writing circuit as taught by Yang in view of Han as all teachings are directed towards pulse generation for RRAM devices. The improvement of Balatti lies in achieving a true and unbiased RNG (Balatti. Pg. 2031 Col. 2 Lines 1-3).
Therefore, Yang in view of Han in view of Balatti teaches:
The random number generator according to claim 13, wherein the writing circuit comprises a pulse generation circuit, a comparator, and a controller,
wherein an m-th writing operation of then writing operations comprises a set operation, at least one writing operation pulse corresponding to the m-th writing operation comprises at least one set pulse, mis a positive integer, and 1≤m≤n, then writing operation pulse numbers comprise an m-th writing operation pulse number corresponding to the m-th writing operation,
the controller is configured to control the pulse generation circuit to generate and apply the at least one set pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value, and configured to control the counter to count the at least one set pulse to obtain an m-th set pulse number, and the m-th writing operation pulse number comprises the m-th set pulse number;
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result; and
the controller is further configured to control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value.
Regarding claim 15, while Yang teaches the random number generator of claim 13, the writing circuit and m writing operations for generation of pulse numbers and therethrough random numbers (Yang: Col. 7 Lines 47-67; Col. 8 Lines 18-43), a counter for purposes of counting the number of pulses and outputting a random number through an output circuit using the count of pulses generated (Yang: Col. 12 Lines 34-36; Col. 2 Lines 67 and Col. 3 Lines 1-3), Yang does not explicitly teach the writing circuit having a pulse generation circuit, a comparator, and controller, a set operation, or a set state conductance threshold.
However, Han teaches:
wherein the writing circuit comprises a pulse generation circuit, a comparator, and a controller (Han: Fig. 2 as writing circuit, element 213 as controller, elements 215 and 217 as pulse generation circuits, and element 212 as comparators),
wherein an m-th writing operation of then writing operations comprises a set operation (Han: ¶ 0040 pulses generated by set operation from writing operations),
the controller is configured to control the pulse generation circuit to generate and apply the at least one set pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value (Han: ¶ 0040 teachings completing the set operation until Vsinitial i.e., initial conductance value reaches the Vset i.e., set state conductance value; ¶ 0090 enables set operation i.e., set operation pulses), and configured to control the counter to count the at least one set pulse to obtain an m-th set pulse number, and the m0th writing operation pulse number comprises the m-th set pulse number (Han: ¶ 0017 set counter produces scounter signal and counts the number of set pulses; Fig. 2 element 214)
the controller is further configured to obtain a set pulse number threshold (Han: ¶ 0088 P as set pulse number threshold and sent signal i.e., counter of set pulses must be less than P, once sent signal gets to P’s value, the set operation stops) in a case where the m-th set pulse number reaches the set pulse number threshold (Han: ¶ 0040 set operation stops once the set pulse number threshold is reached, i.e., sent = P).
The motivation to combine with respect to claim 2 applies equally to claim 15.
While Han does teach a comparator (Han: Fig. 2 Element 212), Han does not explicitly teach:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result; and
the controller is further configured to control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value.
However, Balatti teaches:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output); and
the controller is further configured to control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output).
The motivation to combine with respect to claim 14 applies equally to claim 15.
Therefore, Yang in view of Han in view of Balatti teaches:
The random number generator according to claim 13, wherein the writing circuit comprises a pulse generation circuit, a comparator, and a controller,
wherein an m-th writing operation of then writing operations comprises a set operation, at least one writing operation pulse corresponding to the m-th writing operation comprises at least one set pulse, mis a positive integer, and 1≤m≤n, then writing operation pulse numbers comprise an m-th writing operation pulse number corresponding to the m-th writing operation,
the controller is configured to control the pulse generation circuit to generate and apply the at least one set pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually increased from a set initial conductance value to a set state conductance value, and configured to control the counter to count the at least one set pulse to obtain an m-th set pulse number, and the m-th writing operation pulse number comprises the m-th set pulse number;
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a set state conductance value threshold to obtain a set comparison result; and
the controller is further configured to obtain a set pulse number threshold, and control the counter to output the m-th set pulse number obtained by counting to the output circuit in a case where the set comparison result indicates that the conductance value of the operated analog resistive random access memory is increased to the set state conductance value or the m-th set pulse number reaches the set pulse number threshold.
Regarding claim 16, while Yang teaches the counter for outputting a random number (Yang: Col. 12 Lines 34-36; Col. 2 Lines 67 and Col. 3 Lines 1-3), Yang does not explicitly teach the random number generator having a reset operation, a counter for counting reset pulses, or a comparator for comparing the conductance to a threshold.
However, Han teaches:
The random number generator according to claim 14, wherein the m-th writing operation further comprises a reset operation, and the at least one writing operation pulse further comprises at least one reset pulse (Han: ¶ 0038 reset operation that comprises reset pulses),
the controller is configured to control the pulse generation circuit to generate and apply the at least one reset pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Han: ¶ 0038 teachings completing the set operation until Vrinitial i.e., initial conductance value reaches the Vreset i.e., set state conductance value; ¶ 0090 controller enables reset operation i.e., set operation pulses), and configured to control the counter to count the at least one reset pulse to obtain an m-th reset pulse number, and the m-th writing operation pulse number further comprises them-th reset pulse number (Han: ¶ 0017 reset counter produces rcounter signal and counts the number of reset pulses; Fig. 2 element 216);
The motivation to combine with respect to claim 2 applies equally to claim 16.
However, Han does not explicitly teach:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result;
the controller is further configured in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value.
However, Balatti teaches:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output);
the controller is further configured in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output).
The motivation to combine with respect to claim 14 applies equally to claim 16.
Therefore, Yang in view of Han in view of Balatti teaches:
The random number generator according to claim 14, wherein the m-th writing operation further comprises a reset operation, and the at least one writing operation pulse further comprises at least one reset pulse,
the controller is configured to control the pulse generation circuit to generate and apply the at least one reset pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value, and configured to control the counter to count the at least one reset pulse to obtain an m-th reset pulse number, and the m-th writing operation pulse number further comprises them-th reset pulse number;
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result;
the controller is further configured to control the counter to output the m-th reset pulse number obtained by counting to the output circuit in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value.
Regarding claim 17, while Yang teaches the counter for outputting a random number (Yang: Col. 12 Lines 34-36; Col. 2 Lines 67 and Col. 3 Lines 1-3), Yang does not explicitly teach the random number generator having a reset operation, a counter for counting reset pulses, or a comparator for comparing the conductance to a threshold.
However, Han teaches:
The random number generator according to claim 14, wherein the m-th writing operation further comprises a reset operation, and the at least one writing operation pulse further comprises at least one reset pulse (Han: ¶ 0038 reset operation that comprises reset pulses),
the controller is configured to control the pulse generation circuit to generate and apply the at least one reset pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value (Han: ¶ 0038 teachings completing the reset operation until Vrinitial i.e., initial conductance value reaches the Vreset i.e., set state conductance value; ¶ 0090 controller enables reset operation i.e., set operation pulses), and configured to control the counter to count the at least one reset pulse to obtain an m-th reset pulse number, and the m-th writing operation pulse number further comprises them-th reset pulse number (Han: ¶ 0017 reset counter produces rcounter signal and counts the number of reset pulses; Fig. 2 element 216);
the controller is further configured to obtain a reset pulse number threshold (Han: ¶ 0088 P as reset pulse number threshold and rent signal i.e., counter of reset pulses must be less than P), to output the m-th reset pulse number obtained in a case where the m-th reset pulse number reaches the reset pulse number threshold (Han: ¶ 0088 reset operation is completed once P is reached by rent signal).
The motivation to combine with respect to claim 2 applies equally to claim 17.
However, Han does not explicitly teach:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result;
the controller is further configured in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value.
However, Balatti teaches:
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output);
the controller is further configured in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value (Balatti: Pg. 2031 Col. 2 Lines 10-16 comparator used to digitize output and to facilitate random bit output).
The motivation to combine with respect to claim 14 applies equally to claim 17.
Therefore, Yang in view of Han in view of Balatti teaches:
The random number generator according to claim 14, wherein the m-th writing operation further comprises a reset operation, and the at least one writing operation pulse further comprises at least one reset pulse,
the controller is configured to control the pulse generation circuit to generate and apply the at least one reset pulse to the operated analog resistive random access memory, so that the conductance value of the operated analog resistive random access memory is gradually decreased from the set state conductance value to a reset target conductance value, and configured to control the counter to count the at least one reset pulse to obtain an m-th reset pulse number, and the m-th writing operation pulse number further comprises the m-th reset pulse number;
the comparator is configured to compare the conductance value of the operated analog resistive random access memory with a reset target conductance value threshold to obtain a reset comparison result;
the controller is further configured to obtain a reset pulse number threshold, and control the counter to output the m-th reset pulse number obtained by counting to the output circuit in a case where the reset comparison result indicates that the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value or the m-th reset pulse number reaches the reset pulse number threshold.
Claim 19 recites the random number generator of claim 16 and is therefore rejected for the same reasons therein. Additionally, claim 19 recites the controller further configured to control the counter to output the m-th reset pulse number obtained by counting the output circuit in a case where the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value, which is taught by Yang in view of Han in view of Balatti (Balatti: Pg. 2030 Fig. 1 shows the decreasing the V set i.e., set stand conductance to V reset or reset state conductance and vice versa). The motivation to combine with respect to claim 4 applies equally to claim 19.
Regarding claim 20, recites the random number generator of claim 17 and is therefore rejected for the same reasons therein. Additionally, claim 20 recites the controller further configured to control the counter to output the m-th reset pulse number obtained by counting the output circuit in a case where the conductance value of the operated analog resistive random access memory is decreased to the reset target conductance value, which is taught by Yang in view of Han in view of Balatti (Balatti: Pg. 2030 Fig. 1 shows the decreasing the V set i.e., set stand conductance to V reset or reset state conductance and vice versa). The motivation to combine with respect to claim 4 applies equally to claim 20.
Claim 22 teaches the random number generator that practices the method of claim 10 and is therefore rejected for the same reasons therein.
Claim 12, is rejected under 35 U.S.C. 103 as being unpatentable over Yang, in view of Han in view of Balatti, further in view of Ueda et al. (US 2015/0100614 A1) (hereinafter “Ueda”).
While Yang in view of Han teaches the method of claim 10, Yang in view of Han does not teach a modulo 2L computation for generating the random number, taking the n intermediate numbers as n digits of an n-bit 2Lary number.
However, Ueda teaches a N-ary number (including a 2Lary number) converting circuit for converting an intermediate number of each number of bits into an N-ary number by reading the intermediate number having the predetermined number of bits of the intermediate number converted into the N-ary number (Ueda: ¶ 0048).
It would be obvious to combine the N-nary conversion i.e., computation as taught by Ueda with the method as taught by Yang in view of Han as all teachings are directed towards digital design for randomization. The improvement of Ueda lies in having a more randomized output by having the output more randomly obtained (Ueda: ¶ 0049).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, in view of Han, further in view of Sakamoto (5966313) (hereinafter “Sakamoto”).
While Yang in view of Han teaches the random number generator of claim 13 and the counter of the output circuit being a 1-bit counter (Yang: Col. 3 Lines 8-9 counter can be single bit counter; Fig. 2A element 240), Yang does not teach the output circuit containing a D-trigger to output random numbers.
However, Sakamoto teaches a D flip-flop i.e. D-trigger used to output random numbers from pulses (Col. 4 Lines 63-66).
It would be obvious to combine the D flip-flop for outputting random numbers as taught by Sakamoto with the random number generator as taught by Yang in view of Han as all teachings are directed towards randomization of output. The improvement of Sakamoto lies in providing greater flexibility of random number output (Sakamoto: Col. 7 Lines 18-20).
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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