Prosecution Insights
Last updated: April 19, 2026
Application No. 17/781,011

DISPLAY PANEL AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Nov 16, 2023
Examiner
ALAM, MOHAMMED R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
496 granted / 557 resolved
+21.0% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
576
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.3%
+4.3% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 557 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1-3, 5-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (US publication 2016/0365367 A1), hereinafter referred to as Kimura367, in view of Hayama et al. (US publication 2015/0337245 A1), hereinafter referred to as Hayama245. Regarding claim 1, Kimura367 teaches a display panel (fig. 42 and related text), comprising: a substrate (102, [0202]); and a first metal layer (343, [0257]) disposed on the substrate (fig. 42); wherein the first metal layer comprises a barrier layer (a copper-magnesium-aluminum alloy layer of a two-layer gate structure (other two-layer or a three layer structure as described in [0324] can also be applied), [0324]) and a main body layer (a copper layer of a two-layer gate structure (other two-layer or a three layer structure as described in [0324] can also be applied), [0324]) arranged in a stack, the main body layer is disposed on a side of the barrier layer away from the substrate ([0324], fig. 42). Kimura367 does not explicitly teach and wherein a corrosion potential difference between the main body layer and the barrier layer is greater than or equal to −0.1V and less than or equal to 0.3V. Hayama245 teaches and wherein a corrosion potential difference between the main body layer (16, [0079], fig. 1a-fig. 1b) and the barrier layer (14, [0079]) is greater than or equal to −0.1V and less than or equal to 0.3V ([0026, 0030, and 0104]). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that and wherein a corrosion potential difference between the main body layer and the barrier layer is greater than or equal to −0.1V and less than or equal to 0.3V for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 2, Kimura367 teaches further comprising a gate insulating layer (108, [0254]) and a second metal layer (source or drain electrode of a transistor 150b, [0324 and 0361]) disposed on the first metal layer, wherein the gate insulating layer is disposed between the first metal layer and the second metal layer, the first metal layer comprises a gate, and the second metal layer comprises a source and a drain; and wherein at least one of the first metal layer or the second metal layer is a composite metal layer ([0324 and 0361], fig. 42). Regarding claim 3, Kimura367 teaches wherein a material of the main body layer comprises copper ([0324]), and a material of the barrier layer comprises a magnesium-aluminum alloy ([0361]). Regarding claim 5, Hayama245 teaches wherein a thickness of the barrier layer is smaller than a thickness of the body layer (fig. 1a-fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein a thickness of the barrier layer is smaller than a thickness of the body layer for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 6, Kimura367 and Hayama245 disclose all the limitations of claim 5 as discussed above on which this claim depends. Kimura367 and Hayama245 do not explicitly teach wherein the thickness of the barrier layer is greater than or equal to 300 angstroms and less than or equal to 500 angstroms. However, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation. Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kimura367 and Hayama245 so that wherein the thickness of the barrier layer is greater than or equal to 300 angstroms and less than or equal to 500 angstroms for the purpose of optimizing device performance and overall size of the device. Regarding claim 7, Kimura367 and Hayama245 disclose all the limitations of claim 6 as discussed above on which this claim depends. Kimura367 and Hayama245 do not explicitly teach wherein the thickness of the main body layer is greater than or equal to 2000 angstroms and less than or equal to 8000 angstroms. However, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation. Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kimura367 and Hayama245 so that wherein the thickness of the main body layer is greater than or equal to 2000 angstroms and less than or equal to 8000 angstroms for the purpose of optimizing device performance and overall size of the device. Regarding claim 8, Hayama245 teaches wherein an edge of the barrier layer is flush with an edge of the main body layer; or an edge of the barrier layer extends beyond an edge of the main body layer (fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein an edge of the barrier layer is flush with an edge of the main body layer; or an edge of the barrier layer extends beyond an edge of the main body layer for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 9, Hayama245 teaches wherein the main body layer and the barrier layer comprise an inclined surface, and an orthographic projection of the main body layer on the substrate falls within an orthographic projection of the barrier layer on the substrate (fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein the main body layer and the barrier layer comprise an inclined surface, and an orthographic projection of the main body layer on the substrate falls within an orthographic projection of the barrier layer on the substrate for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 10, Kimura367 teaches an electronic device (fig. 42 and related text), comprising a device body (372, [0252], fig. 42) and a display panel (device top on and below 372) mounted on the device body (fig. 42), wherein the display panel comprises a substrate (102, [0202]); and a first metal layer (343, [0257]) disposed on the substrate (fig. 42); wherein the first metal layer comprises a barrier layer (a copper-magnesium-aluminum alloy layer of a two-layer gate structure (other two-layer or a three layer structure as described in [0324] can also be applied), [0324]) and a main body layer (a copper layer of a two-layer gate structure (other two-layer or a three layer structure as described in [0324] can also be applied), [0324]) arranged in a stack, the main body layer is disposed on a side of the barrier layer away from the substrate ([0324], fig. 42). Kimura367 does not explicitly teach and wherein a corrosion potential difference between the main body layer and the barrier layer is greater than or equal to −0.1V and less than or equal to 0.3V. Hayama245 teaches and wherein a corrosion potential difference between the main body layer (16, [0079], fig. 1a-fig. 1b) and the barrier layer (14, [0079]) is greater than or equal to −0.1V and less than or equal to 0.3V ([0026, 0030, and 0104]). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that and wherein a corrosion potential difference between the main body layer and the barrier layer is greater than or equal to −0.1V and less than or equal to 0.3V for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 11, Kimura367 teaches wherein the display panel further comprising a gate insulating layer (108, [0254]) and a second metal layer (source or drain electrode of a transistor 150b, [0324 and 0361]) disposed on the first metal layer, wherein the gate insulating layer is disposed between the first metal layer and the second metal layer, the first metal layer comprises a gate, and the second metal layer comprises a source and a drain; and wherein at least one of the first metal layer or the second metal layer is a composite metal layer ([0324 and 0361], fig. 42). Regarding claim 12, Kimura367 teaches wherein the first metal layer and the second metal layer are composite metal layers ([0324 and 0361], fig. 42). Regarding claim 13, Kimura367 teaches wherein a material of the main body layer comprises copper ([0324]), and a material of the barrier layer comprises a magnesium-aluminum alloy ([0361]). Regarding claim 15, Hayama245 teaches wherein a thickness of the barrier layer is smaller than a thickness of the body layer (fig. 1a-fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein a thickness of the barrier layer is smaller than a thickness of the body layer for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 16, Kimura367 and Hayama245 disclose all the limitations of claim 15 as discussed above on which this claim depends. Kimura367 and Hayama245 do not explicitly teach wherein the thickness of the barrier layer is greater than or equal to 300 angstroms and less than or equal to 500 angstroms. However, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation. Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kimura367 and Hayama245 so that wherein the thickness of the barrier layer is greater than or equal to 300 angstroms and less than or equal to 500 angstroms for the purpose of optimizing device performance and overall size of the device. Regarding claim 17, Kimura367 and Hayama245 disclose all the limitations of claim 16 as discussed above on which this claim depends. Kimura367 and Hayama245 do not explicitly teach wherein the thickness of the main body layer is greater than or equal to 2000 angstroms and less than or equal to 8000 angstroms. However, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation. Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kimura367 and Hayama245 so that wherein the thickness of the main body layer is greater than or equal to 2000 angstroms and less than or equal to 8000 angstroms for the purpose of optimizing device performance and overall size of the device. Regarding claim 18, Hayama245 teaches wherein an edge of the barrier layer is flush with an edge of the main body layer (fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein an edge of the barrier layer is flush with an edge of the main body layer for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 19, Hayama245 teaches wherein an edge of the barrier layer extends beyond an edge of the main body layer (fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein an edge of the barrier layer extends beyond an edge of the main body layer for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Regarding claim 20, Hayama245 teaches wherein the main body layer and the barrier layer comprise an inclined surface, and an orthographic projection of the main body layer on the substrate falls within an orthographic projection of the barrier layer on the substrate (fig. 1b). It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to combine the teachings of Kimura367 with that of Hayama245 so that wherein the main body layer and the barrier layer comprise an inclined surface, and an orthographic projection of the main body layer on the substrate falls within an orthographic projection of the barrier layer on the substrate for providing a cleaning composition that can suppress corrosion of the wiring material and the barrier metal material used for the wiring board, and occurrence of defects ([0008 and 0104]). Allowable Subject Matter Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The claims contain limitations that none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Nov 16, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 14, 2026
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Patent 12581639
SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
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Patent 12575180
DISPLAY PANEL, METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.3%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 557 resolved cases by this examiner. Grant probability derived from career allow rate.

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