Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 12/05/2025 via amendment. Claims 1-17 are pending examination. Claims 1-3 are currently amended. Claim 4 is as originally filed. Claims 5-17 are newly presented.
Response to Arguments
Rejections under 35 U.S.C. 101
Applicant’s arguments regarding the 35 U.S.C. 101 rejections have been fully considered. Regarding the rejection under 35 U.S.C. 101, Applicant argues “Amended claim 1, for example, includes wherein the share of the random number is mixed with a share of a calculation result to generate a privacy-protected output. This added limitation explicitly recites a practical application”. See Remarks 8 filed 12/05/2025. Applicant further argues “wherein the processing circuitry of each of the secure computation apparatuses is configured to… This is a concrete technical solution to the technical problem of high communication overhead in prior art secure computation systems… Thus, the claims are directed to a specific implementation that improves computer capabilities, similar to Enfish, LLC v. Microsoft Corp.” see Remarks 9.
Examiner respectfully disagrees with Applicant’s arguments. The recitation of the processing circuitry of each of the secure computation apparatuses is clearly an apply it scenario and generally linking the use of the judicial exception to a particular field of use. see MPEP 2106.05(h).
Further, it is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
Rejections under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1-4 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 15-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 15-16 recite “wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain the share of the random number through cooperation with others of the secure computation apparatuses” it is unclear how the processing circuitry obtain the shares through cooperation without being in communication with each other.
Claim 17 is rejected for being dependent on an above rejected claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The whole of claim 7 is a repetition of the final limitation of the amended claim 1. Specifically claim 7 only recites “wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain a share of the random number without communication with others of the secure communication apparatuses.”. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A secure random number generation system generating a concealed value of a random number following a binomial distribution (mathematical calculation) comprising (mental process, evaluation) a plurality of secure computation apparatuses, the secure computation apparatuses each comprising: (mental process, evaluation) processing circuitry configured to: (mental process, evaluation)
store a pseudorandom function and at least one set of a key and a polynomial;
obtain a pseudorandom number for each key by computing the pseudorandom function using the key; (mathematical calculation)
count a number of 1s included in each pseudorandom number; and (mental process, observation; mathematical calculation)
obtain a sum of products of the number of 1s and an output of the polynomial corresponding to the number of 1s as the share of the random number (mathematical calculation)
wherein the share of the random number is mixed with a share of a calculation result to generate a privacy-protected output, (mathematical calculation)
and wherein the processing circuitry of each of the secure computation apparatuses is configured to (mental process, evaluation) obtain a share of the random number without communication with others of the secure commutation apparatuses (mental process, evaluation).
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “generating a concealed value of a random number” limitation is a mathematical calculation that can be performed by generating the concealed value by hand using pen and paper. The “comprising” limitation is an evaluation mental process that can be performed by choosing what the system comprises. The “the secure computation apparatuses each comprising” limitation is an evaluation mental process that can be performed by choosing what the secure computation apparatuses comprise. The “processing circuitry configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain a pseudorandom number for each” limitation is a mathematical calculation that can be performed by generating the pseudorandom numbers using the keys and functions by hand using pen and paper. The “count a number of 1s” limitation is an observation mental process and mathematical calculation that can be performed by looking at the number and determining the number of 1s by hand using pen and paper. The “obtain a sum of products of the number of 1s” limitation is a mathematical calculation that can be performed by calculating the sum of products by hand using pen and paper. The “wherein the share of the random number is mixed with” limitation is a mathematical calculation that can be performed by mixing the random number by hand using pen and paper. The “and wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain a share of the random number without” limitation is an evaluation mental process and mathematical calculation that can be performed by generating the share of the random number by hand without communicating with others also generating their share by hand using pen and paper and choosing how the processing circuitry generates the share.
At step 2A Prong 2, the additional elements are bolded above. The “store” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering for the claimed obtain steps. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “store a pseudorandom function and at least one set of a key and a polynomial”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 2, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 2 is directed towards the statutory category of a machine, thus also satisfying step 1. The “store” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘store’ in the context of the claim encompasses mere data gathering for the claimed obtain steps. The remaining additional elements (a secure computation apparatus, etc.) are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “store a pseudorandom function and at least one set of a key and a polynomial”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 3, it recites similar language to claim 1 and is rejected for, at least, the same reasons therein. Herein claim 3 is directed towards the statutory category of a method, thus also satisfying step 1. Under step 2A prong 2, The “stored” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘stored’ in the context of the claim encompasses mere data gathering for the claimed obtaining steps. The remaining additional elements (a storage unit, etc.) are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “wherein a pseudorandom function and at least one set of a key and a polynomial are stored in a storage unit”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 4, It is directed to mental processes and/or mathematical concepts. The “A non-transitory computer recording medium on which a program for causing a computer to” limitation is an evaluation mental process that can be performed by choosing what the non-transitory computer recording medium does. Under step 2A prong 2, The “recorded” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘recorded’ in the context of the claim encompasses mere data gathering. The remaining additional elements (A non-transitory computer recording medium, a computer, the secure computation apparatus, etc.) are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “A non-transitory computer recording medium on which a program for causing a computer to operate as the secure computation apparatus according to claim 2 is recorded”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 5, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “locally obtain the pseudorandom number for each key by” limitation is a mathematical calculation that can be performed by computing the pseudorandom function using the key by hand using pen and paper. The “locally count the number of 1s included in each pseudorandom number” limitation is an observation mental process and mathematical calculation that can be performed by looking at the number and determining the number of 1s by hand using pen and paper. The “locally obtain the sum of the products of the number of” is a mathematical calculation that can be performed by obtaining the sum of products by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 6, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain the share of the random number through cooperation with others of the secure computation apparatuses” limitation is an evaluation mental process and mathematical calculation that can be performed by obtaining the share by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 7, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain the share of the random number without communication with others of the secure computation apparatuses” limitation is an evaluation mental process and mathematical calculation that can be performed by obtaining the share by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 8, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain the pseudorandom number by computing the pseudorandom function using the key and a parameter a that is used in common by the plurality of secure computation apparatuses” limitation is a mathematical calculation that can be performed by obtaining the pseudorandom number by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 9, it is directed to mental processes and/or mathematical concepts. The “wherein the parameter a is a time stamp” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the common parameter is. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 10, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “and obtain the share of the random number based on a sum computed for each of the plurality of sets” limitation is a mathematical relationship that can be performed by obtaining the share by hand using pen and paper. Under step 2A prong 2 the “store” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. For example, the ‘stores’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “store a plurality of sets of keys and polynomials”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well- understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 11, it is directed to mental processes and/or mathematical concepts. The “wherein the pseudorandom function is configured to” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the pseudorandom function is configured to do. The “output an L-bit pseudorandom number” limitation is a mathematical calculation that can be performed by outputting the number by hand using pen and paper. The “the number of 1s follows a binomial distribution” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the number of 1s follows. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, it is directed to mental processes and/or mathematical concepts. The “wherein the at least one set of the key and the polynomial corresponds to a set A” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the set corresponds to. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 13, it is directed to mental processes and/or mathematical concepts. The “wherein the polynomial is Fa” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the polynomial is. The “and satisfies a condition that Fa(0)= 1” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what conditions are satisfied. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 14, it is directed to mental processes and/or mathematical concepts. The “wherein the polynomial is Fa” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the polynomial is. The “and satisfies a condition that Fa(i)=0 if a” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what conditions are satisfied. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 15, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. The “obtain the pseudorandom number for each key by computing” limitation is an evaluation mental process and mathematical calculation that can be performed by obtaining the pseudorandom number by hand using pen and paper. The “locally count the number of 1s included in each” limitation is an observation mental process and mathematical calculation that can be performed by looking at the number and determining the number of 1s by hand using pen and paper. The “locally obtain the sum of the products of the number of” limitation is a mathematical calculation that can be performed by obtaining the sum of products by hand using pen and paper. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, it is directed to mental processes and/or mathematical concepts. The “wherein the processing circuitry of each of the secure computation apparatuses is configured to” limitation is an evaluation mental process that can be performed by choosing what the processing circuitry is configured to do. “obtain the share of the random number through cooperation with others” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing how the shares are obtained and obtaining them by hand using pen and paper. The “based on Shamir's secret sharing method” limitation is an evaluation mental process that can be performed by choosing how the shares are obtained. Under step 2A prong 2, none of the additional elements regarding the generic computer components (i.e. the processing circuitry, the secure computation apparatuses, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 17, it is directed to mental processes and/or mathematical concepts. The “wherein the cooperation is based on” limitation is an evaluation mental process that can be performed by choosing what the cooperation is based on. Under steps 2A prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 5-7, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Dwork et al. (US 20070083493 A1), hereinafter Dwork in view of Garcia Morchon et al. (US 20150358154 A1) hereinafter Morchon further in view of Qian et al. (US 20180054219 A1) hereinafter Qian, further in view of Kikuchi et al. (“Field Extension in Secret-Shared Form and Its Applications to Efficient Secure Computation”) hereinafter Kikuchi.
With regards to claim 1, Dwork teaches A secure random number generation system generating a concealed value of a random number following a binomial distribution (Dwork [0038]: noise can be generated by generating random bits at each computer, and sending those bits to one or more central computing devices. The central computing device can combine the random bits; Dwork Fig. 1D: Fig. 1D shows multiple computers for generating random bits; Dwork [0034]: The main work is to construct a share of the noise. Binomial noise, adequate for the case in which the functions f are 0/1 valued, is easy to construct, as there are several protocols for securely generating (shares of) relatively unbiased random bits. These shares can then be added to obtain a share of the binomial noise)
Comprising: a plurality of secure computation apparatuses (Dwork [0038]: noise can be generated by generating random bits at each computer, and sending those bits to one or more central computing devices. The central computing device can combine the random bits; Dwork Fig. 1D: Fig. 1D shows multiple computers for generating random bits)
the secure computation apparatuses each comprising processing circuitry configured to: (Dwork [0005]: The devices may also generate random bits. The random bits may be combined)
wherein the share of the random number is mixed with a share of a calculation result to generate a privacy-protected output, (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result)
and wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain a share of the random number [without communication with others of the secure communication apparatuses] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach store a pseudorandom function and at least one set of a key and a polynomial; obtain a pseudorandom number for each of the keys by computing the pseudorandom function using the key.
However, Morchon teaches store a pseudorandom function (Morchon [0010]: The electronic parameter storage is configured to store multiple functions)
and at least one set of a key and a polynomial; (Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0010]: The electronic parameter storage is configured to store multiple functions; Morchon [0018]: In a preferred embodiment one or more of the functions are polynomials)
obtain a pseudorandom number for each of the keys by computing the pseudorandom function using the key (Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0010]: The electronic parameter storage is configured to store multiple functions)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork with the pseudorandom function, key, polynomial, and obtaining the pseudorandom number of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach and obtain a sum of products of the number of 1s and an output of the polynomial corresponding to the number of 1s as a share of the random number and without communication with others of the secure communication apparatuses.
However, Kikuchi teaches and obtain a sum of products of the [number of 1s] and an output of the polynomial (of Dwork in view of Morchon) corresponding to the [number of 1s] as a share of the random number of Dwork in view of Morchon (Kikuchi Page 352 Paragraph 7: Secure Sum of Products up to Additive Attacks: This functionality captures a secure computation for the inner product of two vectors of input sharings. As with Fmult, security up to additive attacks is considered)
without communication with others of the secure communication apparatuses (Kikuchi Page 348 Paragraph 3: the parties can obtain a share of s1+s2X+···+smXm−1 ∈K from shares of s1,...,sm ∈ K without communicating).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon with the sum of products and having the apparatuses not communicate as taught by Kikuchi. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as the devices could finish their parts without waiting for data form the other devices.
Dwork in view of Morchon further in view of Kikuchi fails to teach count the number of 1s included in each pseudorandom number; and that the sum of products of Dwork in view of Morchon further in view of Kikuchi uses the number of 1s.
However, Qian does teach count the number of 1s included in each pseudorandom number; (Qian [0193]: the number of 0 and the number of 1 in the binary sequence are counted)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi with counting the 1s as taught by Qian. One of ordinary skill in the art would be motivated to make this combination because during the construction process, a small amount of computations is required, the time delay is small, and the efficiency is high as taught by Qian (Qian [0149]).
Claim 2 is directed to an apparatus that implements the same or similar features as the system of claim 1 and is therefore rejected for at least the same reasons therein.
Claim 3 is directed to a method that implements the same or similar features as the system of claim 1 and is therefore rejected for at least the same reasons therein.
Claim 4 is directed to a recording medium that implements the same or similar features as the apparatus of claim 2 and is therefore rejected for at least the same reasons therein. Furthermore, Dwork teaches a non-transitory computer recording medium to implement said features (Dwork [0057]-[0058]: The invention may be implemented in the general context of computer-executable instructions… Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions).
With regards to claim 5, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to: locally obtain the pseudorandom number [for each key by computing the pseudorandom function using the key;] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result)
locally [count the number of 1s included in each pseudorandom number;] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result)
and locally [obtain the sum of the products of the number of 1s and the output of the polynomial corresponding to the number of 1s as the share of the random number] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach for each key by computing the pseudorandom function using the key.
However, Morchon teaches for each key by computing the pseudorandom function using the key; (Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0010]: The electronic parameter storage is configured to store multiple functions).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the pseudorandom function, key, and obtaining the pseudorandom number of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach obtain the sum of the products of [the number of 1s] and the output of the polynomial corresponding to [the number of 1s] as the share of the random number.
However, However, Kikuchi teaches obtain the sum of the products of [the number of 1s] and the output of the polynomial corresponding to [the number of 1s] as the share of the random number (Kikuchi Page 352 Paragraph 7: Secure Sum of Products up to Additive Attacks: This functionality captures a secure computation for the inner product of two vectors of input sharings. As with Fmult, security up to additive attacks is considered).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the sum of products as taught by Kikuchi. One of ordinary skill in the art would be motivated to make this combination for at least the same reasons as above. Further this would increase the security of the system as using the sum of products makes it much more difficult for a third party to attack the encrypted data.
Dwork in view of Morchon further in view of Kikuchi fails to teach count the number of 1s included in each pseudorandom number; and that the sum of products of Dwork in view of Morchon further in view of Kikuchi uses the number of 1s.
However, Qian does teach count the number of 1s included in each pseudorandom number; (Qian [0193]: the number of 0 and the number of 1 in the binary sequence are counted)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with counting the 1s as taught by Qian. One of ordinary skill in the art would be motivated to make this combination because during the construction process, a small amount of computations is required, the time delay is small, and the efficiency is high as taught by Qian (Qian [0149]).
With regards to claim 6, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain the share of the random number through cooperation with others of the secure computation apparatuses (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network).
With regards to claim 7, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 5 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain the share of the random number [without communication with others of the secure computation apparatuses] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach without communication with others of the secure computation apparatuses.
However, Kikuchi teaches without communication with others of the secure communication apparatuses (Kikuchi Page 348 Paragraph 3: the parties can obtain a share of s1+s2X+···+smXm−1 ∈K from shares of s1,...,sm ∈ K without communicating).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with having the apparatuses not communicate as taught by Kikuchi. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as the devices could finish their parts without waiting for data form the other devices.
With regards to claim 12, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches [wherein the at least one set of the key and the polynomial] corresponds to a set A of the secure computation apparatuses (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach wherein the at least one set of the key and the polynomial.
However, Morchon teaches wherein the at least one set of the key and the polynomial (Morchon [0010]: the electronic parameter storage is configured to store multiple functions; Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0018]: In a preferred embodiment one or more of the functions are polynomials).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the key and polynomial of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
With regards to claim 15, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to: obtain the pseudorandom number [for each key by computing the pseudorandom function using the key] in cooperation with others of the secure computation apparatuses; (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network)
locally [count the number of 1s included in each pseudo random number] in cooperation with others of the secure computation apparatuses; (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network)
and locally [obtain the sum of the products of the number of 1s and the output of the polynomial corresponding to the number of 1s as the share of the random number] in cooperation with others of the secure computation apparatuses (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network).
Dwork fails to teach for each key by computing the pseudorandom function using the key.
However, Morchon teaches for each key by computing the pseudorandom function using the key (Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0010]: The electronic parameter storage is configured to store multiple functions).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the pseudorandom function, key, and obtaining the pseudorandom number of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach obtain the sum of the products of [the number of 1s] and the output of the polynomial corresponding to [the number of 1s] as the share of the random number.
However, However, Kikuchi teaches obtain the sum of the products of [the number of 1s] and the output of the polynomial corresponding to [the number of 1s] as the share of the random number (Kikuchi Page 352 Paragraph 7: Secure Sum of Products up to Additive Attacks: This functionality captures a secure computation for the inner product of two vectors of input sharings. As with Fmult, security up to additive attacks is considered).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the sum of products as taught by Kikuchi. One of ordinary skill in the art would be motivated to make this combination for at least the same reasons as above. Further this would increase the security of the system as using the sum of products makes it much more difficult for a third party to attack the encrypted data.
Dwork in view of Morchon further in view of Kikuchi fails to teach count the number of 1s included in each pseudorandom number; and that the sum of products of Dwork in view of Morchon further in view of Kikuchi uses the number of 1s.
However, Qian does teach count the number of 1s included in each pseudorandom number; (Qian [0193]: the number of 0 and the number of 1 in the binary sequence are counted)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with counting the 1s as taught by Qian. One of ordinary skill in the art would be motivated to make this combination because during the construction process, a small amount of computations is required, the time delay is small, and the efficiency is high as taught by Qian (Qian [0149]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Harada et al. (US 20150278309 A1) hereinafter Harada.
With regards to claim 8, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain the pseudorandom number [by computing the pseudorandom function using the key and a parameter a that is used in common] by the plurality of secure computation apparatuses (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach by computing the pseudorandom function using the key and a parameter a that is used in common.
However, Morchon teaches by computing the pseudorandom function using the key [and a parameter a that is used in common] (Morchon [0010]: the electronic parameter storage is configured to store multiple functions; Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key)
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the key of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach and a parameter a that is used in common.
However, Harada teaches and a parameter a that is used in common (Harada [0022]: Causing each segment to produce the same sequence is achieved by starting with the same initialization seed value for the random number generator on each segment).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the common parameter as taught by Harada. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as obtaining random numbers that satisfy these requirements from parallel computers is difficult, particularly in MPP databases where the number of nodes that process a query is not known in advance, and where communications between processors is impractical as taught by Harada (Harada [0002]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Harada further in view of Hart et al. (US 10055336 B1) hereinafter Hart.
With regards to claim 9, Dwork in view of Morchon further in view of Kikuchi further in view of Qian further in view of Harada teaches all of the limitations of claim 8 above. Dwork fails to teach wherein the parameter a is a time stamp.
However, Hart teaches wherein the parameter a is a time stamp (Hart Column 13 Lines 30-33: in which case process 550 selects the second seed value by applying an exclusive OR operation to the first selected hash value and the second time stamp value).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian further in view of Harada with the time stamp as taught by Hart. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system as obtaining the time stamp is faster and more efficient than generating a seed.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Unagami et al. (US 20130039491 A1) hereinafter Unagami.
With regards to claim 10, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to: (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach store a plurality of sets of keys and polynomials.
However, Morchon teaches store a plurality of [sets of keys] and polynomials (Morchon [0010]: The electronic parameter storage is configured to store multiple functions; Morchon [0018]: In a preferred embodiment one or more of the functions are polynomials).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the plurality of polynomials of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach plurality of sets of keys, and and obtain the share of the random number based on a sum computed for each of the plurality of sets.
However, Unagami teaches plurality of sets of keys (The key share generation unit may generate the plurality of regenerated key shares such that the key share from which the regenerated key shares is generated is obtained by addition of the regenerated key shares, and the key share update unit may generate the new key share by adding the regenerated key share to the key share stored therein)
and obtain the share of the random number based on a sum computed for each of the plurality of sets (Unagami [00680]: The key share generation unit may generate the plurality of regenerated key shares such that the key share from which the regenerated key shares is generated is obtained by addition of the regenerated key shares, and the key share update unit may generate the new key share by adding the regenerated key share to the key share stored therein; Unagami [0313]: In this case, for example, the key share generation unit 610 generates a random number r1 as a key share d1, a random number r2 as a key share d2, a random number r3 as a key share d3, and a random number r4 as a key share d4; Unagami [0319]: Since the key shares d1, d2, d3, d4, and d5 are generated from the encryption/decryption key d, d=d1+d2+d3+d4+d5 is satisfied).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the plurality of keys and the sum as taught by Unagami. One of ordinary skill in the art would be motivated to make this combination because it reduces the possibility of a malicious leak of the decryption key from the protection control module. As a result, security of the tampering monitoring system is increased as taught by Unagami (Unagami [0014]-[0015]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Teranishi et al. (machine translation of WO 2014132552 A1) hereinafter Teranishi.
With regards to claim 11, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the pseudorandom function is configured to output an L-bit pseudorandom number, (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result)
and the number of 1s follows a binomial distribution [Bin(L, 1/2)] (Dwork [0034]: The main work is to construct a share of the noise. Binomial noise, adequate for the case in which the functions f are 0/1 valued, is easy to construct, as there are several protocols for securely generating (shares of) relatively unbiased random bits. These shares can then be added to obtain a share of the binomial noise).
Dwork fails to teach that the binomial distribution is Bin(L, 1/2).
However, Teranishi teaches that the binomial distribution is Bin(L, 1/2) (Teranishi Page 7 Paragraph 20: An algorithm for generating random numbers according to the binomial distribution Binom (n, 1/2) is executed).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the binomial distribution as taught by Teranishi. One of ordinary skill in the art would be motivated to make this combination because it would increase the efficiency of the system because in order to generate a source efficiently for a huge parameter, the conditional probability is binomial as taught by Teranishi (Teranishi Page 4 Paragraph 14.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Katta et al. (US 5621799 A) hereinafter Katta.
With regards to claim 13, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 12 above. Dwork fails to teach wherein the polynomial is FA.
However, Morchon teaches wherein the polynomial is FA (Morchon [0010]: the electronic parameter storage is configured to store multiple functions; Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0018]: In a preferred embodiment one or more of the functions are polynomials).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the plurality of polynomials of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach and satisfies the condition that FA(0)=1.
However, Katta teaches and satisfies the condition that FA(0)=1 (Katta Column 8 Lines 57-61: When the most-significant bit (MSB) of the seed is `1`, the output of AND circuit 118 is ON, and the maximum period sequence is generated from the primitive polynomial (1-x.sup.28 -x.sup.31); (at x=0 the polynomial equals 1)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the condition of Katta. One of ordinary skill in the art would be motivated to make this combination because in addition, when only part of the data code is scrambled, such as when scramble effects control is used, a random number value is only required for the number of coded bits when the scrambled signal is obtained, but the complete random number sequence with a number of bits equivalent to the number of code bits must be available at the same time. The object of the present invention is therefore to provide a scrambled transmission system which solves these problems as taught by Katta (Katta Column 2 Lines 17-30).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Akiyama et al. (US 20070230692) hereinafter Akiyama.
With regards to claim 14, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 12 above. Dwork further teaches [and satisfies the condition that FA(i)=0 if] a secure computation apparatus {i} [is not included in the set A] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result).
Dwork fails to teach wherein the polynomial is FA.
However, Morchon teaches wherein the polynomial is FA (Morchon [0010]: the electronic parameter storage is configured to store multiple functions; Morchon [0033]: The parameter generation device is configured to obtain a cryptographic key, say receive the key or generate the key etc, and to configure the electronic parameter storage of the electronic device for generating a sequence of random numbers in dependence on the cryptographic key; Morchon [0018]: In a preferred embodiment one or more of the functions are polynomials).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the plurality of polynomials of Morchon. One of ordinary skill in the art would be motivated to make this combination because it would increase the security of the random numbers as even if a third party had access to the same source of entropy they could not reproduce the same random numbers without the key.
Dwork in view of Morchon fails to teach and satisfies the condition that FA(i)=0 if [a secure computation apparatus {i}] is not included in the set A.
However, Akiyama teaches and satisfies the condition that FA(i)=0 if [a secure computation apparatus {i}] is not included in the set A (Akiyama [0228]: The function is set at 1 when a polynomial .eta. belongs to a set S of randomizing polynomials, and the function is set at 0 when the polynomial .eta. does not belong to the set S." but I couldn't find anything about the output of a polynomial being 0 if a computing device doesn't belong in a set).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with the condition as taught by Akiyama. One of ordinary skill in the art would be motivated to make this combination because efficiency of key generation can be improved as taught by Akiyama (Akiyama [0168]).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Dwork in view of Morchon further in view of Qian further in view of Kikuchi further in view of Wu et al. (US 20190294417 A1) hereinafter Wu.
With regards to claim 16, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 1 above. Dwork further teaches wherein the processing circuitry of each of the secure computation apparatuses is configured to obtain the share of the random number through cooperation with others of the secure computation apparatuses (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network).
Dwork fails to teach based on Shamir's secret sharing method.
However, Wu teaches based on Shamir's secret sharing method (Wu [0072]: FIG. 9 illustrating an overall process 900 for generating and recovering the two prime numbers for generating a RSA key pairs in accordance with this application).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with Shamir’s secret sharing method as taught by Wu. One of ordinary skill in the art would be motivated to make this combination because it would increase the flexibility of the system as the most widely used asymmetric cryptographic algorithm is the one developed by Ron Rivest, Adi Shamir and Leonard Adelman (RSA). The RSA algorithm creates a pair of keys, namely, public key and private key. There are two ways of using an asymmetric key algorithm, namely, encryption and digital signature. Some algorithm can only do one of the two implementations. However, the RSA algorithm is capable of providing both implementations as taught by Wu (Wu [0005]).
With regards to claim 17, Dwork in view of Morchon further in view of Kikuchi further in view of Qian teaches all of the limitations of claim 15 above. Dwork further teaches wherein the cooperation is [based on Shamir's secret sharing method] (Dwork [0031]: The various computers 101, 111, 121 may each participate in generating and combining random bits, wherein a combination of random bits is used to generate noise, and the noise is ultimately combined with the collective result to obtain a collective noisy result; Dwork [0057]: The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network).
Dwork fails to teach based on Shamir's secret sharing method.
However, Wu teaches based on Shamir's secret sharing method (Wu [0072]: FIG. 9 illustrating an overall process 900 for generating and recovering the two prime numbers for generating a RSA key pairs in accordance with this application).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings Dwork in view of Morchon further in view of Kikuchi further in view of Qian with Shamir’s secret sharing method as taught by Wu. One of ordinary skill in the art would be motivated to make this combination because it would increase the flexibility of the system as the most widely used asymmetric cryptographic algorithm is the one developed by Ron Rivest, Adi Shamir and Leonard Adelman (RSA). The RSA algorithm creates a pair of keys, namely, public key and private key. There are two ways of using an asymmetric key algorithm, namely, encryption and digital signature. Some algorithm can only do one of the two implementations. However, the RSA algorithm is capable of providing both implementations as taught by Wu (Wu [0005]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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