Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed October 10th, 2025 does not place the application in condition for allowance.
The rejections over Nishida et al. in view of Eid et al. are maintained.
The rejections over Nishida et al. in view of Bauer et al. are withdrawn due to Applicant’s amendment.
The rejections over Nishida et al. in view of Savelli et al. are withdrawn due to Applicant’s amendment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (JP 2015-135932 A) in view of Eid et al. (US 2021/0043543 A1) as evidenced by Anson “LGA vs PGA – CPU Socket Types Explained” in view of Inada et al. (US 2015/0035989 A1). Nishida et al. is mapped to the English machine translation provided by the EPO.
In view of Claim 1, Nishida et al. teaches a sensor device (Figure 5-6) comprising: a peltier element (Figure 5-6, #1/#2 & #21 - Paragraph 0031), a sensor element thermally connected to a cooling surface of the Peltier element (Figure 5-6, #20, in Fig. 6 the sensor element is bonded to the cooling surface but not shown - Paragraph 0011-0013, 0016 & 0031); and a package substrate that is made of ceramic and is thermally connected to a heat dissipation surface of the Peltier element and accommodates the Peltier element and the sensor element (Figure 5-6, #4 & Paragraph 0031), wherein the package substrate has a substantially rectangular parallelepiped shape (Figs. 5-6), wherein a plurality of external terminals are provided on a bottom surface of the package substrate (Figure 6, below #25 & Paragraph 0031).
Nishida et al. does not disclose that the plurality of external terminals protrude downward from the bottom surface of the package substrate and wherein the plurality of external terminals are connected to a plurality of wirings provided in the package substrate.
Eid et al. teaches a plurality of external terminals (Figure 13, #156/#158 & Paragraph 0028) that protrude downward from the bottom surface of a package substrate (Figure 13, #102 & Paragraph 0028), wherein the plurality of external terminals are connected to a plurality of wirings provided in the package substrate (Figure 13, #127 & Paragraph 0045 – coupled to any signal or power/ground pathways).
Eid et al. disclose that’s the external pin terminals may be in the form of a pin grid array package (PGA) (Paragraph 0028). As evidenced by Anson, this corresponds to the external pin terminals being disposed in a first matrix having a plurality of rows and a plurality of columns (Page 2, 1st Figure & Paragraph 1-2). Eid et al. teaches that this configuration may help transfer heat to dissipate heat of the face of a package substrate while still performing a thermal function (Paragraph 0045). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the package substrate of Eid et al. as Nishida et al. such that the plurality of external terminals that protrude downward from the bottom surface of the package substrate and wherein the plurality of external terminals are connected to a plurality of wirings provided in the package substrate for the advantages of helping dissipating heat of the package substrate while performing a thermal function.
Nishida et al. does not disclose a wiring layer of a relay substrate, and a bonding pad provided in a stepped portion of the package substrate are electrically connected by a bonding wire.
Inada et al. teaches a wiring layer of a relay substrate (Figure 1, #50 & #70 – Paragraph 0042-0044), and a bonding pad provided in a stepped portion (See Annotated Inada et al. Figure 1, below & Paragraph 0046 – the portion where wiring 77 is bonded to section package main body 62) of a substantially rectangular parallelepiped shape (Fig. 1, #60) that are electrically connected by a bonding wire (Figure 1, #77 – Paragraph 0044). Inada et al. teaches that his optical sensor can be cooled with a Peltier device (Paragraph 0007). Inada et al. discloses that this configuration results in a uniform light intensity distribution on an image surface and thus has a high image quality (Paragraph 0013). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the configuration of modified Nishida et al. incorporate a wiring layer of a relay substrate, and a bonding pad provided in a stepped portion of the package substrate are electrically connected by a bonding wire for the advantages of having uniform light intensity distribution on an image surface and thus high image quality.
Annotated Inada et al. Figure 1
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In view of Claim 2, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 1. Nishida et al. teaches the plurality of external terminals (Figure 6, #25) and the Peltier element are provided at different positions in a plan view (Figure 6, #1/#2 & #21). Eid et al. was relied upon to disclose why it would be obvious to use a plurality of external terminals protruding from the back package substrate of Nishida.
In view of Claim 3, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 2. Nishida et al. discloses the peltier element (Figure 5-6, #1/#2 & #21) covers a central portion of the back surface of the package substrate, which is flat and provides a heat dissipation surface corresponding the Peltier element (Figure 6, #4 – back surface is flat). Eid et al. was relied upon to disclose why it would be obvious to use a configuration in which a plurality of external terminals are provided on the back surface of a package substrate (Figure 13, #156/#158), thus the combination of Eid et al. with Nishida et al. results in a sensor device where the bottom heat dissipation area of the bottom surface of the package substrate is shared with the plurality of external terminals.
In view of Claim 4, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 3. Nishida et al. teaches that the bottom heat dissipation area is wider than the Peltier element (Figure 6, the portion of the ceramic substrate the Peltier element is nestled within is smaller than the package substrate 4).
In view of Claim 6, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 2. Nishida et al. teaches the Peltier element is nestled into the center part of the back surface of the package substrate in a plan view (Figure 6, #1/#2 & #21 – Paragraph 0031).
Eid et al. was relied upon to disclose why it would be obvious to utilize a configuration in which a plurality of external terminals that protrude downward from the bottom surface of a package substrate (Figure 13, #156/#158 cover the back surface of a package substrate). The resulting combination of a plurality of external terminals on Nishida et al. back surface package substrate would result in the central Peltier element of Nishida et al. being surrounded by the plurality of external terminals that would be provided on the periphery of the back surface of the package substrate.
In view of Claim 7, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 1. Nishida et al. teaches a side heat dissipation area, which is flat, is provided on a side surface of the package substrate (Figure 4, the side surfaces above elements 25 meets this limitation).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (JP 2015-135932 A) in view of Eid et al. (US 2021/0043543 A1) as evidenced by Anson “LGA vs PGA – CPU Socket Types Explained” in view of Inada et al. (US 2015/0035989 A1) in view of Machine Vision Blog “How Does Shortwave Infrared Imaging Work?”. Nishida et al. is mapped to the English machine translation provided by the EPO.
In view of Claim 8, Nishida et al., Eid et al., and Inada et al. are relied upon for the reasons given above in addressing Claim 1. While Nishida et al. discloses that the sensor can be utilized to detect infrared light (Paragraph 0002), its not explicitly disclosed that the sensor element is a short wave infrared (SWIR) image sensor.
Machine Vision Blog discloses that shortwave infrared imaging introduces a broad range of possibilities in industrial and scientific applications such that vision systems leveraging SWIR technology can capture images in wavelengths deeper within the infrared spectrum, allowing these systems to see details outside of the visible spectrum (Page 1, 1st Paragraph). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate a short-wave infrared image sensor as the sensor element of Nishida et al. for the advantage of being able to capture images in wavelengths deeper within the infrared spectrum, allowing these systems to see details outside of the visible spectrum.
Response to Arguments
Applicant argues that Eid et al. does not disclose that the external pin terminals are disposed in at least a first matrix having a plurality of rows and a plurality of columns. The Examiner respectfully points out to Applicant that Eid et al. disclose that’s the external pin terminals may be in the form of a pin grid array package (PGA) (Paragraph 0028). As evidenced by Anson, this corresponds to the external pin terminals being disposed in a first matrix having a plurality of rows and a plurality of columns (Page 2, 1st Figure & Paragraph 1-2). Accordingly, this argument is unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P MALLEY JR. whose telephone number is (571)270-1638. The examiner can normally be reached Monday-Friday 8am-430pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 571-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL P MALLEY JR./Primary Examiner, Art Unit 1726
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