DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 14 January 2026 has been entered.
Applicant has amended claims 1 and 10. Claims 1-5 and 7-16 are pending.
Response to Arguments
Applicant’s arguments filed on 14 January 2026 have been considered and are not persuasive.
Applicant asserts that the amended limitations in claim 1 are not disclosed cited sources due to the location of the drain on the second end of the plurality of transistor pillars at which a drain of the respective transistor is located. Applicant identifies reference Glass, specifically fig. 5A-6, showing that a backside thinning process disclosed cannot reach the S/D region located on the “second end” when only reaching the sub-fin 221, or in the alternative, when the fin is removed, both source and drain are located in this region, as opposed to only the drain as claimed in the instant application’s amended claims.
However, Glass is only relied upon for the backside thinning process that can applied to the structure of the transistor array, as formed by the method of Forbes in view of Sandhu. Forbes discloses forming a source at a first end and forming a drain at a second end, as applied in previous rejections to claim 1.
Therefore, the thinning process of Glass applied to the second end of the wafer formed by the method disclosed by Forbes in view of Sandhu would expose the second end where only the source or drain is located, disclosing the claimed limitation by combination of Forbes, Sandhu, and Glass.
Applicant applies this assertion to the similar features in amended claim 10 which are similarly disclosed by the aforementioned prior art, where Sandhu also discloses a structure where source and drain are at opposite ends of the mesa structure (Sandhu fig. 3A). .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-9, and 11 rejected under 35 U.S.C. 103 as being unpatentable over Forbes US Patent 7564088 (hereinafter Forbes) in view of Sandhu et al. US PGPUB No. 20120326242 (hereinafter Sandhu) and Glass et al. US PGPUB No. 20190157310 (hereinafter Glass).
Regarding claim 1, Forbes discloses (figs. 1-15) a method for manufacturing a transistor array, comprising:
providing a wafer (102, 4:39-54);
partially etching the wafer from a first surface of the wafer along a first direction, to form a grid-like etched trench and a transistor pillar array (trenches 210 and 212 forming the array, fig. 12, 3:34-49, 8:34-38), each of the plurality of transistor pillars has a first preset thickness smaller than an initial thickness of the wafer (fig. 12, where first thickness must be smaller than wafer thickness due to use of etching process showing remaining substate below the pillars), the first direction is a thickness direction of the wafer and is perpendicular to the first surface (Forbes disclosed trenches 210 and 212 in first and second direction along forming a plane acting as the first surface and the direction normal to this plane would be the claimed first direction, fig. 12, 8:33-38);
depositing an insulating material (214, 8:39-41) in the grid-like etched trench to form an insulating layer surrounding each of the plurality of transistor pillars (fig. 12);
etching the insulating layer (214) to expose a first sidewall and a second sidewall (8-39-46), opposite to each other in a second direction perpendicular to the first direction, of each of the plurality of transistor pillars (fig. 13);
forming a gate oxide layer (120, 5:16-17) and a gate (122, 5: 17-21) sequentially on each of the first sidewall and the second sidewall (fig. 14, 8:59-61);
forming a source (106, 8:47) at a first end of each of the plurality of transistor pillars (fig. 15); and
forming the drain (110, 8:49-50) at the second end of each of the plurality of transistor pillars (fig. 2)
Forbes further discloses that the source (106) and the drain (110) of the respective transistor are respectively located at the first end and the second end that are opposite ends of a respective transistor pillar in the first direction (fig. 2, where source and drain are opposite ends in the first or vertical direction within the pillar) and the plurality of transistor pillars are isolated from each other (5:5-7, where depletion regions isolate pillars from the substrate, and by extension, provide isolation from other pillars on the substrate), wherein the second surface of the wafer is a surface opposite to the first surface of the wafer (fig. 2).
Forbes does not disclose thinning the wafer from a second surface of the wafer until exposing a second end of each of the plurality of transistor pillars at which a drain of a respective transistor is located, and when forming the drain, wherein a part of each of the plurality of transistor pillars between the source and the drain forms a channel region of the respective transistor.
In the same field of endeavor, Sandhu discloses (figs. 1-3B) a transistor array (with transistor mesas 320 forming the array, Sandhu, ¶18-22) wherein a part of each of the plurality of transistor pillars between the source (140, Sandhu, ¶19) and the drain (130, Sandhu, ¶19) forms a channel region (125, Sandhu, ¶30) of the respective transistor. It would have been obvious to one of ordinary skill in the art at the time of filing to include a channel disclosed by Sandhu within the transistors within the array of Forbes, allowing for more versatility in transistor function.
Forbes and Sandhu do not disclose thinning the wafer from a second surface of the wafer until exposing a second end of each of the plurality of transistor pillars at which a drain of a respective transistor is located.
In the same field of the endeavor, Glass discloses backside thinning (Glass, ¶12) to reveal the backside or underside of the device layer (Glass fig. 5A-6 ¶38-42, where device layer 220 is etched to the backside, providing isolated transistor pillars 221). It would have been obvious to one of ordinary skill in the art at the time of filing to thin the wafer from a second surface of the wafer until exposing the second end of each of the plurality of isolated transistor pillars of Forbes in view of Sandhu, improving device performance by reducing contact resistance for the source/drain region (Glass, ¶12).
Regarding claim 2, Forbes in view Sandhu and Glass discloses the method of claim 1,
wherein the etching the insulating layer to expose the first sidewall and the second sidewall, opposite to each other in the second direction perpendicular to the first direction, of each of the plurality of transistor pillars comprises:
partially etching the insulating layer along the first direction with positions of a first edge and a second edge, opposite to each other in the second direction, of each of the plurality of transistor pillars as the etching start point, to remove the insulating layer with a preset size in the second direction and with a second preset thickness in the first direction, to form a plurality of etched trenches arranged in parallel along the second direction (Forbes, 8:41-46, where the oxide along the direction for trenches 210 is etched away but left between adjacent pillars in the other direction of the first plane, fig. 13),
wherein each of the plurality of etched trenches exposes a sidewall of each of the plurality of transistor pillars arranged in parallel along a third direction correspondingly, a plane where the third direction and the second direction are located is perpendicular to the first direction, the third direction intersects with the second direction (fig. 13);
the preset size is smaller than an interval between two adjacent transistor pillars in the second direction (Forbes, 9:4-12, where the array is disclosed as rectangular, where the interval between two transistor pillars would be smaller than in the other direction); and
the second preset thickness is smaller than or equal to the first preset thickness (Forbes discloses oxide 214 “substantially absent along the trenches 210,” Forbes, 8:46, indicating this anisotropic etch of second preset thickness is smaller than the first as it does not completely remove the oxide in the trench).
Regarding claim 3, Forbes in view of Sandhu and Glass discloses the method of claim 2.
Forbes in view of Sandhu does not explicitly disclose the sequence wherein the forming the gate oxide layer and the gate sequentially on each of the first sidewall and the second sidewall comprises: forming, by in-situ oxidation, the gate oxide layer on each of the first sidewall and the second sidewall; depositing a conductive material in the etched trench formed with the gate oxide layer to form a conductive layer; and etching the conductive layer along the first direction, to remove part of the thickness of the conductive layer in the first direction to form the gate.
Forbes in view of Sandhu discloses an oxide as the gate dielectric in claim 1. It would have been obvious to one of ordinary skill in the art at the time of filing to use thermal processes for in-situ growth for the gate oxide, using a common practice to provide a cost-efficient insulation layer for the gate.
Sandhu discloses a conductive material in the etched trench formed with the gate oxide layer (355, Sandhu ¶19-21) to form a conductive layer (352, Sandhu ¶19, 22-25). It would have been obvious to one of ordinary skill in the art at the time of filing to use the conductive material disclosed by Sandhu in the array of Forbes, supporting higher energy associated with channel of Sandhu applied to the transistor of Forbes in claim 1. It would have been obvious to one of ordinary skill in the art at the time of filing to remove part of the thickness of the conductive layer by etching as disclosed by Forbes, allowing the conductive material to also form the gate, reducing cost by removing depositing gate conductive material as an additional step.
Regarding claim 4, Forbes in view of Sandhu and Glass discloses the method of claim 2,
Forbes in view of Sandhu does not explicitly disclose the sequence wherein the forming the gate oxide layer (120, Forbes, 5:16-17) and a gate (122, Forbes, 5: 17-21) sequentially on each of the first sidewall and the second sidewall comprises: forming, by in-situ oxidation, an initial gate oxide layer on each of the first sidewall and the second sidewall; depositing a conductive material in the etched trench formed with the initial gate oxide layer, to form a conductive layer; and etching the initial gate oxide layer and the conductive layer along the first direction, to remove part of the thicknesses of the initial gate oxide layer and the conductive layer in the first direction to form the gate.
Forbes in view of Sandhu discloses an oxide as the gate dielectric in claim 1. It would have been obvious to one of ordinary skill in the art at the time of filing to use thermal processes for in-situ growth for the initial gate oxide, using a common practice to provide a cost-efficient insulation layer for the gate.
Sandhu discloses a conductive material in the etched trench formed with the gate oxide layer (355, Sandhu ¶19-21) to form a conductive layer (352, Sandhu ¶19, 22-25). It would have been obvious to one of ordinary skill in the art at the time of filing to use the conductive material disclosed by Sandhu in the array of Forbes, supporting higher energy associated with channel of Sandhu applied to the transistor of Forbes in claim 1. It would have been obvious to one of ordinary skill in the art at the time of filing to remove part of the thickness of the conductive layer by etching as disclosed by Forbes, allowing the conductive material to also form the gate, reducing cost by removing depositing gate conductive material as an additional step.
Regarding claim 5, Forbes in view of Sandhu and Glass discloses the method of claim 2.
Sandhu discloses further comprising after forming the gate oxide layer and the gate: forming an isolation layer (390, Sandhu, ¶20,22) by deposition in the etched trench, wherein a size of the isolation layer in the third direction is larger than a size of each of the plurality of transistor pillars in the third direction. The isolation layer (390, Sandhu, not shown in fig. 3C, ¶22) extends along multiple mesas/pillars. It would have been obvious to one of ordinary skill in the art at the time of filing to fill in gaps between transistors, preventing other, undesirable materials from entering the gaps and disrupting device function.
Regarding claim 7, Forbes in view of Sandhu and Glass discloses the method of claim 1,
wherein cross-sectional shapes of the source (106, 8:47) and the drain (110, 8:49-50) parallel to a preset plane are the same (Sandhu, figs. 3A-3B) or different (Forbes, fig. 15), and the preset plane is perpendicular to the first direction (a top or plan view); and the cross-sectional shapes of the source and the drain parallel to the preset plane comprise any one of a square, a semicircle, a triangle, or any polygon. Forbes and Sandhu each disclose a polygon shape of the source and drain regions in the top view.
Regarding claim 8, Forbes in view of Sandhu and Glass discloses the method of claim 1,
wherein each of the plurality of transistor pillars is a columnar transistor pillar (fig. 12), and a length of each of the first sidewall and the second sidewall in the first direction is smaller than the first preset thickness (Forbes discloses oxide 214 “substantially absent along the trenches 210,” Forbes, 8:46, indicating this anisotropic etch of second preset thickness is smaller than the first as it does not completely remove the oxide in the trench).
Regarding claim 9, Forbes in view of Sandhu and Glass discloses the method of claim 1,
wherein each of the plurality of transistor pillars is an inverted T-shaped transistor pillar (Forbes, fig. 15), and a length of each of the first sidewall and the second sidewall in the first direction is equal to the first preset thickness (Forbes, fig. 12, where first thickness must be smaller than wafer thickness due to use of etching process showing remaining substate below the pillars).
Regarding claim 11, Forbes in view of Sandhu and Glass disclose a method of claim 1.
Forbes in view of Sandhu discloses forming at least one memory array (array of memory cells 100, Forbes, 7:19), each of which comprising at least a transistor array comprising a plurality of transistors (formed in pillars 104, Forbes, 4:42-59) arranged in an array (Forbes, fig. 12), each of the plurality of transistors comprising double gates (122, Forbes, fig. 15, 5: 17-21), a source (106, Forbes, 8:47) and a drain (110, Forbes, 8:49-50), and the transistor array being manufactured by the method of claim 1.
Forbes further discloses forming a plurality of word lines (122, Forbes, 6:8-12) arranged in parallel along a third direction (fig. 15), each of the plurality of word lines connected to the double gates of each of the plurality of transistors arranged in parallel along the third direction (fig. 15), and configured to provide a word line voltage and control each of the plurality of transistors to be turned on or off by the word line voltage (Forbes, 6:8-12); and
forming a plurality of bit lines (112, Forbes, 4:61-63) arranged in parallel along a second direction (Forbes, 4:62-63), each of the plurality of bit lines connected to the source or the drain of each of the plurality of transistors arranged in parallel along the second direction (Forbes, 4:61-63), and configured to perform a read or write operation on each of the plurality of transistors when each of the plurality of transistors is turned on (Forbes, 6:28-34), the third direction intersects with the second direction (shown in figs. 12-15), and a plane where the third direction and the second direction are located is perpendicular to the first direction.
Claims 10, 12, and 16 rejected under 35 U.S.C. 103 as being unpatentable over Sandhu in view of Glass.
Regarding claim 10, Sandhu discloses (figs. 1-4) a transistor array, comprising a plurality of transistors (320, ¶18-22) arranged in an array (fig. 4), each of the plurality of transistors comprising: a channel region (125, ¶30);
a source (140, ¶19) located at a first end of the channel region (figs. 3A-3B);
a drain (130, ¶19) located at a second end of the channel region (figs. 3A-3B), wherein the first end and the second end, at which the drain is located are opposite ends of the channel region in a first direction which is a thickness direction of a wafer forming the channel region (vertical direction, fig. 3A);
double gates (350, ¶19) located on two sides of the channel region respectively (fig. 3A), each of the double gates corresponding to the channel region (125);
a gate oxide layer (355, ¶19-21) located between the channel region and each of the double gates (350);
and an isolation layer (390, ¶20,22) arranged on each of the double gates (350) along the first direction and extending along a third direction (aligned with the array shown in fig. 3B), wherein a size of the isolation layer in the third direction is greater than a size of the channel region in the third direction (fig. 3B), and the third direction is parallel to a column arrangement direction of the transistor array (fig. 3B).
Sandhu does not disclose wherein the second end is exposed by thinning the wafer, and the plurality of transistors are isolated from each other.
In the same field of the endeavor, Glass discloses backside thinning (Glass, ¶12) to reveal the backside or underside of the device layer (Glass fig. 5A-6 ¶38-42, where device layer 220 is etched to the backside, providing isolated transistor pillars 221). It would have been obvious to one of ordinary skill in the art at the time of filing to thin the wafer from a second surface of the wafer until exposing the second end of each of the plurality of isolated transistor pillars, improving device performance by reducing contact resistance for the source region (Glass, ¶12).
Regarding claim 12, Sandhu in view of Glass discloses a semiconductor device, comprising: at least one memory array (array of memory cells 220), a plurality of word lines (shared 350 common gate can act as a word line, fig. 4, ¶22) arranged in parallel along a third direction (shown vertical in top view of fig. 4), and a plurality of bit lines (322, ¶23) arranged in parallel along a second direction (shown horizontal in fig. 4); wherein each of the at least one memory array comprises the transistor array of claim 10.
each of the plurality of transistors comprises at least double gates (350, ¶19), a source (140, ¶19) and a drain (130, ¶19); and the third direction intersects with the second direction, and a plane where the third direction and the second direction are located is perpendicular to the first direction;
each of the plurality of word lines is connected to the double gates of each of the plurality of transistors arranged in parallel along the third direction (shared 350 common gate can act as a word line, fig. 4, ¶22), and is configured to provide a word line voltage and control each of the plurality of transistors to be turned on or off by the word line voltage; and
each of the plurality of bit lines (322) is connected to the source (140) or the drain (130) of each of the plurality of transistors arranged in parallel along the second direction, and is configured to perform a read or write operation on each of the at least one memory array when each of the plurality of transistors is turned on (shared source contacts allow current flow to a selected memory cell for memory access that would allow read or write operations, ¶30).
Regarding claim 16, Sandhu in view of Glass discloses the semiconductor device of claim 12,
when the semiconductor device comprises a plurality of memory arrays, the plurality of memory arrays are connected in parallel or in series. Sandhu discloses multiple memory arrays (fig. 4 divided between left and right side) connected by shared bit lines (322, ¶23).
Claim 13 rejected under 35 U.S.C. 103 as being unpatentable over Sandhu in view of Glass and Forbes.
Regarding claim 13, Sandhu in view of Glass discloses the semiconductor device of claim 12.
Sandhu does not disclose wherein each of the at least one memory array further comprises a storage capacitor, the storage capacitor has one end connected to the drain or the source of the transistor and the other end grounded, and is configured to store data written into each of the at least one memory array.
In the same field of endeavor, Forbes discloses (fig. 4) wherein each of the at least one memory array further comprises a storage capacitor (132, Forbes, 5:54-67), the storage capacitor has one end connected to the drain or the source of the transistor and the other end grounded (Forbes, fig. 4), and is configured to store data written into each of the at least one memory array (Forbes, 6:39-47).
It would have been obvious to one of ordinary skill in the art at the time of filing to use a capacitor disclosed by Forbes in the memory device of Sandhu, providing a more space-efficient memory storage array.
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Sandhu in view of Glass and Kumura et al. US PGPUB No 20080230818 (hereinafter Kumura).
Regarding claim 14, Sandhu discloses the semiconductor device of claim 12 of the at least one memory array.
Sandhu does not disclose wherein each of the at least one memory array further comprises a ferroelectric capacitor, the ferroelectric capacitor comprises an upper electrode, a lower electrode and a ferroelectric material layer located between the upper electrode and the lower electrode;
the upper electrode of the ferroelectric capacitor is connected to the drain of the transistor, and the lower electrode of the ferroelectric capacitor is connected to the source of the transistor, and the ferroelectric capacitor is configured to store data written into each of the at least one memory array.
In the same field of endeavor, Kumura discloses (figs. 1-9) a memory device (10, Kumura, ¶34) that further comprises a ferroelectric capacitor (13, Kumura, ¶34, 42),
the ferroelectric capacitor comprises an upper electrode (30, Kumura, ¶34, 42),
a lower electrode (29, Kumura, ¶34, 42) and
a ferroelectric material layer (28, Kumura, ¶34, 42) located between the upper electrode and the lower electrode(Kumura, fig. 2, ¶34, 42);
the upper electrode (30) of the ferroelectric capacitor is connected to the drain of the transistor (connected through contact plug 72, Kumura, fig. 9, ¶95), and the lower electrode (29) of the ferroelectric capacitor is connected to the source of the transistor (connected through first contact plug 26, Kumura ¶41-43), and the ferroelectric capacitor is configured to store data written into each of the at least one memory array (Kumura ¶35).
It would have been obvious to one of ordinary skill in the art at the time of filing to use a ferroelectric capacitor disclosed by Kumura in the memory device of Sandhu, providing improved write speeds and lower power consumption over other capacitor types.
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Sandhu in view of Glass and Wu et al. US PGPUB No. 20220020419 (hereinafter Wu).
Regarding claim 15, Sandhu discloses the semiconductor device of claim 12.
Sandhu discloses varying resistance memory states “as a result of changes in current induced magnetization of the cell material” (Sandhu, ¶4), but does not disclose wherein each of the at least one memory array further comprises an adjustable resistor, the adjustable resistor is connected between the bit line and the source of the transistor, or is connected between the bit line and the drain of the transistor, and is configured to adjust a state of data stored in each of the at least one memory array by a bit line voltage provided by the bit line.
In the same field of endeavor, Wu discloses (Wu, figs. 1-6) a memory controller wherein transistors adjustable resistors (such as RWPU[1], Wu, ¶18), providing a plurality of data signals to the memory modules. It would have been obvious to one of ordinary skill in the art at the time of filing to apply adjustable resistors disclosed by Wu as the varying resistance memory components of Sandhu, connecting to bit line and source or drain, improving the memory device by making it non-volatile in case of power loss.
Conclusion
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/Seth D Lawson/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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