DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-13 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7, 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scherr [US 20200244481].
As to claim 1, Scherr discloses Method of communication between a first electronic circuit, [fig. 1, 0029] master 11, and second electronic circuits, [fig. 1, 0029] slaves 12, via a bidirectional bus, [fig. 11, 0030] bus 13 that can be configured for bidirectional communication, allowing the full duplex communication, [0036] the bus implements a UART (Universal Asynchronous Receiver Transmitter) interface; wherein UART is a full-duplex communication interface, each second electronic circuit having a single identifier corresponding thereto, [fig. 7, 0075] slave identification, the method comprising
the transmission by the first electronic circuit of first frames over the bus to the second electronic circuits, [fig. 7, 0075] the master communicates with the slave using a DESERT frame, [0116] that is implemented using a UART-based interface,
each first frame comprising the same number of bits, [fig. 7, 0066, 0076] the frame comprises a specific length of bits selected for the specific implementation and are the same,
the bits of each first frame being distributed in successive groups of bits, [fig. 7] predetermined succession of bits for each block of data,
the positions of the groups being the same in each first frame, [fig. 6, 0066, 0076] each frame is the same, with the same arrangement of blocks,
the first frames being such that, in each first frame,
a first group of bits among the groups of bits indicates a corresponding first identifier among the identifiers, [fig. 7, 0077] a symbol used to identify slaves (ID) can include more than one ID,
a second group of bits among the groups of bits indicates corresponding orders to be executed by the second electronic circuit corresponding to the first identifier of the first frame, [fig. 7, 075] command (CMD) following the ID of the slave to which the command is directed, and
a third group of bits among the groups of bits indicates a corresponding second identifier among the identifiers, [fig. 7, 0077] slave ID after trigger symbols,
the method being such that, as a response to the first frame of the plurality of first frames, only the second electronic circuit indicated by the corresponding second identifier is authorized to transmit a second frame to the first electronic circuit over the bus, [0075] the slave identified by the ID responds, and transmits a second frame to the first electronic circuit over the bus, [0075, 0079] the slave identified by the ID responds with a second frame.
As to claim 2. Scherr discloses Method according to claim 1, wherein the first electronic circuit modifies the third group of bits of the first frames to cyclically scan all the identifiers according to a given order, [0077] the master changes the ID frame to identify the required slave.
As to claim 7. Scherr fails to disclose Method according to claim 1, wherein, when the first identifier and the second identifier are the same, the second electronic circuit corresponding to the first identifier executes the orders before the sending of the second frame, [0075].
As to claim 10 is rejected using the same prior arts and reasoning as to that of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scherr in view of Mishra et al. [US 20180357199].
As to claim 3. Scherr fails to disclose Method according to claim 1, wherein the first electronic circuit transmits a succession of first frames with a third group of words corresponding to the same second identifier if it has not received a second frame transmitted by the second electronic circuit corresponding to the second identifier.
Mishra teaches a communication in a bus topology comprising a master 1302 and a plurality of slaves 1304-1308, [fig. 13, 0127], implementing a full duplex, bidirectional communication, [0118, 0127]; wherein the host resends a packet to a slave that does not reply with confirmation packet wherein the communication is performed successively, [0063].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of Mishra so that the master can confirm that the slave received the command.
As to claim 4. Scherr fails to disclose Method according to claim 3, wherein the first electronic circuit successively transmits a plurality of first frames with the third group of words corresponding to a given value which does not correspond to one of the identifiers if, after the transmission of said succession of first frames, it still has not received a second frame transmitted by the second electronic circuit corresponding to the second identifier.
Mishra teaches a communication in a bus topology comprising a master 1302 and a plurality of slaves 1304-1308, [fig. 13, 0127], implementing a full duplex, bidirectional communication, [0118, 0127]; wherein the host resends the packet to a slave that does not reply with confirmation packet wherein the communication is performed successively, [0063].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of Mishra so that the master can confirm that the slave received the command.
Claim(s) 5, 6, 8, 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Scherr in view of de Greef et al. [US 20150104673].
As to claim 5, Scherr fails to disclose Method according to any of claim1, wherein the first electronic circuit and the second electronic circuits form part of a battery of electrical accumulators, the electrical accumulators being distributed in assemblies of electrical accumulators, each second electronic circuit corresponding to the first identifier controlling the connection or the disconnection of each electrical accumulator of one of the assemblies based on said orders.
De Greef teaches a communication bus and control comprising a battery manager 130 and battery sections 140-144 configured to communicate in a bi-directional communication bus using a master-slave communication protocol, [fig. 1, 0035]; which can be implemented using a full-duplex channel, [0102]; wherein the command from the battery manager includes disconnecting all battery cells, [0086].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of de Greef so that the system can protect the batteries in case of an emergency.
As to claim 6, Scherr fails to disclose Method according to claim 5, wherein the orders are orders to turn on or off switches coupling the electrical accumulators.
De Greef teaches a communication bus and control comprising a battery manager 130 and battery sections 140-144 configured to communicate in a bi-directional communication bus using a master-slave communication protocol, [fig. 1, 0035]; which can be implemented using a full-duplex channel, [0102]; wherein the command from the battery manager includes disconnecting all battery cells, [0086].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of de Greef so that the system can protect the batteries in case of an emergency.
As to claim 8, Scherr discloses Method according to any of claim 1, wherein each second electronic circuit is coupled to at least one sensor, [0031] and wherein the second frame comprises data representative of at least one value measured by the sensor coupled to the second electronic circuit corresponding to the second identifier, [0078] the data from the sensor can be sensor data.
Mishra fails to disclose wherein the sensor is voltage and/or current.
De Greef teaches a communication bus and control comprising a battery manager 130 and battery sections 140-144 configured to communicate in a bi-directional communication bus using a master-slave communication protocol, [fig. 1, 0035]; which can be implemented using a full-duplex channel, [0102]; wherein the status data includes measurement of current and/or voltage, [0029].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of de Greef so that the system can be used to monitor battery status.
As to claim 9, Scherr fails to disclose Method according to any of claim 1, wherein the transmission by the first electronic circuit of the first frames over the bus to the second electronic circuits is performed periodically.
De Greef teaches a communication bus and control comprising a battery manager 130 and battery sections 140-144 configured to communicate in a bi-directional communication bus using a master-slave communication protocol, [fig. 1, 0035]; which can be implemented using a full-duplex channel, [0102]; wherein the battery manager periodically send the command messages, [0078].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Scherr with that of de Greef so that the system can monitor battery status periodically to avoid unexpected failures.
As to claim 11 is rejected using the same prior arts and reasoning as to that of claim 5.
Allowable Subject Matter
Claims 12, 13 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art of record does not disclose nor suggest individually or in combination the claimed electronic system and method as claimed in claim 1; wherein the frequency of transmission of the first frames is in a range from 1 kHz to 50 kHz.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 08/07/2026 have been fully considered but they are not persuasive.
Argument 1: The Office Action’s consideration of the frame TRIGGER (master) to include multiple identifiers ID is incorrect. The identifier ID can take different values depending on the number of slave circuits. The frame TRIGGER (master) sent by the master circuit contains only one identifier ID.
Response 1: Scherr [0077] specifically describes that the ID symbol “or example, in a case with four slaves, each value (0, 1, 2, and 3) may identify one of the slaves. In a case with three slaves, values 1-3 may identify the three slaves individually, … . It should be noted that in systems with more slaves, for example the symbol format of FIG. 5 may be used, where 3-bit values may be encoded, or more than 1 symbol may be used for addressing.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENYAM HAILE whose telephone number is (571)272-2080. The examiner can normally be reached 7:00 AM - 5:30 PM Mon. - Thur..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached at (571)270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Benyam Haile/Primary Examiner, Art Unit 2688
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