Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Status of the Claims
The Examiner acknowledges amended claim 1 incorporating original claims 2 and 3, amended claim 12 incorporating amended claims 13 and 14, amended claim 23, and cancellation of claims 2-4, and 13-15.
Drawings
The Examiner acknowledges amendments to the applicant’s drawings. The Examiner withdraws objections to the drawings due to amendments to the drawings and cancellation of claims 4 and 15.
Specification
The Examiner acknowledges amendments to the applicant’s specification. The Examiner withdraws objections to the applicant’s specification due to amendments made to the specification.
Claim Objections
The Examiner acknowledges amendments made to claim 1. The Examiner withdraws the objection to claim 1 due to amendments to the claim.
Claim Rejections
The Examiner acknowledges the cancellation of claims 4 and 15, for these reasons the Examiner withdraws the 112(a) rejections regarding claims 4 and 15.
The Examiner acknowledges and has fully considered the applicant’s arguments regarding 112(b) rejections to claims 2 and 13. The applicant seemingly argues that K is bounded, and a person skilled in the art would recognize K is finite and bounded by being determined by the implementation of the state-transfer function. The Examiner is persuaded by the applicant’s arguments and withdraws the 112(b) rejection to claims 2 and 13 due to the arguments, as well as cancellation of claims 2 and 13.
The Examiner acknowledges that the applicant’s statements that claims 3 and 14 have been amended to correct antecedent basis. However, claims 3 and 14 have been cancelled. The Examiner withdraws the 112(b) rejections regarding claims 3 and 14 due to cancellation of the claims.
The Examiner acknowledges cancellation of claims 4 and 15, and withdraws 112(b) rejections regarding claims 4 and 15 due to cancellation of the claims.
The Examiner acknowledges amendment to claim 5 to correct claim dependency. The Examiner withdraws 112(b) claim rejections to claims 5-10 due to amendment and correction of claim dependency of claim 5, which claims 6-10 are dependent upon.
The Examiner acknowledges amendments to claims 6 and 17 correcting antecedent basis issues of the claims. The Examiner withdraws 112(b) rejections to claims 6 and 17 due to amendments to the claims.
The Examiner acknowledges and has fully considered the applicant’s arguments regarding 112(b) rejections to claims 7 and 18. The applicant asserts that there is no inconsistency between claims 1 and claim 7, seemingly arguing that claim 1 requires a variable seed used in at least one step of at least one cycle of the state-transfer calculation, whereas claim 7 simply specifies that the use of the variable seed not be used in the first step of the first cycle. The Examiner is persuaded by the applicant’s arguments and withdraws the 112(b) rejections to claims 7 and 18 due to being persuaded by the arguments.
The Examiner acknowledges amendments to claims 8 and 19 regarding the 112(b) rejection for further clarification of what is claimed. The Examiner withdraws the 112(b) rejections to claims 8 and 19 due to amendments to the claims.
The Examiner acknowledges amendments to claims 9 and 20 regarding the 112(b) rejections. The Examiner withdraws the 112(b) rejections to claims 9 and 20 due to amendments to the claims.
35 U.S.C. 103 Rejections
The Examiner acknowledges the incorporation of indicated allowable subject matter into the independent claims, 1, 12, and 23. The Examiner withdraws the 103 rejections to the claims due to the amendments to the independent claims which include the indicated allowable subject matter.
35 U.S.C. 101 Rejections
The Examiner acknowledges and has fully considered the applicant’s arguments regarding the 101 rejections.
The applicant seemingly asserts that the amended claims are directed to a specific computer-implemented process applying mathematical relationships in a processor controlled environment to produce practical results, and that the claims do not preempt the mathematical relationship themselves, Remarks page 13 section D paragraph 2. The Examiner respectfully notes that preemption is not a standalone test for determining claim eligibility, and instead are resolved by the Alice framework steps 2A and 2B, see MPEP 2106.04(I) paragraph 4. The Examiner also respectfully notes that applicant seemingly admits that the claims are an abstract idea (mathematical relationships) applied on a computer (computer implemented, in a processor controlled environment).
The applicant further argues that the independent claims use bounded parameters, N and K, stepwise assignment of integer and fractional components to define iterative state transitions, and processor-controlled propagation of state and seed values between cycles, which the applicant seemingly asserts makes the claims directed to a specific computer-implemented process and removed any possible reading that the invention covers a mathematical relationship in the abstract, Remarks page 12 section D paragraph 3. The Examiner respectfully disagrees. The Examiner respectfully points out that the mentioned specific computer-implemented process, is a mathematical algorithm which uses a computer as a tool, and upon which the algorithm is applied, as well as simply storing instructions for a computer to run the mathematical calculations which is considered well understood, routine and conventional activity. See MPEP 2106.05(I)(A)(i), 2106.05(I)(A)(ii) and 2106.05(d)(II)(iv).
The Applicant further argues that the claims as amended are not directed to an abstract idea, Remarks page 13 section D paragraph 4. The Examiner respectfully disagrees, and points to the claim as a mathematical algorithm which uses a computer as a tool upon which the algorithm is applied, as well as simply storing instructions for a computer to run the mathematical calculations which is considered well understood, routine and conventional activity. See MPEP 2106.05(I)(A)(i), 2106.05(I)(A)(ii) and 2106.05(d)(II)(iv).
The applicant further argues that the amended claims are directed to a concrete processor-executed state-management method that performs ordered digital operations to generate pseudo-random sequences. The applicant continues by stating that each claim explicitly requires execution by one or more processors, finite parameters defining bounded state spaces, iteration over discrete steps including an integer portion and fractional portion, and storage and reuse of those values to initialize the next step or cycle. The applicant continues by stating that this is a specific computing architecture, not a mathematical idea performed in the mind, Remarks page 14 paragraphs 1-3. The Examiner respectfully disagrees with the applicant’s arguments. The applicant’s asserts that each claim explicitly requires processors and storage, but storage and reuse of values to initialize the next step or cycle are seemingly unclaimed elements of claim 1. The Examiner respectfully notes that out of the list the applicant provided of what each claim now explicitly requires, the only two would be considered additional elements, processors and storage, with the rest being considered an algorithm of mathematical concepts. Furthermore, the two additional elements listed, processors and storage, are considered a computer as a tool upon which the algorithm is applied, as well as simply storing instructions for a computer to run the mathematical calculations which is considered well understood, routine and conventional activity. See MPEP 2106.05(I)(A)(i), 2106.05(I)(A)(ii) and 2106.05(d)(II)(iv).
The applicant seemingly further argues that the claims improve the way a processor manages random-sequence generation by ensuring bounded memory use, repeatable cycles, and improved sequence uniformity, seemingly arguing that the claims recite a particular implementation how the computer operates not a disembodied formula, Remarks page 14 paragraph 3. The Examiner respectfully disagrees. The Examiner notes that the “repeatable cycles” seemingly refers to cycles of a state transfer function, wherein an example of what a claimed cycle of the state transfer function is comes from the newly amended claim 1, “cycle of state transfer calculation comprises performing (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2”, which points to the cycles as part of a mathematical algorithm which is applied on a generic computer. The Examiner notes that there seemingly isn’t any indication in the applicant’s disclosure of improving a processor random-sequence generation by ensuring bounded memory use, repeatable cycles, and improved sequence uniformity. The Examiner notes that any purported improvements of the applicant’s invention is a direct result of the mathematical concepts, and not technology, which is generically claimed as a generic computer upon which the mathematical concepts are applied.
The applicant seemingly further argues that the amended claims add meaningful limitations that integrate any mathematical operation into a practical application. The applicant continues by reciting that the processors perform ordered calculations constrained by finite integer bounds, divide and assign results into integer and fractional registers, propagate those registers across cycles to control further computation, and thereby generate pseudo-random outputs in real time for subsequent digital processes. The applicant further continues by stating that these operations improve computer performance by reducing computation load, and enabling deterministic reproducibility, Remarks page 14, paragraphs 4-5 and continued on page 15 through paragraph 1. The Examiner respectfully disagrees with the applicant’s arguments. The Examiner notes that the claims nor the applicant’s specification, nor the applicant’s drawings seem to mention or show registers, or processors propagating registers across cycles to control further computation, nor does the applicant’s claims, specification or drawings mention or show real time computation or outputs. Furthermore, the claimed cycles are part of a mathematical algorithm which is merely applied in a generic computer.
The applicant further argues that the claims are technologically rooted and do not preempt an abstract idea, with each amended claim limited to processor execution within a bounded digital state space, defined integer and fractional seed handling, and a finite iterative control sequence. The applicant continues by asserting that because the claims are confined to this specific computing environment, they do not preempt all mathematical uses of the recited equations, and that they are directed to a particular practical application of a state-transfer function in processor-based pseudo-random number generation, Remarks page 15 paragraphs 2-3. The Examiner respectfully disagrees with the applicant’s arguments. The Examiner respectfully notes that preemption is not a standalone test for determining claim eligibility, and instead are resolved by the Alice framework steps 2A and 2B, see MPEP 2106.04(I) paragraph 4.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 5-10, 12, 16-20, and 23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
With regards to claim 1, under the Alice Framework Step 1, claim 1 falls within the four statutory
categories of patentable subject matter identified by 35 U.S.C. 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 1 recites an abstract idea, including mathematical concepts, specifically, mathematical calculations:
A method for generating pseudo-random number, comprising: receiving, an initial state and a seed; performing, at least a cycle of state transfer calculation; and outputting a series of pseudo random numbers; wherein a variable decimal seed is used in at least one step of the at least one cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation, wherein performing at least a cycle of state transfer calculation comprises performing (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2; wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n); a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n); wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle.
Under the Alice Framework Step 2A prong 2, and 2B analysis, claim 1 recites the additional element of “at least one processor”. The “at least one processor” is described in a manner of simply applying it, as a generic tool for operating the mathematical concepts. This additional element merely recite a generic computer system upon which the abstract idea is applied to and thus are not integrated into a practical application, see MPEP 2106.04(d)(I), MPEP 2106.05(f)(2)(i), and 2106.05(I)(A)(ii). Furthermore, this additional element which merely recite a generic computer system performing generic computer functions are considered well-understood, routine, and conventional activities, see MPEP 2106.05(I)(A)(ii), and 2106.05(d)(II). For these reasons this additional element is neither integrated into a practical solution nor amount to significantly more than the abstract idea.
Claim 5 is rejected for at least the reasons set forth with respect to claim 1. Claim 5 merely further limits the mathematical concept set forth in claim 1.
Under the Alice Framework Step 2A prong 1, claim 5 recites an abstract idea, including a mathematical concept. Specifically, claim 5 recites the following mathematical calculations:
wherein performing at least a cycle of state transfer calculation comprises performing M cycles of state transfer calculation, M being an integer equal to or greater than 1.
Claim 5 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 5 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 6 is rejected for at least the reasons set forth with respect to claim 5. Claim 6 merely
further limits the mathematical concept set forth in claim 5.
Under the Alice Framework Step 2A prong 1, claim 6 recites an abstract idea, including a mathematical concept. Specifically, claim 5 recites the following mathematical calculations:
in a m-th cycle, a value of V(m) is obtained in a last step of the m-th cycle, 1 < m <M; an integer part of V(m) is assigned as a m-th state S(m); a decimal part of V(m) is assigned as a m-th variable decimal seed frac (m); wherein, in a (m+1) cycle, S(m) is used as an initial state of the (m+1) cycle, and frac(m) is used as an initial variable decimal seed of the (m+1) cycle; and m is an integer representing a cycle number between 1 and M.
Claim 6 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 6 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 7 is rejected for at least the reasons set forth with respect to claim 5. Claim 7 merely further limits the mathematical concept set forth in claim 5.
Under the Alice Framework Step 2A prong 1, claim 7 recites an abstract idea, including a mathematical concept. Specifically, claim 7 recites the following mathematical calculations:
wherein, in a first step of a first cycle of state transfer calculation, the state transfer calculation is performed without an input of a variable decimal seed.
Claim 7 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 7 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 8 is rejected for at least the reasons set forth with respect to claim 5. Claim 8 merely further limits the mathematical concept set forth in claim 5.
Under the Alice Framework Step 2A prong 1, claim 8 recites an abstract idea, including a mathematical concept. Specifically, claim 8 recites the following mathematical calculations:
further comprising receiving, an input indicating a total number of pseudo random numbers in the series of pseudo random numbers to be outputted.
Claim 8 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 8 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 9 is rejected for at least the reasons set forth with respect to claim 5. Claim 9 merely further limits the mathematical concept set forth in claim 5.
Under the Alice Framework Step 2A prong 1, claim 9 recites an abstract idea, including a mathematical concept. Specifically, claim 9 recites the following mathematical calculations:
wherein each cycle comprises (N-1) number of steps of state transfer function calculation to generate N number of states and N number of random numbers; N is an integer number of states in each cycle M is equal to the total number of pseudo random numbers in the series divided by N: and the total number of pseudo random numbers is an integer multiple of N.
Claim 9 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 9 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 10 is rejected for at least the reasons set forth with respect to claim 9. Claim 10 merely further limits the mathematical concept set forth in claim 9.
Under the Alice Framework Step 2A prong 1, claim 10 recites an abstract idea, including a mathematical concept. Specifically, claim 10 recites the following mathematical calculations:
wherein the series of pseudo random numbers comprises M * N number of bit numbers.
Claim 10 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 10 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
With regards to claim 12, under the Alice Framework Step 1, claim 12 falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 12 recites an abstract idea, including mathematical concepts, specifically, mathematical calculations:
A random number generator, comprising: receive an initial state and a seed; perform at least a cycle of state transfer calculation; and output a series of pseudo random numbers; wherein, a variable decimal seed is used in at least one step of the at least a cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation; wherein, to perform at least a cycle of state transfer calculation, to perform (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2: wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n); a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n): wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle.
Under the Alice Framework Step 2A prong 2, claim 12 recites the additional elements of “memory”, “one or more processors”, and “computer-executable instructions”. The additional elements are described in a manner of simply applying it, as a generic tool for operating the mathematical concepts. This additional element merely recite a generic computer system upon which the abstract idea is applied to and thus are not integrated into a practical application, see MPEP 2106.04(d)(I), MPEP and 2106.05(f)(2)(i). For this reason claim 12 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, these additional elements which merely recite a generic computer system performing generic computer functions are considered well-understood, routine, and conventional activities, see MPEP 2106.05(I)(A)(ii), and 2106.05(d)(II). For the additional element of “memory”, the recited memory is simply for storing instructions for the processor to run the mathematical calculations, and is considered well-understood, routine and conventional activity, see MPEP 2106.05(d)(II)(iv). Furthermore, see How the Computer Works: The CPU and Memory. (2021, August) https://homepage.cs.uri.edu/faculty/wolfe/book/Readings/Reading04.htm?wcmmode=edit . For these reasons, claim 12 does not comprise an inventive concept, not amounting to significantly more than the abstract idea.
Claim 16 is rejected for at least the reasons set forth with respect to claim 12. Claim 16 merely further limits the mathematical concept set forth in claim 12.
Under the Alice Framework Step 2A prong 1, claim 16 recites an abstract idea, including a mathematical concept. Specifically, claim 16 recites the following mathematical calculations:
wherein the memory stores computer-executable instructions for controlling the one or more processors to perform M cycles of state transfer calculation, M being an integer equal to or greater than 1.
Claim 16 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 16 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 17 is rejected for at least the reasons set forth with respect to claim 16. Claim 17 merely further limits the mathematical concept set forth in claim 16.
Under the Alice Framework Step 2A prong 1, claim 17 recites an abstract idea, including a mathematical concept. Specifically, claim 17 recites the following mathematical calculations:
wherein, in a m-th cycle, a value of V(m) is obtained in a last step of the m-th cycle, 1 < m <M; an integer part of V(m) is assigned as a m-th state S(m); a decimal part of V(m) is assigned as a m-th variable decimal seed frac (m); wherein, in a (m+1) cycle, S(m) is used as an initial state of the (m+1) cycle, and frac(m) is used as an initial variable decimal seed of the (m+1) cycle; and m is an integer representing a cycle number between 1 and M.
Claim 17 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 17 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 18 is rejected for at least the reasons set forth with respect to claim 16. Claim 18 merely further limits the mathematical concept set forth in claim 16.
Under the Alice Framework Step 2A prong 1, claim 18 recites an abstract idea, including a mathematical concept. Specifically, claim 18 recites the following mathematical calculations:
wherein, in a first step of a first cycle of state transfer calculation, the state transfer calculation is performed without an input of a variable decimal seed.
Claim 18 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 18 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 19 is rejected for at least the reasons set forth with respect to claim 16. Claim 19 merely further limits the mathematical concept set forth in claim 16.
Under the Alice Framework Step 2A prong 1, claim 19 recites an abstract idea, including a mathematical concept. Specifically, claim 19 recites the following mathematical calculations:
wherein the for controlling to receive an input indicating a total number of pseudo random numbers in the series of pseudo random numbers to be outputted.
Claim 19 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 19 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
Claim 20 is rejected for at least the reasons set forth with respect to claim 16. Claim 20 merely further limits the mathematical concept set forth in claim 16.
Under the Alice Framework Step 2A prong 1, claim 20 recites an abstract idea, including a mathematical concept. Specifically, claim 20 recites the following mathematical calculations:
wherein each cycle comprises (N-1) number of steps of state transfer function calculation to generate N number of states and N number of random numbers; N is an integer number of states in each cycle M is equal to the total number of pseudo random numbers in the series divided by N: and the total number of pseudo random numbers is an integer multiple of N.
Claim 20 recites no additional elements in the claim limitations which require a Step 2A prong 2 or Step 2B analysis. For these reasons, claim 20 is neither integrated into a practical application nor amounting to significantly more than the abstract idea.
With regards to claim 23, under the Alice Framework Step 1, claim 23 falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 23 recites an abstract idea, including mathematical concepts, specifically, mathematical calculations:
being executable to perform: receiving, an initial state and a seed; performing, at least a cycle of state transfer calculation; and outputting a series of pseudo random numbers; wherein a variable decimal seed is used in at least one step of the at least a cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation; wherein performing at least a cycle of state transfer calculation comprises performing (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2; wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n);a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n); wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle
Under the Alice Framework Step 2A prong 2 analysis, claim 23 recites the additional elements of “computer-program product”, “a non-transitory tangible computer-readable medium having computer-readable instructions thereon”, and “processor”. The “processor” and “a non-transitory tangible computer-readable medium having computer-readable instructions thereon” are described in a manner of simply applying it, as generic tools for operating the mathematical concepts, see MPEP 2106.04(d)(I), MPEP and 2106.05(f)(2)(i). For this reason claim 23 is not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the additional element of “processor” is described in a manner of simply applying it, as a generic tool for operating the mathematical concepts, see MPEP 2106.05(I)(A)(ii), and 2106.05(d)(II). For the additional element of “a non-transitory tangible computer-readable medium having computer- readable instructions thereon”, the recited “a non-transitory tangible computer-readable medium having computer- readable instructions thereon” is simply for storing instructions for the processor to run the mathematical calculations, and is considered well-understood, routine and conventional activity, MPEP 2106.05(d)(II)(iv). See Bitlaw. Section 101 Examples: 3-Halftoning--Digital Image Processing (BitLaw). (2015). https://www.bitlaw.com/source/pto/examples/3.html . For these reasons, claim 23 does not comprise an inventive concept, not amounting to significantly more than the abstract idea.
Allowable Subject Matter
Claims 1, 5-10, 12, 16-20, and 23 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 101 set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the applicant claims a method for generating pseudo random numbers, wherein the method of claim 1 comprises:
receiving, by at least one processor, an initial state and a seed; performing, by the at least one processor, at least a cycle of state transfer calculation; and outputting a series of pseudo random numbers; wherein a variable decimal seed is used in at least one step of the at least one cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation, wherein performing at least a cycle of state transfer calculation comprises performing (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2;wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n); a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n); wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Regarding claim 12 the applicant claims a random number generator, wherein the random
number generator of claim 12 comprises:
a memory; one or more processors; wherein the memory and the one or more processors are connected with each other; and the memory stores computer-executable instructions for controlling the one or more processors to: receive an initial state and a seed; perform at least a cycle of state transfer calculation; and output a series of pseudo random numbers; wherein, a variable decimal seed is used in at least one step of the at least a cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation; wherein, to perform at least a cycle of state transfer calculation, the memory stores computer-executable instructions for controlling the one or more processors to perform (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2:wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n); a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n): wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Regarding claim 23 the applicant claims a computer-product comprising a non-transitory tangible computer-readable medium having computer-readable instructions thereon, wherein the computer-readable instructions are executed by the processor for the processor to perform:
receiving, by at least one processor, an initial state and a seed; performing, by the at least one processor, at least a cycle of state transfer calculation; and outputting a series of pseudo random numbers; wherein a variable decimal seed is used in at least one step of the at least a cycle of state transfer calculation; and the variable decimal seed is calculated in a previous step of the at least a cycle of state transfer calculation; wherein performing at least a cycle of state transfer calculation comprises performing (N-1) number of steps of state transfer calculation in a respective cycle to obtain N number of states and N number of bit numbers corresponding to the N number of states, wherein N < K, K is a maximum possible number of states according to a state transfer function for performing the state transfer calculation, N being an integer equal to or greater than 2, K being an integer equal to or greater than 2;wherein, at the end of a (n-1)-th step of the respective cycle, a value U(n) is calculated, 1< n < (N-1); an integer part of U(n) is assigned as a n-th state S(n);a decimal part of U(n) is assigned as a n-th variable decimal seed frac(n); wherein, in a n-th step of the respective cycle, S(n) is used as an initial state of the n-th step, and frac(n) is used as an initial variable decimal seed of the n-th step, for calculating a value U(n); and n is an integer representing a step number in the respective cycle.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Rose et al. (U.S. Patent Application Publication 20080263117 A1), hereinafter, “Rose”, teaches the claimed invention of a random number generator that generates random numbers in at least one cycle of states outputting pseudorandom numbers. Rose in view of Wilton (U.S. Patent Application Publication 20140172933 A1), hereinafter, “Wilton”, teaches that a decimal seed may be used in determining the next state for outputting random numbers. However, Rose in view of Wilton does not explicitly disclose the italicized claim limitations in combination with the remaining claim limitations including intervening claims as referenced above.
Rose et al. (U.S. Patent Application Publication 20070230694 A1), hereinafter, “Rose2”, teaches (Figure 6) a cycle of steps of transitions between states of a pseudo random number generator, with a new state generated based on the current state and the seed value with the seed seemingly equal to a remainder due to a modulo function (Figure 5, items 501; [0056], [0058]). However, Rose2 does not explicitly disclose the italicized claim limitations in combination with the remaining claim limitations including intervening claims as referenced above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182