DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments (Applicant’s Remarks pages 8-11) assert that the new limitations “an orthographic projection of the electrostatic protection layer on the base substrate is located in an orthographic projection of the second electrode on the base substrate, and the orthographic projection of the second electrode on the base substrate is located in the orthographic projection of the electrostatic protection layer on the base substrate, to make that the electrostatic protection layer and the second electrode are formed by a same mask”, emphasizing “to make that the electrostatic protection layer and the second electrode are formed by a same mask” are not taught by the prior art of record. However, the Examiner respectfully disagrees:
US 20180107856 A1 (Troccoli et al), which discloses an electrostatic protection layer, includes overlapping orthographic projections consistent with the broadest reasonable interpretation of the claim. Regarding the “formed by a same mask” limitation, this is a product-by-process limitation which does not render the final device structure of the claimed device distinguishable over the device of Troccoli as there is no necessary structural difference as a result (see also MPEP 2113 I).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20170236857 A1 (Bu) in view of US 20180107856 A1 (Troccoli et al hereinafter Troccoli).
Regarding claim 1, Bu discloses a photoelectric sensor (the photoelectric sensor shown in FIG. 1D, ¶ [0055]), comprising: a base substrate (FIG. 1D, base substrate 1 ¶ [0051]); a driving circuit (FIG. 1D, a circuit including the pictured TFT formed of gate 2, gate insulating layer 3, semiconductor layer 4, and source/drain metal layer 6, located on base substrate 1 ¶ [0049-0051]), located on the base substrate; a photoelectric converter (FIG. 1D, the PIN type photodiode formed of N-type 71, I-type 72, P-type 73, and metal layer 6 located on base substrate 1 ¶ [0051]), located on the base substrate, wherein the photoelectric converter comprises a first electrode (FIG. 1D, the right portion of metal layer 6 ¶ [0051, 0055]), a photoelectric conversion layer (FIG. 1D, the PIN type photodiode formed of N-type 71, I-type 72, and P-type 73 ¶ [0051]) and a second electrode (FIG. 1D, bias electrode layer 10 ¶ [0051]), and the photoelectric conversion layer is located at a side of the first electrode away from the base substrate (FIG. 1D, metal layer 6 is between base substrate 1 and N-type 71 and the other photodiode layers),
the driving circuit comprises a reset sub-circuit (FIG. 1D, the pictured TFT may function as a reset sub-circuit ¶ [0049-0051]), the reset sub-circuit comprises a first source electrode and a first drain electrode (FIG. 1D, source/drain metal layer 6 includes the source and drain electrodes of the TFT ¶ [0051]), the first electrode and the first drain electrode are integrated into a same electrode (the drain of the TFT and the photodiode’s lower electrode are integrally formed ¶ [0055]) and arranged in a same layer as the first source electrode (FIG. 1D, they are all formed in source/drain metal layer 6 ¶ [0051, 0055]); the reset sub-circuit comprises a reset transistor (FIG. 1D, the pictured TFT may be a reset transistor ¶ [0049-0051]), and the reset transistor comprises a first active layer (FIG. 1D, semiconductor layer 4 ¶ [0051]).
Bu does not disclose an electrostatic protection layer, an orthographic projection of the electrostatic protection layer on the base substrate is located in an orthographic projection of the second electrode on the base substrate, and the orthographic projection of the second electrode on the base substrate is located in the orthographic projection of the electrostatic protection layer on the base substrate, to make that the electrostatic protection layer and the second electrode are formed by a same mask.
However, Troccoli discloses a photosensor device (a sensor device including a cross-sectional structure as illustrated in FIG. 9; FIG. 2A also displays an electron microscope plan view of a PIN photodiode pixel ¶ [0047-0049]) comprising an electrostatic protection layer (FIG. 9, ESD protection layer 80 ¶ [0054]), an orthographic projection of the electrostatic protection layer (FIG. 9, ESD protection layer 80 includes a portion that overlaps the second metal 54) on the base substrate (FIG. 9, substrate 62 ¶ [0048]) is located in an orthographic projection of the second electrode (FIG. 9, second metal 54, which connects to the PIN diode of the photosensor, has a partial overlap in orthographic projection with ESD protection layer 80 ¶ [0047]) on the base substrate, and the orthographic projection of the second electrode on the base substrate is located in the orthographic projection of the electrostatic protection layer on the base substrate (FIG. 9, second metal 54 is located in a region that is overlapped by ESD protection layer 80). Troccoli also teaches that the electrostatic protection layer protects metal layers from damage from electrostatic discharge, and may also be formed as a hard layer to provide mechanical protection (¶ [0054]).
Bu and Troccoli both pertain to the field of photosensor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Bu in view of Troccoli to further include an electrostatic protection layer, an orthographic projection of the electrostatic protection layer on the base substrate is located in an orthographic projection of the second electrode on the base substrate, and the orthographic projection of the second electrode on the base substrate is located in the orthographic projection of the electrostatic protection layer on the base substrate, to make that the electrostatic protection layer and the second electrode are formed by a same mask, in order to protect the metal layers from damage from electrostatic discharge, and be formed as a hard layer to provide mechanical protection, as taught by Troccoli.
The language, term, or phrase "to make that the electrostatic protection layer and the second electrode are formed by a same mask", is directed towards the process of making an electrostatic protection layer and a second electrode. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "to make that the electrostatic protection layer and the second electrode are formed by a same mask" only requires a second electrode and electrostatic protection layer which overlap, which does not distinguish the invention from the structure of Troccoli FIG. 9, who teaches the structure as claimed.
Regarding claim 2, Bu in view of Troccoli discloses the limitations of claim 1 as detailed above and Bu further discloses that an orthographic projection of the first electrode of the photoelectric converter on the base substrate is spaced apart from an orthographic projection of the first source electrode on the base substrate (FIG. 1D, the source electrode on the left of the TFT is spaced apart from the right drain/lower electrode of the photodiode ¶ [0051, 0055]).
Regarding claim 4, Bu in view of Troccoli discloses the limitations of claim 1 as detailed above and Bu further discloses that an orthographic projection of the photoelectric conversion layer on the base substrate falls within a range of an orthographic projection of the first electrode on the base substrate (FIG. 1D, the orthographic projection of the PIN layers of the photodiode is entirely encompassed/overlapped by the orthographic projection of the first electrode portion of source/drain metal layer 6).
Regarding claim 17, Bu in view of Troccoli discloses the limitations of claim 1 as detailed above and Bu further discloses that the photoelectric conversion layer comprises an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer which are stacked in order (FIG. 1D, the PIN type photodiode is formed of N-type 71, I-type 72, and P-type 73 that are stacked in that order).
Regarding claim 18, Bu discloses an image sensor (an image sensor of an X-ray detection device, comprising a plurality of photoelectric sensors of the “first embodiment” which includes the variation of FIG. 1D ¶ [0063]; a plurality being present is evident at least because the term “array substrate” implies the presence of more than one photodiode on the substrate), wherein each of the photoelectric sensors is the photoelectric sensor according to claim 1 (the photoelectric conversion array substrate of the “first embodiment” FIG. 1D variation is used in the X-ray detection device ¶ [0055, 0063], and comprises all of the limitations of claim 1 based on Bu in view of Troccoli as detailed above).
Regarding claim 19, Bu in view of Troccoli discloses the limitations of claim 18 as detailed above and Bu further discloses that the plurality of photoelectric sensors are arranged in an array (the photoelectric converters are arranged as an array substrate ¶ [0027, 0063]).
Regarding claim 20, Bu in view of Troccoli discloses an electronic device, comprising the image sensor according to claim 18 (an X-ray detection device having the image sensor comprising the photoelectric conversion array substrate of the “first embodiment” FIG. 1D variation ¶ [0055, 0063], in view of Troccoli).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication Bu in view of Troccoli as applied to claim 1 above, and further in view of US patent publication US 20220238578 A1 (Katsuta).
Regarding claim 5, Bu in view of Troccoli discloses the limitations of claim 1 as detailed above, but does not further disclose that the driving circuit further comprises a signal reading sub-circuit and a signal amplifying sub-circuit, an orthographic projection of the signal reading sub-circuit on the base substrate, an orthographic projection of the signal amplifying sub-circuit on the base substrate and an orthographic projection of the reset sub-circuit on the base substrate are sequentially arranged in a first direction, and an orthographic projection of the driving circuit on the base substrate and an orthographic projection of the photoelectric converter on the base substrate are sequentially arranged in a second direction.
However, Katsuta discloses a photoelectric sensor (FIGS. 5-9, one of detection elements 3 ¶ [0028-0029]) according to claim 1, wherein the driving circuit (FIG. 5 shows a driving circuit for each detection element 3 ¶ [0041-0048]) comprises a reset sub-circuit (FIGS. 5-8, a sub-portion of the circuit including reset transistor Mrst ¶ [0041]), a signal reading sub-circuit (FIGS. 5-8, a sub-portion of the circuit including read transistor Mrd ¶ [0041]) and a signal amplifying sub-circuit (FIGS. 5-8, a sub-portion of the circuit including source follower transistor Msf, which may amplify a signal ¶ [0041]), an orthographic projection of the signal reading sub-circuit on the base substrate (FIG. 8, the projection of read transistor Mrd into the “Dz” direction normal to substrate 21 ¶ [0031]), an orthographic projection of the signal amplifying sub-circuit on the base substrate (FIG. 8, the projection of source follower transistor Msf into the “Dz” direction normal to substrate 21 ¶ [0031]) and an orthographic projection of the reset sub-circuit on the base substrate (FIG. 8, the projection of reset transistor Mrst into the “Dz” direction normal to substrate 21 ¶ [0031]) are sequentially arranged in a first direction (FIG. 8, transistors Mrst, Mrd, and Msf are sequentially arranged along the “Dx” direction ¶ [0031]), and an orthographic projection of the driving circuit on the base substrate (FIG. 8, projections of transistors Mrst, Mrd, and Msf along the “Dz” direction ¶ [0031]) and an orthographic projection of the photoelectric converter on the base substrate (FIG. 8, photoconversion element 30 ¶ [0029]) are sequentially arranged in a second direction (FIG. 8, transistors Mrst, Mrd, and Msf and photoconversion element 30 are arranged along the “Dy” direction ¶ [0029]).
Bu, Troccoli, and Katsuta both pertain to the field of photoelectric sensors, placing them in the same field of endeavor as the claimed invention, and a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Bu in view of Troccoli further in view of Katsuta such that the driving circuit further comprises a signal reading sub-circuit and a signal amplifying sub-circuit, an orthographic projection of the signal reading sub-circuit on the base substrate, an orthographic projection of the signal amplifying sub-circuit on the base substrate and an orthographic projection of the reset sub-circuit on the base substrate are sequentially arranged in a first direction, and an orthographic projection of the driving circuit on the base substrate and an orthographic projection of the photoelectric converter on the base substrate are sequentially arranged in a second direction, because a person of ordinary skill in the art would have found that the sub-circuit features of the device of Katsuta in combination with the device of Bu in view of Troccoli would perform the same functions as they did separately, could have combined the elements as claimed by known methods, and that a person of ordinary skill in the art would have recognized that the results of the combination were predictable (MPEP 2143 I (A)), since such configurations of driving circuits for photodiodes were known in the art.
Regarding claim 6, Bu in view of Troccoli and Katsuta discloses the limitations of claim 5 as detailed above, and they further disclose that the signal reading sub-circuit comprises a signal reading transistor (Katsuta FIGS. 5-8, read transistor Mrd ¶ [0041]), the signal amplifying sub-circuit comprises a signal amplifying transistor (Katsuta FIGS. 5-8, source follower transistor Msf, which may amplify a signal ¶ [0041]), the signal reading transistor comprises a second active layer (Katsuta FIG. 8, semiconductor layer 71 of read transistor Mrd ¶ [0081]), the signal amplifying transistor comprises a third active layer (Katsuta FIG. 8, semiconductor layer 65 of source follower transistor Msf ¶ [0080]), an orthographic projection of the second active layer on the base substrate is spaced apart from an orthographic projection of the photoelectric converter on the base substrate (Katsuta FIG. 8, projections of semiconductor layer 71 and photoconversion element 30 are spaced apart from each other along the “Dz” direction ¶ [0031]), and an orthographic projection of the third active layer on the base substrate is spaced apart from the orthographic projection of the photoelectric converter on the base substrate (Katsuta FIG. 8, projections of semiconductor layer 65 and photoconversion element 30 are spaced apart from each other along the “Dz” direction ¶ [0031]).
Regarding claim 7, Bu in view of Troccoli and Katsuta discloses the limitations of claim 5 as detailed above, and they further disclose that the photoelectric conversion layer comprises a bisector extending in the first direction (Katsuta FIG. 8, photoconversion element 30 may have a bisector drawn along the first Dx direction ¶ [0031]), and the driving circuit is located at a side of the bisector in the second direction (FIG. 8, driving circuit including transistors Mrst, Mrd, and Msf is located at a side of the bisector along the second Dy direction ¶ [0031]).
Regarding claim 8, Bu in view of Troccoli and Katsuta discloses the limitations of claim 5 as detailed above, and they further disclose that the reset sub-circuit further comprises a first control electrode (Bu FIG. 1D, gate metal layer 2 ¶ [0051]), the signal reading sub-circuit comprises a second control electrode (Katsuta FIGS. 5-8, Mrd includes a gate electrode 74 ¶ [0081]), a second source electrode (Katsuta FIGS. 5-8, Mrd includes an unlabeled source electrode toward node N2, evident from the circuit diagram of FIG. 5 ¶ [0046-0047]) and a second drain electrode (Katsuta FIGS. 5-8, Mrd includes drain electrode 72 ¶ [0081]), and the signal amplifying sub-circuit comprises a third control electrode (Katsuta FIGS. 5-8, Msf includes a gate electrode 68 ¶ [0080]), a third source electrode (Katsuta FIGS. 5-8, Msf includes a source electrode 67, which connects to Vsf/SLsf) and a third drain electrode (Katsuta FIG. 5, Msf includes an unlabeled drain electrode toward node N2 evident from the circuit diagram), the third drain electrode is connected with the second source electrode (Katsuta FIGS. 5 and 8, the unlabeled drain of Msf and unlabeled source of Mrd meet at node 2 ¶ [0046-0047]), and the first drain electrode is connected with the third control electrode (Katsuta FIG. 5, the circuit diagram shows that the gate/control electrode of Msf is coupled to the drain of the reset transistor which connects to the photoelectric converter at a node N1 in view of the combination with Bu ¶ [0044-0046]).
Claim 9 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bu in view of Troccoli and Katsuta as applied to claim 8 above, and further in view of US patent publication US 20180040657 A1 (Lee et al hereinafter Lee).
Regarding claim 9, Bu in view of Troccoli and Katsuta discloses the limitations of claim 8 as detailed above, and Katsuta further discloses that a power line (Katsuta FIGS. 5-8, power supply signal line SLsf ¶ [0058]), extending in the second direction (FIGS. 5-8, power line SLsf extends along the second Dy direction) and configured to be connected with the third source electrode (FIGS. 5 and 8, power line SLsf carrying voltage Vsf connects to the third source 67 of Msf); a data reading control line (FIGS. 5 and 8, read control scan line GLrd ¶ [0034]), extending in the first direction (FIG. 8, GLrd extends along first Dx direction ¶ [0042]) and configured to be connected with the second control electrode (FIGS. 5 and 8, GLrd connects to the gate/control electrode of reading transistor Mrd ¶ [0042]); a reset control line (FIGS. 5 and 8, reset control scan lines GLrst ¶ [0034]), extending in the first direction (FIG. 8, GLrst extends along first Dx direction ¶ [0042]) and configured to be connected with the first control electrode (FIGS. 5 and 8, GLrst connects to gate/control electrode of reset transistor Mrst ¶ [0042]); and a data signal line (FIGS. 5 and 8, output signal line SL ¶ [0035]), extending in the second direction (FIG. 8, signal line SL extends along the second Dy direction ¶ [0042]) and configured to be connected with the second drain electrode (FIGS. 5 and 8, second drain electrode 72 is connected to signal line SL ¶ [0081]).
Katsuta does not further disclose that the power line is also configured to be connected with the first source electrode.
However, Lee discloses multiple examples of driving circuits for use in image sensors (FIGS. 4A-4B, circuits 120A and 120B ¶ [0047-0049]), wherein in one example, a power line is configured to be connected with a third transistor S/D electrode (FIG. 4B, power line carrying power source voltage VDD connects to the driving transistor DX ¶ [0042]) and a second power line is configured to be connected with a first transistor S/D electrode (FIG. 4B, power line carrying read voltage VRD connects to the reset transistor RX ¶ [0049]), and in another example, a power line is configured to be connected with both a third source electrode and a first source electrode (FIG. 4A, power line carrying VDD connects to both driving transistor DX and reset transistor RX ¶ [0047]). The embodiment of the driving circuit of Lee FIG. 4B matches the circuit of Katsuta FIG. 5, and the embodiment of the driving circuit of Lee FIG. 4A is both analogous art and in view of Katsuta teaches the limitation that the power line is also configured to be connected with the first source electrode.
Bu, Troccoli, Katsuta, and Lee all pertain to the field of photoelectric sensors. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Bu in view of Troccoli and Katsuta further in view of Lee, such that the power line is also configured to be connected with the first source electrode, because circuit configurations having the first and third source electrodes with either a common power line or two distinct power lines have been demonstrated to be interchangeable design alternatives by the prior art.
Regarding claim 12, Bu in view of Troccoli, Katsuta, and Lee disclose the limitations of claim 9 as detailed above, and Bu further discloses that the photoelectric converter further comprises: a conductive protection layer (Bu FIG. 1D, transparent electrode layer 8 ¶ [0051]), located at a side of the photoelectric conversion layer away from the first electrode (FIG. 1D, transparent electrode layer 8 is on side of photoelectric conversion layers 71/72/73 away from first electrode layer 6); an insulating layer (annotated FIG. 1D pictured below, “insulating layer portion” of first passivation layer 9 ¶ [0051]), located at a side of the conductive protection layer away from the base substrate (FIG. 1D, a portion of passivation layer 9 is located above conductive layer 8); a first passivation layer (annotated FIG. 1D, “first passivation layer portion” of first passivation layer 9 ¶ [0051]), located at a side of the insulating layer away from the conductive protection layer (annotated FIG. 1D, “first passivation layer portion” is at a side of “insulating layer portion” away from electrode layer 8); wherein the second electrode (FIG. 1D, bias electrode layer 10 ¶ [0051]) is located at a side of the first passivation layer away from the base substrate (annotated FIG. 1D, electrode layer 10 is at a side of “first passivation layer portion” away from substrate 1), the photoelectric sensor further comprises a via hole located in the insulating layer and the first passivation layer (FIG. 1D, a via hole is present in both “insulating” and “first passivation” portions of passivation layer 9), and the second electrode is connected with the conductive protection layer through the via hole (FIG. 1D, electrode layer 10 connects to electrode layer 8 though the via hole in passivation layer 9).
Regarding claim 13, Bu in view of Katsuta, Troccoli, and Lee disclose the limitations of claim 12 as detailed above. While Bu does not provide particular detail on the shape of the second electrode from a top-down/plan view, Katsuta further discloses that a second electrode (Katsuta FIGS. 8-9, upper electrode 34 including wiring 34a ¶ [0077]) comprises a first hollow portion (FIG. 8, a region above output signal line SL where no upper electrode 34 is disposed is understood to constitute a first hollow portion), wherein an orthographic projection of the first hollow portion on the base substrate at least partially overlaps with an orthographic projection of the data signal line on the base substrate (FIG. 8, the region considered a first hollow portion overlaps the signal line SL); and a second hollow portion (FIG. 8, a region above read control scan line GLrd where no upper electrode 34 is disposed is understood to constitute a second hollow portion), wherein an orthographic projection of the second hollow portion on the base substrate at least partially overlaps with an orthographic projection of the data reading control line on the base substrate (FIG. 8, the region considered a second hollow portion overlaps the read control scan line GLrd).
In view of the combination of Bu in view of Troccoli, Katsuta, and Lee, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to include the present claim’s features in the device of Bu in view of Troccoli, Katsuta, Lu, and Lee, in order to configure the second electrode in a manner conventionally taught by the prior art.
Regarding claim 14, Bu in view of Troccoli, Katsuta, and Lee disclose the limitations of claim 13 as detailed above, but they do not explicitly teach that a size range of the first hollow portion in the first direction is 8 to 10 microns, and a size range of the first hollow portion in the second direction is 40 to 46 microns, a size range of the second hollow portion in the first direction is 50 to 58 microns, and a size range of the second hollow portion in the second direction is 8 to 10 microns.
However, since the first and second hollow portions are not required to constitute every hollow portion in the photoelectric sensor, a determination of the size of each of the first and second hollow portions includes flexibility since any sub-portion not covered by the second electrode would be eligible to be considered included in one of the first or second hollow portions. Further, a person of ordinary skill in the art would recognize that the area of each photosensor unit is a result-effective variable influencing the resolution of the image sensor device while maintaining effective electrical properties (e.g. avoiding parasitic capacitance or manufacturing defects due to practical limitations in size-reduction methods) as the photosensor unit area is scaled down. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the size of the photosensor units, and correspondingly the size ranges of the first hollow portion and the second hollow portion, in order to optimize the resolution and electrical properties of the device.
Further, in view of the aforementioned broadness with which the first and second hollow portions may be defined, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a size range of the first hollow portion in the first direction is 8 to 10 microns, and a size range of the first hollow portion in the second direction is 40 to 46 microns, a size range of the second hollow portion in the first direction is 50 to 58 microns, and a size range of the second hollow portion in the second direction is 8 to 10 microns while modifying the dimensions of the device.
Furthermore, the applicant has not presented persuasive evidence that the claimed size ranges are for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 15, Bu in view of Troccoli, Katsuta, and Lee teaches the limitations of claim 12 as detailed above, and Bu further discloses a second passivation layer (Bu FIG. 1D, second passivation layer 11 ¶ [0051]), located at a side of the second electrode away from the base substrate (FIG. 1D, layer 11 is located at a side of bias electrode 10 away from base substrate 1); wherein the electrostatic protection layer is located at a side of the second passivation layer away from the second electrode (based on the combination of Bu and Troccoli described in claim 1, the second insulator 66 of Troccoli FIG. 9 is at an analogous position to the second passivation layer 11 of Bu FIG. 1D, and the ESD protection layer 80 of Troccoli FIG. 9 is located at a side of second insulator 66 away from second electrode 54 of Troccoli).
Regarding claim 16, Bu in view of Troccoli, Katsuta, and Lee disclose the limitations of claim 12 as detailed above, and Bu further discloses that a material of the conductive protection layer is a transparent conductive oxide (FIG. 1D transparent electrode layer 8 is formed of ITO or IGZO ¶ [0085]), and a material of the second electrode is a transparent conductive oxide (FIG. 1D second bias electrode is formed of transparent conductive oxides such as ITO or IZO ¶ [0087]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Bu in view of Troccoli, Katsuta, and Lee as applied to claim 9 above, and further in view of US patent publication US 20210066364 A1 (Lu).
Regarding claim 10, Bu in view of Troccoli, Katsuta, and Lee disclose the limitations of claim 9 as detailed above and Katsuta further discloses that the photoelectric conversion layer comprises a bisector extending in the first direction (Katsuta FIG. 8, a bisector can be drawn on a projection of photoconversion element 30 along the first Dx direction ¶ [0031]), and the reset control line is located at a side of the bisector close to the data reading control line (FIG. 8, when the bisector is drawn, the reset control line GLrst is on the same side of the bisector as the read control scan line GLrd; being on the same side of the bisector is understood as being “close to” the reading control line). They did not further disclose that an orthographic projection of the reset control line on the base substrate partially overlaps with an orthographic projection of the photoelectric conversion layer on the base substrate.
However, Lu discloses a photoelectric sensor (the sensor of FIGS. 4-5 ¶ [0015-0016]) wherein an orthographic projection of the reset control line on the base substrate (FIGS. 4-5, a projection of reset control line reset on base substrate 1 ¶ [0036-0037]) partially overlaps with an orthographic projection of the photoelectric conversion layer on the base substrate (FIGS. 4-5, a projection of photodiode D1 overlaps a projection of T10, which is adjacent to and formed in the same layer as a portion of reset line reset ¶ [0036, 0060]); such a configuration could be employed to make efficient use of space by having those features overlap along the direction normal to the upper surface of the substrate.
Bu, Troccoli, Katsuta, Lee, and Lu all pertain to the field of photoelectric sensors. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Bu in view of Troccoli, Lu, Katsuta, and Lee further in view of Lu such that an orthographic projection of the reset control line on the base substrate partially overlaps with an orthographic projection of the photoelectric conversion layer on the base substrate, since such a configuration has been demonstrated as a viable design alternative by the prior art, which could be employed to make efficient use of space by having those features overlap along the direction normal to the upper surface of the substrate.
Regarding claim 11, Bu in view of Troccoli, Katsuta, Lee, and Lu discloses the limitations of claim 10 as detailed above, and Katsuta further discloses a reset connection block (Katsuta FIG. 8, reset control line GLrst includes a pair of unmarked stubs that protrude at the reset transistors Mrst), extending along the second direction (FIG. 8, the stubs on GLrst at Mrst extend along the second Dy direction ¶ [0031]) and located between the power line and the photoelectric conversion layer (FIG. 8, the stubs on GLrst are between an uppermost section of power line SLsf and the photoelectric conversion layer 30 along a diagonal direction), wherein the reset connection block is respectively connected with the reset control line and the first control electrode (FIGS. 5 and 8, the stubs on GLrst connect to the main stem of GLrst and the gate/control electrode of the reset transistor Mrst).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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