DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed June 30th, 2022. Claims 1-4 and 6-8 are pending, of which claims 1-4 and 6-8 are currently rejected. Claim 5 has been cancelled by Applicant.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/30/2022 and 10/05/2023 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 2 and 7 are objected to:
Claim 2 line 4 “a inverse function” should be “an inverse function”
Claim 7 should read “A non-transitory computer recording medium on which a program, for causing a computer to operate as the secure computation apparatus according to claim 6, is stored.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, 2nd paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “the secure computation apparatus” on line 1. It is unclear which of the secure computation apparatuses Claim 6 refers to as claim 1 (upon which claim 6 is dependent) recites a plurality of secure computation apparatuses on line 4. For examination purposes, Examiner construes “the secure computation apparatus” of Claim 6 to be referring to each of the plurality of secure computation apparatuses of claim 1 line 4. Appropriate correction is required.
Claim 7 depends upon claim 6 and is therefore rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, 2nd paragraph, as being indefinite.
Claim 7 recites “the secure computation apparatus” on line 1. It is unclear which of the secure computation apparatuses Claim 7 refers to as claim 1 (upon which claim 7 is dependent through claim 6) recites a plurality of secure computation apparatuses on line 4. For examination purposes, Examiner construes “the secure computation apparatus” of Claim 7 to be referring to each of the plurality of secure computation apparatuses of claim 1 line 4. Appropriate correction is required.
Claim 8 recites “the secure computation apparatus” on line 1. It is unclear which of the secure computation apparatuses Claim 8 refers to as claim 3 (upon which claim 8 is dependent) recites a plurality of secure computation apparatuses on line 4. For examination purposes, Examiner construes “the secure computation apparatus” of Claim 8 to be referring to each of the plurality of secure computation apparatuses of claim 3 line 4. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 6-8 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 6 only recites the secure computation apparatus used in the secure inverse computation system of claim 1, without further limiting the secure computation apparatus. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 8 only recites the secure computation apparatus used in the secure inverse computation system of claim 3, without further limiting the secure computation apparatus. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites secure computation for computing an inverse value using bit decomposition, logical sum, logical negation and a logical product.
Below are the limitations of claim 1 that recite an abstract idea under mathematical concepts:
calculating a share value of [1/a] of the inverse of the value a
wherein λ is a decimal point position of the value a, and
generate a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generate a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generate a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generate a share value [c] of c obtained by bit-connecting the third sequence of share values {y0}, … {yλ-1} in reverse order;
calculate a share value [b] obtained by multiplying the share value [a] by the share value [c];
use the share value [b] to obtain a share value [w] obtained by calculating [1/b]; and
calculate the share value [1/a] obtained by multiplying the share value [w] by the share value [c].
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A secure inverse computation system
for receiving a share value [a] of a value a as an input,
a plurality of secure computation apparatuses,
processing circuitry
a normalization multiplier
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There is an insignificant extra-solution activity that must be made of note here:
for receiving a share value [a] of a value a as an input.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “for receiving a share value [a] of a value a as an input”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 1 is not eligible.
Regarding claim 2, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 2 that recite an abstract idea under mathematical concepts:
wherein a, b, c, d, f, g, H, i, j, k, l, m, o, p, q, α, β, γ, δ, and ζ are parameters for approximating a inverse function with an eighth degree polynomial, and [x]:=[b] is assumed, and
calculate [y’]:=[x(δ x + a - i) - j]
calculate [y]:=[y’ + (ix + j)];
calculate [z’]:= [y(ζ y + b – k) + (c – l)x – m];
calculate [z]:=[z’ + (ky+lx+m)];
calculate [w’/ γ]:= [z(αz + d -n/ γ) + (βx + f – o/ γ)y + (g-p)x + (H-q)/ γ];
calculate [w’]:=[w’/ γ] * γ; and
calculate [w]:= [w’ + (nz + op + px + q)].
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, and step 2B there are no further additional elements beyond those recited in claim 1.
Claim 2 is not eligible.
Regarding claim 3, at Step 1, the claim is directed to a statutory category of invention (machine).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites secure computation for normalizing a value of a bit decomposition, logical sum, logical negation and a logical product.
Below are the limitations of claim 3 that recite an abstract idea under mathematical concepts:
normalizing a share value of [a] of the value a
wherein λ is a decimal point position of the value a, and
generate a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generate a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generate a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generate a share value [c] of c obtained by bit-connecting the third-sequence of share values {y0}, …, {yλ-1} in reverse order; and
calculate a share value [b] obtained by multiplying the share value [a] by the share value [c].
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A secure inverse normalization system
a plurality of secure computation apparatuses,
processing circuitry
a normalization multiplier
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 3 does not amount to significantly more than the abstract idea.
Claim 3 is not eligible.
Regarding claim 4, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites secure computation for computing an inverse value using bit decomposition, logical sum, logical negation and a logical product.
Below are the limitations of claim 4 that recite an abstract idea under mathematical concepts:
calculating a share value of [1/a] of the inverse of the value a
generating a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generating a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generating a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generating a share value [c] of c obtained by bit-connecting the third sequence of share values {y0}, … {yλ-1} in reverse order;
calculating a share value [b] obtained by multiplying the share value [a] by the share value [c];
using the share value [b] to obtain a share value [w] obtained by calculating [1/b]; and
calculating the share value [1/a] obtained by multiplying the share value [w] by the share value [c]
wherein λ is a decimal point position of the value a.
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
A secure inverse computation system
for receiving a share value [a] of a value a as an input,
a plurality of secure computation apparatuses,
processing circuitry
a normalization multiplier
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There is an insignificant extra-solution activity that must be made of note here:
for receiving a share value [a] of a value a as an input.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 4 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “for receiving a share value [a] of a value a as an input”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 4 is not eligible.
Claim 6, dependent upon claim 1, is directed towards the secure computation apparatus used in the secure inverse computation system of claim 1. Claim 6 is directed to the statutory category of machine, thus also satisfying Step 1. Moreover, at Step 2A none of the additional elements are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. There are no further additional elements beyond those recited in claim 1.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not eligible.
Claim 7, dependent upon claim 6, recites a non-transitory computer recording medium on which a program is stored with instructions of the method of claim 6, which is practiced by the apparatus of claim 1. Claim 7 is directed to the statutory category of article of manufacture, thus also satisfying Step 1. Moreover, at Step 2A none of the additional elements i.e., the non-transitory computer recording medium are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not eligible.
Claim 8, dependent upon claim 3, is directed towards the secure computation apparatus used in the secure normalization system of claim 3. Claim 8 is directed to the statutory category of machine, thus also satisfying Step 1. Moreover, at Step 2A none of the additional elements are more than high level generic computer components that amount to mere instructions to apply the abstract idea on a generic computer. There are no further additional elements beyond those recited in claim 1.
As disclosed in the claim in light of the specification, described are mere instructions to apply an exception, invoking the computing elements merely as a tool to perform an existing process. See MPEP 2105.06(f). Mere instructions to apply an exception cannot provide an inventive concept. The claim is not eligible.
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(d) and 101. The following is a statement of reasons for the indication of allowable subject matter.
Applicant claims a secure inverse computation system for receiving a share value [a] of a value a as an input, and calculating a share value [1/a] of the inverse of the value a, the secure inverse computation system as in claim 1 comprising:
a plurality of secure computation apparatuses,
wherein λ is a decimal point position of the value a, and
each of the plurality of secure computation apparatuses comprises
processing circuitry configured to:
generate a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generate a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generate a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generate a share value [c] of a normalization multiplier c obtained by bit-connecting the third sequence of share values {y0}, … {yλ-1} in reverse order;
calculate a share value [b] obtained by multiplying the share value [a] by the share value [c];
use the share value [b] to obtain a share value [w] obtained by calculating [1/b]; and
calculate the share value [1/a] obtained by multiplying the share value [w] by the share value [c].
R. Kikuchi et al., (“Efficient Bit-Decomposition and Modulus Conversion Protocols with an Honest Majority”, 2018) teaches a secret-sharing-based bit-decomposition for modulus conversion, using a multi-party paradigm for cooperative computation and using a shares-based approach (Kikuchi: Pg 8 Protocol 2). Kikuchi is silent as to the specific algorithm for bit-decomposition and the deriving of shares.
L. Kamm et al., “Secure Floating-Point Arithmetic and Private Satellite Collision Analysis”, 2013) teaches a multi-party computation for floating-point arithmetic using a shares-based approach (Kamma: Pg. 3 Points 1 and 2; Pg. 7 Algorithm 7). Kamm is silent as to the specific algorithm for bit-decomposition and deriving of shares.
Because claim 1 is allowable over the prior art, dependent claims 2, 6, and 7 are also allowable over the prior art.
Applicant claims a secure normalization system for receiving for normalizing a share value [a] of a value a, the secure normalization system as in claim 3 comprising:
a plurality of secure computation apparatuses,
wherein λ is a decimal point position of the value a, and
each of the plurality of secure computation apparatuses comprises
processing circuitry configured to:
generate a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generate a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generate a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generate a share value [c] of a normalization multiplier c obtained by bit-connecting the third sequence of share values {y0}, … {yλ-1} in reverse order; and
calculate a share value [b] obtained by multiplying the share value [a] by the share value [c].
R. Kikuchi et al., (“Efficient Bit-Decomposition and Modulus Conversion Protocols with an Honest Majority”, 2018) teaches a secret-sharing-based bit-decomposition for modulus conversion, using a multi-party paradigm for cooperative computation and using a shares-based approach (Kikuchi: Pg 8 Protocol 2). Kikuchi is silent as to the specific algorithm for bit-decomposition and the deriving of shares.
L. Kamm et al., “Secure Floating-Point Arithmetic and Private Satellite Collision Analysis”, 2013) teaches a multi-party computation for floating-point arithmetic using a shares-based approach (Kamma: Pg. 3 Points 1 and 2; Pg. 7 Algorithm 7). Kamm is silent as to the specific algorithm for bit-decomposition and deriving of shares.
Because claim 3 is allowable over the prior art, dependent claims 8 is also allowable over the prior art.
Applicant claims a secure normalization inverse computation method executed by a secure inverse computation system for receiving a share value [a] of a value a as an input, and calculating a share value [1/a] of the inverse of the value a, the secure inverse computation system including a plurality of secure computation apparatuses, the secure inverse computation method as in claim 4 comprising:
a plurality of secure computation apparatuses,
each of the plurality of secure computation apparatuses comprises
processing circuitry configured to:
generating, by a processing circuitry of each of the plurality of secure computation apparatuses, a first sequence of share values {a0}, …, {aλ-1} of a bit representation a0, …, aλ-1 of the value a from the share value [a];
generating, by a processing circuitry of the secure computation apparatus, a second sequence of share values {x0}, …, {xλ-1} of a flag sequence of x0, …, xλ-1 indicating a most significant bit of the first sequence of share values {a0}, …, {aλ-1};
generating, by the processing circuitry of the secure computation apparatus, a third sequence of share values {y0}, …, {yλ-1} of a bit sequence yo, …, yλ-1, {y0} and {y1} being share values of 0, {y2}, …, {yλ-1} being share values of a value obtained by calculating an exclusive logical sum of a result of calculating a logical product of logical negation of share values {ai-2} of the first sequence of share values and share values {xi-1} of the second sequence of share values, and share values {xi} of the second sequence of share values where i is an integer equal to or greater than 2 and smaller than λ, and {yλ} being a share value of a value obtained by calculating a logical product of a logical negation of a share value {aλ-2} of the first sequence of share values and a share value {xλ-1} of the second sequence of share values;
generating, by the processing circuitry of the secure computation apparatus a share value [c] of a normalization multiplier c obtained by bit-connecting the third sequence of share values {y0}, … {yλ-1} in reverse order,
calculating, by the processing circuitry of the secure computation apparatus, a share value [b] obtained by multiplying the share value [a] by the share value [c];
using, by the processing circuitry of the secure computation apparatus, the share value [b] to obtain a share value [w] obtained by calculating [1/b]; and
calculating, by the processing circuitry of the secure computation apparatus, the share value [1/a] obtained by multiplying the share value [w] by the share value [c]
wherein λ is a decimal point position of the value a.
R. Kikuchi et al., (“Efficient Bit-Decomposition and Modulus Conversion Protocols with an Honest Majority”, 2018) (hereinafter “Kikuchi”) teaches a secret-sharing-based bit-decomposition for modulus conversion, using a multi-party paradigm for cooperative computation and using a shares-based approach (Kikuchi: Pg 8 Protocol 2). Kikuchi is silent as to the specific algorithm for bit-decomposition and the deriving of shares.
L. Kamm et al., (“Secure Floating-Point Arithmetic and Private Satellite Collision Analysis”, 2013) (hereinafter “Kamm”) teaches a multi-party computation for floating-point arithmetic using a shares-based approach (Kamma: Pg. 3 Points 1 and 2; Pg. 7 Algorithm 7). Kamm is silent as to the specific algorithm for bit-decomposition and deriving of shares.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151