DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "at least one first signal transmission line" and “at least one second signal transmission line” in lines 3-5. It is unclear how the at least one first signal transmission line relates to the claimed first signal transmission line of claim 1. Additionally, claims 4-17 do not continue the use of “at least one” for example claim 4, line 6 recites “the second signal transmission line”. Corrections should be made for consistency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGPub 2015/0287362) in view of Wang et al. (US PGPub 2022/0139350).
Regarding claim 1, Lee discloses a display device (fig. 1 and [0062], an OLED display), comprising:
a display panel (fig. 1, display panel DP), the display panel comprising a plurality of light-emitting devices ([0076] and [0078], “Referring to FIG. 1 again, the display panel DP includes the scan lines SL1 to SLn, the light-emitting lines EL1 to ELn, the data lines DL1 to DLm, and the pixels PX” and “Each of the pixels PX includes an OLED (not shown) and a pixel circuit (not shown) that controls light emission of the OLED”);
a driving unit (fig. 1, driving voltage generator 400), wherein the driving unit has a first terminal and a second terminal (fig. 1, ELVDD output and ELVSS output); in a display stage, the first terminal outputs an initial power reference voltage to cathodes of the light-emitting devices ([0069], “The driving voltage generator 400 can include a boosting converter that boosts up the power voltage Vin so as to generate the first voltage ELVDD”and fig. 4, where ELVDD is output to the cathode of the ED element), and the second terminal outputs an initial anode reset voltage to anodes of the light-emitting devices ([0071], “The driving voltage generator 400 can generate the second voltage ELVSS having a predetermined voltage range in response to the driving voltage control signal VCS. The second voltage ELVSS can have a negative voltage within a range of about −4 volts to about −2 volts. The driving voltage generator 400 can selectively generate the second voltage ELVSS having about −4 volts, about −3 volts, or about −2 volts in response to the driving voltage control signal VCS”);
a first signal transmission line, arranged in the display panel and connected with the second terminal (fig. 4, line connecting ELVSS to ED), wherein the first signal transmission line transmits the initial anode reset voltage in the display stage ([0072], “the driving voltage generator 400 can generate the second voltage ELVSS having different voltage levels in accordance with frame periods. In addition, the driving voltage generator 400 can generate second voltages ELVSS having different voltage levels from each other in the predetermined voltage range”); and
a compensation line; in the display stage, the compensation line provides an anode reset voltage to reset the anodes of the light-emitting devise, the anode reset voltage varying with a variation of the initial power reference voltage ([0074]-[0075], “The discharge voltage generator 500 can receive the first voltage ELVDD and the second voltage ELVSS from the driving voltage generator 400. The discharge voltage generator 500 can generate a third voltage Vi2 and a fourth voltage Vi1 using the first and second voltages ELVDD and ELVSS. … The fourth voltage Vi1 can have an electric potential difference with respect to the second voltage ELVSS. For example, when the second voltage ELVSS has the voltage level of about −4 volts to about −2 volts, the fourth voltage Vi1 can have the voltage level of about −3 volts to about −1 volts”).
Lee discloses a driving voltage generator 400 as a driving unit. It would have been obvious to one of ordinary skill in the art to implement such driving voltage generator in the form a chip for its compact form factor for ease of physical design and packaging.
While Lee discloses generating a fourth voltage using ELVSS as an input, it has been known to connect a compensation and a transmission line for added redundancy. In a similar field of endeavor of display devices, Wang discloses wherein the compensation line is connected to any position of the first signal transmission line (fig. 2 and [0062], “That is, the voltage feedback lines J1 may be coupled to the fourth common electrode line C4 via positions corresponding to the fourth common electrode line C4 (i.e., detection points F2) at the both sides of the common electrode 1, acquire the actual common voltage on the fourth common electrode line C4 as the common voltage of the common electrode 1, and transmit the acquired actual common voltage to the common voltage compensation unit 2”); the compensation line provides a voltage at the position of the first signal transmission line (fig. 2 and [0070], “at least one voltage compensation line (for example, K1, K2, and K3) may be disposed in the display panel 100. One end of the voltage compensation line is coupled to a common electrode line that will receive the compensation voltage, and the other end of the voltage compensation line is coupled to the common voltage compensation unit 2. The common voltage compensation unit 2 transmits the compensation voltage to a common electrode line for compensating the common voltage of the common electrode 1 through the voltage compensation line.”).
In view of the teachings of Lee and Wang, it would have been obvious to one of ordinary skill in the art to include the voltage compensation line of Wang, within the system of Lee, for the purpose of providing a line to compensate ethe common voltage (Wang: [0003]).
Regarding claim 2, the combination of Lee and Wang further discloses wherein the driving chip comprises a voltage follower (Lee: fig. 3A, second discharge voltage generator 500-2), and the voltage follower comprises an input resistor (Lee: fig. 3A, resistor R10) and a feedback resistor (Lee: fig. 3A, resistor R20);
wherein a positive input end of the voltage follower receives the initial power reference voltage (Lee: fig. 3A, ELVSS), a negative input end of the voltage follower, one end of the input resistor, and one end of the feedback resistor are connected together (Lee: fig. 3A, inputs to the negative input terminal), another end of the input resistor is grounded (Lee: fig. 3A, Vref), another end of the feedback resistor is connected with an output end of the voltage follower (Lee: fig. 3A, output of the AMP), and the output end of the voltage follower is connected with the second terminal (Lee: output is Vi1 which is output from discharge voltage generator 500), the initial anode reset voltage changes synchronously with the initial power reference voltage (Lee: [0085], “The second discharge voltage generator 500-2 includes a differential amplifier AMP to output a voltage difference between the reference voltage Vref provided from the driving voltage generator 400 and the second voltage ELVSS as the fourth voltage Vi1”).
Regarding claim 3, the combination of Lee and Wang further discloses wherein a resistance value of the input resistor and a resistance value of the feedback resistor are equal (Lee: fig. 3A and [0087], “The differential amplifier AMP outputs the voltage difference between the reference voltage Vref and the second voltage. The voltage difference is substantially proportional to the resistance ratio of the first and second resistors R10 and R20. That is, the voltage level of the fourth voltage Vi1 can be controlled by adjusting the resistance ratio of the first and second resistors R10 and R20”).
Regarding claim 18, the combination of Lee and Wang further discloses wherein the driving chip further comprises a plurality of third terminals, and in the display stage, the plurality of third terminals output at least one gray-scale voltage to the display panel; when the gray-scale voltage is less than or equal to a preset voltage (Lee: [0075], “The third voltage Vi2 can have a voltage level lower than that of the data signal. For instance, the third voltage Vi2 can have the voltage level lower than the data signal at a highest gray-scale value”), the compensation line transmits the anode reset voltage that changes synchronously with the initial power reference voltage (Lee: [0075], “The fourth voltage Vi1 can have an electric potential difference with respect to the second voltage ELVSS. For example, when the second voltage ELVSS has the voltage level of about −4 volts to about −2 volts, the fourth voltage Vi1 can have the voltage level of about −3 volts to about −1 volts”).
Regarding claim 19, the combination of Lee and Wang further discloses wherein an amount of change in a voltage value of the anode reset voltage is equal to an amount of change in a voltage value of the initial power reference voltage (Lee: [0075], “The fourth voltage Vi1 can have an electric potential difference with respect to the second voltage ELVSS. For example, when the second voltage ELVSS has the voltage level of about −4 volts to about −2 volts, the fourth voltage Vi1 can have the voltage level of about −3 volts to about −1 volts”).
Claims 4-7, 9-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Wang further in view of Park et al. (US PGPub 2022/0157215)
Regarding claim 4, the combination of Lee and Wang further discloses wherein the display panel has a first end and a second end arranged corresponding to each other (Lee: fig. 1, display panel DP), the driving chip is arranged at the first end (Lee: fig. 1, driving voltage generator 400 shown above display panel DP), the display device comprises at least one first signal transmission line and at least one second signal transmission line (Lee: fig. 1, a plurality of lines), the second signal transmission line is connected with the first terminal (Wang: fig. 2 and [0071], point F1), and in the display stage, the second signal transmission line transmits the initial power reference voltage (Lee: [0085], “The second discharge voltage generator 500-2 includes a differential amplifier AMP to output a voltage difference between the reference voltage Vref provided from the driving voltage generator 400 and the second voltage ELVSS as the fourth voltage Vi1”);
wherein the driving chip further has a feedback terminal and a compensation terminal, the second signal transmission line is provided with a detection point, the first signal transmission line is provided with a compensation point corresponding to the detection point, the feedback terminal is connected with the detection point, and the compensation terminal is connected with the compensation point through the compensation line (Wang: fig. 2 and [0071]-[0073], multiple compensation points).
While the combination of Lee and Wang teaches a plurality of transmission lines, the combination is silent on the layout of the lines, it has been known to have the transmission lines extend in a direction from a first end to a second end. In a similar field of endeavor of display devices, Park discloses both the first signal transmission line and the second signal transmission line extend from the first end to the second end (fig. 1, showed a plurality of lines from 130 where fig. 4A shows elements 130a and 130b on either side of display area AA).
In view of the teachings of Lee, Wang, and Park, it would have been obvious to one of ordinary skill in the art to include the plurality of transmission lines extending from a first end to a second end as taught by Park, within the system of Lee and Wang, as a known layout which distributing elements based on space available in a display device (Park: [0053]).
Regarding claim 5, the combination of Lee, Wang and Park further discloses wherein the first signal transmission line and the second signal transmission line are arranged in different layers, and the first signal transmission line and the second signal transmission line are overlapping in a direction perpendicular to a light-emitting surface of the display panel (Lee: [0078], “Each of the pixels PX includes an OLED (not shown) and a pixel circuit (not shown) that controls light emission of the OLED. The pixel circuit includes a plurality of thin film transistors (TFTs) and a capacitor. The pixels PX includes red pixels representing the color red, green pixels representing the color green, and blue pixels representing the color blue. The OLEDs of the red, green, and blue pixels can include different organic light-emitting layers formed of different materials”).
Regarding claim 6, the combination of Lee, Wang and Park further discloses wherein the display panel comprises a display area and a non-display area connected with the display area (Lee: fig. 1, DP panel area and area outside of display panel), and the first signal transmission line and the second signal transmission line are located in the non-display area (Lee: fig. 1, where lines are arranged outside of the display panel);
wherein the second signal transmission line is provided with a plurality of detection points, the first signal transmission line is provided with a plurality of compensation points, and the detection points and the compensation points are arranged in a one-to-one correspondence (Wang: fig. 2 and [0071]-[0073], multiple compensation points).
Regarding claim 7, the combination of Lee, Wang and Park further discloses wherein the display panel comprises two first signal transmission lines and two second signal transmission lines, the two first signal transmission lines are respectively located in the non-display area on both sides of the display area in the display panel, and the two second signal transmission lines are respectively located in the non-display area on the both sides of the display area in the display panel (Park: fig. 4A; elements 130a and 130b arranged on each side of display area AA which would be connected via lines to display area AA);
wherein each of the two second signal transmission lines is provided with the plurality of detection points arranged at equal intervals, and the detection points located on the two second signal transmission lines are arranged axisymmetrically (Park: ([0053], ”shift registers 131a and 131b may be formed in the form of thin films in the GIP manner and arranged in a non-display area NA of the display panel 150. Each of the shift registers 131a and 131b may include a transistor, a capacitor, and so on. As illustrated in FIG. 4A, the shift registers 131a and 131b may be disposed in left and right non-display areas NA of the display panel 150. As illustrated in FIG. 4B, the shift registers 131a and 131b may be disposed in upper and lower non-display areas NA of the display panel 150. Because the shift registers 131a and 131b are in the form of thin films, the shift registers 131a and 131b may be distributed inside a display area AA as well as the non-display areas NA”).
Regarding claim 9, the combination of Lee, Wang and Park further discloses wherein the detection point is located at a position of the second signal transmission line away from the driving chip (Wang: fig. 2 and [0071]-[0073], multiple compensation points where the common voltage compensation unit 2 is shown below).
Regarding claim 10, the combination of Lee, Wang and Park further discloses wherein the display device further comprises a test line, and the feedback terminal is connected with the detection point through the test line (Lee: [0087], “The differential amplifier AMP outputs the voltage difference between the reference voltage Vref and the second voltage. The voltage difference is substantially proportional to the resistance ratio of the first and second resistors R10 and R20. That is, the voltage level of the fourth voltage Vi1 can be controlled by adjusting the resistance ratio of the first and second resistors R10 and R20” where Vref is the reference voltage which is the test line).
Claims 11 and 12 are within the scope of claims 2 and 3 respectively and are therefore interpreted and rejected based on similar reasoning.
Claim 13 recited the limitations of claim 2 and is therefore interpreted and rejected based on similar reasoning. Additionally, the combination of Lee and Wang discloses the voltage follower is arranged outside the driving chip (Lee: fig. 1, driving voltage generator 400 and discharge voltage generator 500).
Claim 14 is within the scope of claim 3 and is therefore interpreted and rejected based on similar reasoning.
Regarding claim 15, the combination of Lee, Wang and Park further discloses wherein the display device further comprises a circuit board (Lee: fig. 1, discharge voltage generator 500), the circuit board is connected with the driving chip (Lee: fig. 1, driving voltage generator 400 outputs ELVSS which is input into discharge voltage generator 500), and the voltage follower is integrally arranged on the circuit board (Lee: [0085], “Referring to FIG. 3A, the discharge voltage generator 500 includes a second discharge voltage generator 500-2 that generates the fourth voltage Vi1”).
Regarding claim 16, the combination of Lee, Wang and Park further discloses wherein the display device further comprises a first computing unit and a second computing unit (Park: fig. 18, elements 160 and 180), the first computing unit is connected with the detection point and receives the initial power reference voltage, the first computing unit calculates a difference value between the initial power reference voltage and a detection point voltage (Park: [0096], “The gate voltage controller 160 may output the first voltage control signal VCS1 in correspondence with the degree of the deterioration”), the second computing unit receives the initial anode reset voltage and the difference value, and the anode reset voltage is obtained by adding the difference value to the initial anode reset voltage (Park: fig. 18, “The power supply 180 may compensate the gate high voltage used for the scan signal Scan based on the first voltage control signal VCS1 received from the gate voltage controller 160 and output the compensated first gate high voltage Vgh1′”).
Regarding claim 17, the combination of Lee, Wang and Park further discloses wherein the first computing unit and the second computing unit are arranged inside the driving chip (Lee: [0069], “The driving voltage generator 400 can include a DC-DC converter. The driving voltage generator 400 can include a boosting converter that boosts up the power voltage Vin so as to generate the first voltage ELVDD. In addition, the driving voltage generator 400 can include a buck converter that falls down the power voltage Vin so as to generate the second voltage ELVSS”).
Claim 20 is within the scope of claims 1, 2, 4 and 10 and is therefore interpreted and rejected based on similar reasoning.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Wang and Park further in view of Li et al. (US PGPub 2019/0221175).
Regarding claim 8, the combination of Lee, Wang and Park further discloses wherein the second signal transmission line is provided with M detection points, and the first signal transmission line is provided with M first compensation points and N second compensation points; along a direction from the first end to the second end, the M detection points and the M first compensation points are arranged in a one-to-one correspondence, wherein M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1 (Wang: fig. 2 and [0071]-[0073], multiple compensation points);
wherein at least one of the second compensation points is arranged between two adjacent ones of the first compensation points, and an anode reset voltage corresponding to each of the second compensation points is obtained by (Lee: [0075]-[0076], “The third voltage Vi2 can have a voltage level lower than that of the data signal. For instance, the third voltage Vi2 can have the voltage level lower than the data signal at a highest gray-scale value. The fourth voltage Vi1 can have an electric potential difference with respect to the second voltage ELVSS. For example, when the second voltage ELVSS has the voltage level of about −4 volts to about −2 volts, the fourth voltage Vi1 can have the voltage level of about −3 volts to about −1 volts. Referring to FIG. 1 again, the display panel DP includes the scan lines SL1 to SLn, the light-emitting lines EL1 to ELn, the data lines DL1 to DLm, and the pixels PX”).
While the combination of Lee, Wang and Park teaches a plurality of signal lines, it has been known to use interpolation to calculate data between points. In a similar field of endeavor of display devices, Li discloses a voltage is obtained by interpolating anode voltages ([0047], “the SOP circuit 322 may generate the first driving voltage by interpolating the first high voltage (e.g., VO) and the first low voltage (e.g., V1) according to a second portion of bits Din2_2 of the new gray-scale data of the first sub-pixel. The SOP circuit 322 may generate the second driving voltage by interpolating the second high voltage (e.g., V1) and the second low voltage (e.g., V2) according to a second portion of bits Din2_2 of the new gray-scale data of the second sub-pixel”).
In view of the teachings of Lee, Wang, Park and Li, it would have been obvious to one of ordinary skill in the art to use interpolation as taught by Li, to calculate data of Lee, Wang and Park, for the purpose of using a known mathematical technique to estimate unknown values within the range of a known dataset which decreases the amount of measured data required.
Response to Arguments
Applicant’s arguments, see pages 2-5, filed 03/16/2026, with respect to the rejection(s) of claim(s) 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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