Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Remarks
The Examiner acknowledges the amendments to the claims as well as cancellation of claims 6-8.
Claim Objection
The Examiner acknowledges the amendment to claim 1, and withdraws the claim objection due to amendment to the claims.
U.S.C. 112
The Examiner acknowledges and has fully considered the applicant’s arguments. The Examiner withdraws the 112(d) rejections due to cancellation of claims 6-8. The Examiner withdraws the majority of 112(b) rejections due to amendments to the claims, however, the 112(b) rejections regarding [r] and {r} the claims remains. Regarding [r] and {r} the applicant argues, (Remarks page 10 paragraph 4), that “both [r] and {r} are share values that would be r if restored.” The Examiner notes that this does not clear up what was unclear in the claims regarding this. From the Non-Final Rejection mailed on 12/09/2025, (page 5 paragraph 2), “The applicant’s specification paragraph [0014] describes variables in the square brackets as a hidden numerical value, and paragraph [0015] describes variables in the curly brackets as a hidden bit value. With no other or previous mention of “[r]” in claim 1, it is unclear if [r] is meant to be the same as {r} or some other value entirely.” The applicant’s response of “both [r] and {r} are share values that would be r if restored” does not help clarify if [r] and {r} are the same or not. If they are the same, then to further clarify, the Examiner notes that it may be easier to understand if they are both either [r] or {r}. If they are not the same, then that would lead to lack of antecedent basis issues regarding [r], because as mentioned in the 112(b) rejection of the Non-Final Rejection mailed on 12/09/2025, (page 5 paragraph 2), “the share value [r]” is the first mention of [r]. For these reasons, the 112(b) rejections regarding it being unclear if [r] and {r} are the same or not, remains.
U.S.C. 101
The Examiner acknowledges and has fully considered all of the applicant’s arguments. The applicant seemingly argues, (Remarks page 11), that what is claimed is patent eligible due to improvement in how technology operates even if they recite abstract ideas. The Examiner respectfully notes that improvements to technology/improvements to computer functionality is in consideration for 101 rejection, however, improvements should not be directed to an abstract idea, but rather technology, see MPEP 2106.04(d)(1), MPEP 2106.05(a). Furthermore, throughout the arguments, (Remarks pages 11-21) the applicant refers to the newly amended limitation of “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network.” The Examiner notes that transmitting and receiving data over a network is considered well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)i). However, due to the amended claims, specifically the various specific circuitry components rather than a generic “processing circuitry”, required for the limitations in claims 1-3, the 101 rejections are withdrawn for claims 1-3.
The Examiner notes that the limitations of specific circuitry components seemingly has not been amended to claim 4. The applicant seemingly recites patent eligibility under the framework of Desjardins, (Remarks page 11 – page 12 paragraphs 1-2). The applicant seemingly argues, (Remarks page 12 paragraph 3 – page 13 paragraphs 1-2) that the amended claims reflects a technical improvement in technology, pointing out a technical problem to be solved in the applicant’s specification, as well as pointing out improvements in a technique. The Examiner notes that the improvements discussed in (Remarks page 13 paragraph 2) seemingly is directed at mathematical concepts. The applicant further argues, (Remarks page 13 paragraph 3) that the amended claim 1 reflects the improvements by utilizing nine specific circuitry components, bit decomposition circuitry, first bit sequence generation circuitry, flag sequence generation circuitry, flag calculation circuitry, normalization circuitry, second bit sequence generation circuitry, flag calculation circuitry, normalization circuitry, inverse square root calculation circuitry, and inverse normalization circuitry. The Examiner notes that these components are not found in claim 4 limitations, thus the argument is for regarding unclaimed subject matter for claim 4.
The applicant continues, (Remarks page 14 paragraph 1), seemingly arguing that the characterization of the claims reciting “a mathematical concept” consisting of “mathematical relationships, and mathematical formulas” is too high a level of generality. The Examiner respectfully disagrees at least for the reasons given in the Non-Final Rejection Office Action mailed on 12/09/2025, (page 18-19), regarding the specific limitations of the claim recite the mathematical concepts including the type of mathematical concepts they fall into.
The applicant continues (Remarks page 14 paragraphs 2-3) seemingly arguing that the claims are directed to an improvement in technology, seemingly arguing that amended claim 1 recites nine specific circuitry components which is a specific distributed computing architecture. The Examiner respectfully notes that this is an argument for unclaimed elements not found in claim 4.
The applicant continues (Remarks page 15 paragraph 1), seemingly arguing that the previous Office Action stripped the claims, reducing them to bare mathematical operations, and does not give explanation of why specific distributed architecture and inter-apparatus communications are not technological improvements. The Examiner respectfully disagrees for at least the reasons given in the Non-Final Rejection Office action mailed 12/09/2025. Furthermore, seemingly the only inter-apparatus communications found in claim 4 limitations is “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network”. The Examiner notes that this limitations is a high level of generality, with no specifics as to what is meant by “in cooperation with others” besides transmitting and receiving data over the network, which is considered insignificant extra-solution activity, and well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i).
The applicant continues, (Remarks page 15 paragraphs 3-4), seemingly arguing that the amended claims integrate the abstract idea into a practical application. Regarding claim 4, the Examiner respectfully disagrees, see new reasons for rejection below.
The applicant continues, (Remarks page 16 paragraph 1), seemingly arguing that “a plurality of secure computation apparatuses” comprises nine specific circuitry components that reflect a specific architecture, and that this specific architecture provides a technological improvement. The Examiner respectfully disagrees with regards to claim 4, noting that the nine specific circuitry components are unclaimed elements of claim 4.
The applicant continues, (Remarks page 16 paragraph 2), seemingly arguing that the amended claims recite nine specific circuitry components, bit decomposition circuitry, first bit sequence generation circuitry, flag sequence generation circuitry, normalization multiplier generation circuitry, second bit sequence generation circuitry, flag calculation circuitry, normalization circuitry, inverse square root calculation circuitry, and inverse normalization circuitry. The Examiner notes that these are unclaimed elements of claim 4.
The applicant continues, (Remarks page 17 paragraph 2), seemingly arguing that the amended claim limitations of “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network” are inter-apparatus communications not merely incidental, and that share values that are transmitted and received over the network are fragments of secret-shared data, and the cooperative processing among multiple apparatuses is what enables computation to occur while keeping the underlying data hidden. The Examiner notes that the claimed limitation is at a high level of generality and does not give specifics as to what is meant by “in cooperation with others” nor what data is transmitted and received over a network. Merely transmitting and receiving data over a network is considered insignificant extra-solution activity, and well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i).
The applicant continues, (Remarks page 17 paragraph 3 – page 18 paragraph 1), seemingly arguing that an improvement of technology is outlined in the specification, that the improvements are not merely improvements to an abstract mathematical concept, and that the claims specify how the secure computation process is improved through a particular arrangement of nine cooperating circuitry components operating across multiple networked apparatuses. The Examiner respectfully notes that the particular arrangement of nine cooperating circuitry components are unclaimed elements of claim 4.
The applicant continues, (Remarks page 18 paragraph 2-3 – page 19 paragraph 1), seemingly arguing that the Office action does not address the amended claims now reciting nine specific circuitry components. The Examiner respectfully notes that the applicant seemingly is arguing unclaimed elements of claim 4.
The applicant continues, (Remarks page 19 paragraphs 2-3), seemingly arguing that the amended claims recite a specific combination of a plurality of secure computation apparatuses connected via a network and nine specific circuitry components within each apparatus, bit decomposition circuitry, first bit sequence generation circuitry, flag sequence generation circuitry, normalization multiplier generation circuitry, second bit sequence generation circuitry, flag calculation circuitry, normalization circuitry, inverse square root calculation circuitry, and inverse normalization circuitry, and cooperation operation among the apparatuses via communications including transmitting and receiving data over the network. The Examiner respectfully notes that the specific combination of circuitry components are seemingly unclaimed elements with regards to claim 4, and that transmitting and receiving data over a network is considered insignificant extra-solution activity, and well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i). The applicant continues, arguing that the distributed architecture with cooperative inter-apparatus communication is not merely linking mathematics to a computing environment. The applicant continues arguing that the share values transmitted and received over the network are fragments of secret-shared data, and the cooperative processing ensures that no single apparatus has access to the complete data, thus this is a meaningful technological transformation, not mere field-of-use linking. The Examiner respectfully notes that these are seemingly unclaimed elements with respect to claim 4. The amended claim 4 recites the limitations of “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network”. The Examiner notes that the claim seemingly does not limit what is meant by “in cooperation with others” besides noting that it includes “transmitting and receiving data over the network”, which is considered insignificant extra-solution activity, and well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i).
The applicant continues, (Remarks page 20), seemingly arguing that the absence of any 35 U.S.C. 102, or 103 rejection, and the Examiner’s deferral of allowable subject matter indicates that the claimed invention is not conventional. The Examiner respectfully notes that the lack of 35 U.S.C 102, or 103 rejections and the deferring of indication of allowable subject matter does not necessarily indicate that the claimed invention is not conventional. The deferral of indication of allowable subject matter and lack of 35 U.S.C. 102, or 103 rejection too may be from either from numerous 35 U.S.C. 101, or 112 rejections or that the claims being so unclear that the Examiner cannot reasonably interpret all of what is meant to be claimed in order to perform proper examination upon the claimed invention. Furthermore, 35 USC 101 and 35 USC 102/103 are different inquiries, and lack of prior art does not mean that the claims are statutory.
The applicant continues, (Remarks page 20), seemingly arguing that the previous Office Action does not identify evidence showing that the specific combination of a plurality of secure computation apparatuses, each comprising nine named circuitry components operating in cooperation via network communications to perform secure inverse square root computation is well-understood, routine, conventional or in the field of secure computation. The Examiner respectfully notes that the nine circuitry components are seemingly unclaimed elements with regards to claim 4. Furthermore, claim 4 recites cooperation between components at a high level of generality without specifying what is meant by “in cooperation with others”, and that “transmitting and receiving data over the network” is considered insignificant extra-solution activity, and well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i) (Berkheimer evidence). Therefore, any claim element that Examiner indicated as being an insignificant extra solution activity under the step 2A prong 2 analysis, Examiner has provided evidence as being well understood, routine and conventional as required by Berkheimer, under the step 2B analysis.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the various circuitries, such as “bit decomposition circuitry”, and “first bit sequence generation circuitry”, and “flag sequence generation circuitry”, and “normalization multiplier generation circuitry”, and “second bit sequence circuitry”, and “flag calculation circuitry”, and “normalization circuitry”, and “inverse square root calculation circuitry”, and “inverse normalization circuitry” each seemingly individually working “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 3-4, the claims recite the limitations of: “in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network”. It is unclear what is meant by “in cooperation with others”, furthermore, it is unclear what data is being transmitted and received over the network. It is unclear if the data being transmitted and received is the data found in the body of the claim, or some other data.
Claim 2 inherits the same deficiencies as claim 1 based on dependence.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 4 is rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Regarding claim 4, under the Alice Framework Step 1, claim 4 falls within the four statutory categories of patentable subject matter identified by 35 USC 101: a process, machine, manufacture, or a composition of matter.
Under the Alice Framework Step 2A prong 1, claim 4 recites an abstract idea, including a mathematical concept. Specifically, claim 4 recites the following, mathematical relationships, and mathematical formulas:
“A secure inverse square root computation method executed by receiving a share value [a] of a value a as an input, and calculating a share value [1/√a] of the inverse of the square root of the value a, the secure inverse square root computation method comprising: generating, in cooperation with others a first sequence of share values {ao}, ...,{a[Symbol font/0x6C] - i} of a bit representation ao, ..., a[Symbol font/0x6C] - 1 of the value a from the share value [a]; obtaining, in cooperation with others for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, a share value {a'i} of a bit a'i by calculating a logical sum of a share value {ai} and a share value {ai+1} of the first sequence of share values to generate a second sequence of share values {a'o}, ... , {a'[Symbol font/0x6C]’-1} of a bit sequence a'o,...,a'[Symbol font/0x6C]’ - 1; generating, in cooperation with others a third sequence of share values {xo}, ...,{x[Symbol font/0x6C]' - 1} of a flag sequence xo, ..., x[Symbol font/0x6C]’ - 1 indicating the most significant bit of the second sequence of share values {a'o}, ...,{a'[Symbol font/0x6C]’-1}; generating, in cooperation with others a share value [c'] of a normalization multiplier c' obtained by bit-connecting the third sequence of share values {xo}, ...,{x[Symbol font/0x6C]' - 1} in reverse order; setting, a share value {a”i} of a bit a”i as a share value {a2i} of the first sequence of share values for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]” to generate a fourth sequence of share values {a"o}, ...,{a"[Symbol font/0x6C]' - 1} of a bit sequence a"o,..., a"[Symbol font/0x6C]’- 1; summing, in cooperation with others each product {xj} {a”j} of share values {xj} of the third sequence of share values and a share value {a"j} of the fourth sequence of share values where j is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]’ to calculate a share value {r} of a multiplication flag r; using, in cooperation with others the share value [a], the share value [c'], and the share value {r} to calculate [c'][c'][2a] when the multiplication flag r is 1 and [c'] [c'] [a] when the multiplication flag r is 0 to calculate a share value [b]; using, in cooperation with others the share value [b] and the share value [r] to calculate [1/√b] * √2 when the multiplication flag r is 1 and [1/√b] when the multiplication flag r is 0 to calculate a share value [w]; and calculating, in cooperation with others the share value [1/√a] by multiplying the share value [w] by the share value [c'], wherein [Symbol font/0x6C] is a decimal point position of the value a, [Symbol font/0x6C]' is the smallest integer equal to or greater than [Symbol font/0x6C]/2, and [Symbol font/0x6C]" is the largest integer equal to or smaller than [Symbol font/0x6C]/2.”
Under the Alice Framework Step 2A prong 2 analysis, claim 4 recites the additional elements of: “secure computation apparatus”, “plurality of secure computation apparatuses”, “a secure inverse square root computation system”, and “communications including transmitting and receiving data over the network”. The additional elements of “secure computation apparatus”, “plurality of secure computation apparatuses”, “a secure inverse square root computation system”, are generally linking the use of the judicial exception to a particular technological environment or field of use. The additional elements limit the abstract idea, but merely confines the use of the abstract idea to a particular technological environment, see MPEP 2106.04(d), 2106.05(h). The additional element of “communications including transmitting and receiving data over the network”, is insignificant extra-solution activity. For these reasons, the additional elements of claim 4 are not integrated into a practical application.
Under the Alice Framework Step 2B analysis, the additional elements of “secure computation apparatus”, “plurality of secure computation apparatuses”, “a secure inverse square root computation system”, are generally linking the use of the judicial exception to a particular technological environment or field of use. The additional elements limit the abstract idea, but merely confines the use of the abstract idea to a particular technological environment, see MPEP 2106.05(I)(A)(iv), 2106.05(h). The additional element of “communications including transmitting and receiving data over the network”, is well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i). For these reasons, claim 4 is not amounting to significantly more than the abstract idea.
Allowable Subject Matter
Claims 1-3 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 4 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, and U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1-2, the applicant claims a secure inverse square root computation system, whereas the system as in claim 1 comprises:
“A secure inverse square root computation system for receiving a share value [a] of a value a as an input, and calculating a share value [1/√a] of the inverse of the square root of the value a, the secure inverse square root computation system comprising:
A plurality of secure computation apparatuses, wherein
[Symbol font/0x6C] is a decimal point position of the value a, [Symbol font/0x6C]’ is the smallest integer equal to or greater than [Symbol font/0x6C]/2, and [Symbol font/0x6C]” is the largest integer equal to or smaller than [Symbol font/0x6C]/2, and
each of the plurality of secure computation apparatuses comprises:
bit decomposition circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network, a first sequence of share values {a0}, …, {a[Symbol font/0x6C]-1} of a bit representation a0, …, a[Symbol font/0x6C]-1 of the value a from the share value [a];
first bit sequence generation circuitry configured to obtain, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, a share value {a’i} of a bit a’i by calculating a logical sum of a share value {ai} and a share value {ai+1} of the first sequence of share values to generate a second sequence of share values {a’0}, …,{a’[Symbol font/0x6C]’-1} of a bit sequence a’0, …, a’[Symbol font/0x6C]’-1;
flag sequence generation circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} of a flag sequence x0, …, x[Symbol font/0x6C]’-1 indicating the most significant bit of the second sequence of share values {a’0}, …, {a’[Symbol font/0x6C]’-1};
normalization multiplier generation circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a share value [c’] of a normalization multiplier c’ obtained by bit-connecting the third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} in reverse order;
second bit sequence generation circuitry configured to set a share value {a”i} of a bit a”i as a share value {a2i} of the first sequence of share values for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, to generate a fourth sequence of share values {a”0}, …, {a”[Symbol font/0x6C]’-1} of a bit sequence a”0, …, a”[Symbol font/0x6C]’-1 ;
flag calculation circuitry configured to sum, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, each product {xj} {a”j} of share values {xj} of the third sequence of share values and a share value {a”j} of the fourth sequence of share values, where j is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]’, to calculate a share value {r} of a multiplication flag r;
normalization circuitry configured to use, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [a], the share value [c’], and the share value {r} to calculate [c’][c’][2a] when the multiplication flag r is 1 and [c’][c’][a] when the multiplication flag r is 0 to calculate a share value [b];
inverse square root calculation circuitry configured to use, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [b] and the share value [r] to calculate [1/√b]* √2 when the multiplication flag r is 1 and [1/√b] when the multiplication flag r is 0 to calculate a share value [w]; and
inverse normalization circuitry configured to calculate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [1/√a] by multiplying the share value [w] by the share value [c’].”
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Regarding claim 3, the applicant claims a secure normalization system, whereas the system as in claim 3 comprises:
A secure normalization system for normalizing a share value [a] of a value a in order to calculate a share value [1/√a] of the inverse of the square root of the value a, the secure normalization system comprising:
a plurality of secure computation apparatuses,
wherein [Symbol font/0x6C] is a decimal point position of the value a, [Symbol font/0x6C]’ is the smallest integer equal to or greater than [Symbol font/0x6C]/2, and [Symbol font/0x6C]” is the largest integer equal to or smaller than [Symbol font/0x6C]/2, and
each of the plurality of secure computation apparatuses comprises:
bit decomposition circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network, a first sequence of share values {a0}, …, {a[Symbol font/0x6C]-1} of a bit representation a0, …, a[Symbol font/0x6C]-1 of the value a from the share value [a];
first bit sequence generation circuitry configured to obtain, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, a share value {a’i} of a bit a’i by calculating a logical sum of a share value {ai} and a share value {ai+1} of the first sequence of share values to generate a second sequence of share values {a’0}, …,{a’[Symbol font/0x6C]’-1} of a bit sequence a’0, …, a’[Symbol font/0x6C]’-1;
flag sequence generation circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} of a flag sequence x0, …, x[Symbol font/0x6C]’-1 indicating the most significant bit of the second sequence of share values {a’0}, …, {a’[Symbol font/0x6C]’-1};
normalization multiplier generation circuitry configured to generate, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a share value [c’] of a normalization multiplier c’ obtained by bit-connecting the third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} in reverse order;
second bit sequence generation circuitry configured to set a share value {a”i} of a bit a”i as a share value {a2i} of the first sequence of share values for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, to generate a fourth sequence of share values {a”0}, …, {a”[Symbol font/0x6C]’-1} of a bit sequence a”0, …, a”[Symbol font/0x6C]’-1 ;
flag calculation circuitry configured to sum, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, each product {xj} {a”j} of share values {xj} of the third sequence of share values and a share value {a”j} of the fourth sequence of share values, where j is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]’, to calculate a share value {r} of a multiplication flag r; and
normalization circuitry configured to use, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [a], the share value [c’], and the share value {r} to calculate [c’][c’][2a] when the multiplication flag r is 1 and [c’][c’][a] when the multiplication flag r is 0 to calculate a share value [b].
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Regarding claim 4, the applicant claims a secure inverse square root method, whereas the method as in claim 4 comprises:
A secure inverse square root computation method executed by each secure computation apparatus of a plurality of secure computation apparatuses of a secure inverse square root computation system for receiving a share value [a] of a value a as an input, and calculating a share value [1/√a] of the inverse of the square root of the value a, the secure inverse square root computation method comprising:
Generating, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over a network, a first sequence of share values {a0}, …, {a[Symbol font/0x6C]-1} of a bit representation a0, …, a[Symbol font/0x6C]-1 of the value a from the share value [a];
Obtaining, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, a share value {a’i} of a bit a’i by calculating a logical sum of a share value {ai} and a share value {ai+1} of the first sequence of share values to generate a second sequence of share values {a’0}, …,{a’[Symbol font/0x6C]’-1} of a bit sequence a’0, …, a’[Symbol font/0x6C]’-1;
generating, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} of a flag sequence x0, …, x[Symbol font/0x6C]’-1 indicating the most significant bit of the second sequence of share values {a’0}, …, {a’[Symbol font/0x6C]’-1};
generating, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, a share value [c’] of a normalization multiplier c’ obtained by bit-connecting the third sequence of share values {x0}, …, {x[Symbol font/0x6C]’-1} in reverse order;
setting a share value {a”i} of a bit a”i as a share value {a2i} of the first sequence of share values for each i where i is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]”, to generate a fourth sequence of share values {a”0}, …, {a”[Symbol font/0x6C]’-1} of a bit sequence a”0, …, a”[Symbol font/0x6C]’-1 ;
summing, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, each product {xj} {a”j} of share values {xj} of the third sequence of share values and a share value {a”j} of the fourth sequence of share values, where j is an integer equal to or greater than 0 and smaller than [Symbol font/0x6C]’, to calculate a share value {r} of a multiplication flag r;
using, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [a], the share value [c’], and the share value {r} to calculate [c’][c’][2a] when the multiplication flag r is 1 and [c’][c’][a] when the multiplication flag r is 0 to calculate a share value [b];
using, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [b] and the share value [r] to calculate [1/√b]* √2 when the multiplication flag r is 1 and [1/√b] when the multiplication flag r is 0 to calculate a share value [w]; and
calculating, in cooperation with others of the plurality of secure computation apparatuses via communications including transmitting and receiving data over the network, the share value [1/√a] by multiplying the share value [w] by the share value [c’], wherein [Symbol font/0x6C] is a decimal point position of the value a, [Symbol font/0x6C]’ is the smallest integer equal to or greater than [Symbol font/0x6C]/2, and [Symbol font/0x6C]” is the largest integer equal to or smaller than [Symbol font/0x6C]/2.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Dimitrov et al. (Dimitrov, V., Kerik, L., Krips, T., Randmets, J., & Willemson, J. (2016, August 12). Alternative implementations of secure real numbers. IACR Cryptology ePrint Archive. https://eprint.iacr.org/2016/773 ), hereinafter, “Dimitrov” discusses secure data calculations, including private values used in square root calculations (Page 11 section 4.3.5). However, Dimitrov fails to teach or suggest the italicized claim limitations in combination with the remaining claim limitations as referenced above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/J.A.K./ Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182
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