Prosecution Insights
Last updated: April 19, 2026
Application No. 17/791,623

RELIABLE SUPERVISED MACHINE LEARNING USING INTERVAL ARITHMETIC

Non-Final OA §112
Filed
Jul 08, 2022
Examiner
BUI, KENNY KIM
Art Unit
2182
Tech Center
2100 — Computer Architecture & Software
Assignee
Modal Technology Corporation
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
4y 0m
To Grant
85%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
6 granted / 10 resolved
+5.0% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 0m
Avg Prosecution
27 currently pending
Career history
37
Total Applications
across all art units

Statute-Specific Performance

§101
29.8%
-10.2% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
7.7%
-32.3% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§112
DETAILED ACTION The Office Action is sent in response to Applicant’s Communication received on 07/08/2022 and 09/12/2023 for application number 17/791,623. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract of “WO 2021/142440 A1”, Oath/declaration, IDS, Claims, Certified Copy of Foreign Priority Application, International search report, Written opinion, Notice of Acceptance under U.S.C. 371 and a preliminary amendment with applicant’s remarks. Examiner Notes the following: A Preliminary Amendment has been filed on 07/08/2022, amending Claims 1 and 4, and specification. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description: reference characters 40 and 42 from figure 2b is missing from the specification. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs mentioned in the description: “training accelerator 36” on p.19 ll.12 and 18-19 from the specification. “central processing unit servers 32” on p.19, ll.17-18 from the specification Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: “modal interval arithmetic processing units”. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claims 1 and 4 objected to because of the following informalities: In claim 1, step a, “subdivisions arithmetically” should read as “subdivisions are arithmetically” (emphasis added). In claim 4, step e, “between the bisection context the bisection queue” should read as “between the bisection context and the bisection queue” (emphasis added). Appropriate correction is required. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation is: For claims 1 and 4, “modal interval arithmetic processing units”. The Term “modal interval arithmetic processing units” does not appear to be a term of art. See Search history for PE2E search. IP.com, and Bing search for “modal interval arithmetic processing units" that show either zero hits or the instant application and it’s WIPO publication. As such, the limitation is being interpreted under 35 U.S.C. 112(f). Because this claim limitation is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 1 and 4, Claim limitation “modal interval arithmetic processing units” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In the specification, there is no disclosure of adequate structure to perform the claimed function. In particular, the specification states that there is a modal processing unit comprising of modal interval processing units, but not modal interval arithmetic processing units. However, there is no disclosure of any particular structure, either explicitly or inherently, to perform the modal interval arithmetic processing for a modal processing unit comprising of modal interval arithmetic processing units. The use of the term “modal interval arithmetic processing units” are not adequate structure for performing the modal interval arithmetic processing because it does not describe a particular structure for performing the function. As would be recognized by those of ordinary skill in the art, the term “modal interval arithmetic processing units” refers to any kind of structure to do modal interval arithmetic processing and can be performed in any number of ways in hardware, software or a combination of the two. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which modal interval arithmetic processing units structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Regarding claims 2-3, effectively depends on claim 1 and are rejected for the reasons given above. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above, the disclosure does not provide adequate structure to perform the claimed functions of modal interval arithmetic processing given the claimed unit. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, Hayes (US 9,588,736 B2, in the IDS filed 07/08/2022) discloses modal interval processor and general improvement over interval arithmetic using modal intervals. See at least col.2. Sayyar-Rodsari et al. (US 2005/0187643 A1) discloses using various processors for neural network optimization and application of interval arithmetic on models with some respect to branch and bound search strategy. See par.26-31, 167-169, and 180. Delling et al. (US 2012/0254597 A1) discloses a branch and bound distributed system. See figure 3B, par.2 and 35-38. Gennat et al. (NPL: “Sensitivity Analysis Using Interval Arithmetic”) discloses a branch and bound bisection algorithm including bisection context of various lists, interval vectors and bounds. See Tables 1 and 2. Qi et al. (NPL: “The Parallel Implementation of Interval Global Optimization Algorithm and Its Application) discloses a branch and bound delete algorithm, with work list of interval vectors and respective upper and lower bounds. See Sec.III.A. Gau et al. (NPL: “Parallel Interval-Newton Using Message Passing: Dynamic Load Balancing Strategies”) discloses Various processors for load balancing with bisection operations [See Sec.2 for bisecting problems into subproblems] and bisection tracking/queue [See Sec.4.1 for global state information and Sec.3.2 for global work index vectors]; And undertaking, in connection to depth first domain bisection, operations relative to the bisection context which are memorialized in relation to the bisection queue, operations which include a work stealing scheme for simultaneous breadth first search, depth and breadth searching being concurrently executed. [Sec.3.4 for dynamic load balancing algorithms i.e. work stealing and Sec.6 for depth and breadth operations done together] Eck (NPL: “Introduction to Programming Using Java”) discloses linked lists and stacks made from linked lists, with various operations like delete, pop, and push. See Sec.9.2, 9.2.5, and 9.3.1. For claim 1, the prior art of record, alone or in combination, does not teach or suggest a combination as claimed including: “…the bisection context characterized by a plurality of arrays, each array of the plurality of arrays having a number of elements equal to a number of variables of an objective function to be minimized, the bisection queue being a collection of bisection records…. An index to a particular element of an array in the bisection context… a record associated with the particular array element…”. Regarding claim 4, the prior art of record, alone or in combination, does not teach or suggest a combination as claimed including “…the bisection context including a plurality of arrays (domain, Bottom, Top, and Subdomain), Domain and Subdomain being interval arrays, bottom and top being integer arrays, the arrays having a number of elements equal to a number of variables of an objective function to be minimized, the bisection queue being a collection of bisection records…. An index to a particular element of an array in the bisection context… a record associated with the particular array element……”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571)272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNY K. BUI/Patent Examiner, Art Unit 2182 (571)270-0604 /ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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Prosecution Timeline

Jul 08, 2022
Application Filed
Jul 08, 2022
Response after Non-Final Action
Jan 22, 2026
Non-Final Rejection — §112
Mar 31, 2026
Applicant Interview (Telephonic)
Mar 31, 2026
Examiner Interview Summary

Precedent Cases

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Patent 12425047
METHODS AND APPARATUS TO PERFORM WEIGHT AND ACTIVATION COMPRESSION AND DECOMPRESSION
2y 5m to grant Granted Sep 23, 2025
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
85%
With Interview (+25.0%)
4y 0m
Median Time to Grant
Low
PTA Risk
Based on 10 resolved cases by this examiner. Grant probability derived from career allow rate.

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