DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed January 16, 2026 have been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), and Shibazaki et al. (JP 2011054625 A).
Regarding claim 1, Perez et al. teaches:
A semiconductor device [20, Col. 3, Lines 61-63, Fig. 1] comprising:
a substrate [24, Col. 4, Lines 10-14, Fig. 1] having a substrate obverse surface [31, Col. 4, Lines 10-11, Fig. 1] and a substrate reverse surface [32, Col. 4, Lines 10-11, Fig. 1] facing away from each other in a thickness direction;
a conductive part [34 “conductive terminals”, Col. 4, Lines 19-23, Fig. 1] made of an electrically conductive material on the substrate obverse surface [31];
an electronic component [22 “semiconductor chip”, Col. 4, Lines 19-23, Fig. 1] disposed on the substrate obverse surface [31] and electrically connected to the conductive part [34]; and
an outer sealing resin [“Encapsulation”, Shown in Fig. 1, not described in more detail in the description, Col. 1, Lines 21-32, Fig. 1] covering the electronic component [22, Fig.1] and at least a portion of the substrate [24, Fig. 1], the outer sealing resin [“Encapsulation”, Shown in Fig. 1, not described in more detail in the description, Col. 1, Lines 21-32, Fig. 1] being exposed to outside of the semiconductor device [20, Col. 3, Lines 61-63, Fig. 1],
wherein the conductive part [34, Fig. 1] includes an overlapping wiring trace [36 “bond wires”, Col. 4, Lines 20-23, Fig. 1] having an overlapping portion that overlaps with the electronic component [22] as viewed in the thickness direction, with the overlapping portion being not electrically bonded to the electronic component [22, Col. 4, Lines 20-23].
the electronic component [22] has an opposing surface disposed opposite the substrate obverse surface [31], the opposing surface including an insulating portion [44 “epoxy”, Col. 1, Lines 57-59, Fig. 1] made of an insulating material.
Perez et al. does not teach:
the overlapping wiring trace overlaps with the electronic component only at the insulating portion of the opposing surface as viewed in the thickness direction.
and the insulating portion is formed by a portion of the additional resin.
Clark et al. teaches:
the overlapping wiring trace [52, Fig. 6] overlaps with the electronic component [50, Fig. 6] only at the insulating portion [51, Col. 4, Lines 55-57, Fig. 6] of the opposing surface as viewed in the thickness direction.
the insulating portion [51] is formed by a portion of the sealing resin [54, Col. 5, Lines 21-24, Fig. 6].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Clark et al. into the teachings of Perez et al. to include the overlapping wiring trace overlaps with the electronic component only at the insulating portion of the opposing surface as viewed in the thickness direction, and the insulating portion is formed by a portion of the additional sealing resin, for the purpose of providing a shorter conduction path, allowing greater flexibility in designing conduction paths, increasing package density, and avoiding unwanted contact.
Perez et al. and Clark et al. do not teach:
the electronic component includes an electronic element and an additional sealing resin covering the electronic element in a manner such that an entirety of the electronic element is spaced apart from the outer sealing resin, and the additional sealing resin is embedded within the outer sealing resin.
the additional sealing resin forms the opposing surface, and the opposing surface as a whole is spaced apart from the substrate obverse surface in the thickness direction.
Shibazaki et al. teaches:
the electronic component [22, paragraph [0025-0026], [0031-0032], Fig. 3(A)]includes an electronic element [control circuit inside 22, paragraph [0031], Fig. 3(A)] and an additional sealing resin [not given a numerical designation, talked on in paragraph [0025], [0031], Fig. 3(A)] covering the electronic element [control circuit inside 22, Fig. 3(A)] in a manner such that an entirety of the electronic element [control circuit inside 22, Fig. 3(A)] is spaced apart from the outer sealing resin [16, paragraph [0029], Fig. 3(A)], and the additional sealing resin [not given a numerical designation, talked on in paragraph [0025], [0031], Fig. 3(A)] is embedded within the outer sealing resin [16, Fig. 3(A)]
the additional sealing resin [not given a numerical designation, talked on in paragraph [0025], [0031], Fig. 3(A)] forms the opposing surface [bottom of 22, Fig. 3(A)], and the opposing surface [bottom of 22, Fig. 3(A)] as a whole is spaced apart from the substrate [11, paragraph [0025-0026], [0029], [0031-0032], Fig. 3(A)] obverse surface in the thickness direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Shibazaki et al. into the teachings of Perez et al. and Clark et al. to include the electronic component includes an electronic element and an additional sealing resin covering the electronic element in a manner such that an entirety of the electronic element is spaced apart from the outer sealing resin, and the additional sealing resin is embedded within the outer sealing resin, the additional sealing resin forms the opposing surface, and the opposing surface as a whole is spaced apart from the substrate obverse surface in the thickness direction, for the purpose of protecting features within the device, relieving, reducing and preventing stresses, improving reliability, improving electrical connections between features within the device, isolating features from other features to prevent short circuits, generating less heat, and simpler and easier for subsequent processes and maintenance.
Regarding claim 3, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Clark et al. further teaches
wherein an entire surface of the opposing surface is the insulating portion [51, Col. 4, Lines 54-67 to Col. 5, Lines 1-5, Fig. 6].
Regarding claim 6, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Perez et al. further teaches:
wherein the electronic element [22, Col. 3, Lines 61-66, Fig. 1] comprises a switching element [“transistor”].
Regarding claim 18, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Perez et al. further teaches:
wherein the substrate reverse surface [32] is exposed from the outer sealing resin [See Fig. 1].
Regarding claim 19, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Perez et al. further teaches:
wherein the substrate [24] is made of a ceramic material [Col. 2, Lines 58-64, Claim 16, Fig. 1].
Regarding claim 20, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Shibazaki et al. further teaches:
further comprising a passive electronic component [22, paragraph [0025-0026], [0031-0032], Fig. 3(A)] disposed on the substrate [11, paragraph [0025-0026], [0029], [0031-0032], Fig. 3(A)] obverse surface, wherein the passive electronic component [22, Fig. 3(A)] is covered by the outer sealing resin [16, paragraph [0029], Fig. 3(A)] and is spaced apart from the additional sealing resin [paragraph [0025], [0031], Fig. 3(A)].
Regarding claim 21, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Shibazaki et al. further teaches:
wherein the electronic element [control circuit inside 22, paragraph [0031],Fig. 3(A)] overlaps with the opposing surface [bottom of 22, Fig. 3(A)] as viewed in the thickness direction, and the opposing surface [bottom of 22, Fig. 3(A)] is disposed between the electronic element [control circuit inside 22, Fig. 3(A)] and the substrate [11, Fig. 3(A)] obverse surface in the thickness direction.
Regarding claim 22, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Shibazaki et al. further teaches:
wherein the overlapping wiring trace [26, paragraph [0025-0026], [0031], Fig. 3(A)] is disposed between the substrate [11, Fig. 3(A)] obverse surface and the opposing surface [bottom of 22, Fig. 3(A)] in the thickness direction.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), and Shibazaki et al. (JP 2011054625 A) as applied to claim 1 above, and further in view of Chen (US 20090253278 A1). Chen (US 20090253278 A1) will hereby be referred to as Chen ‘278.
Regarding claim 5, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
However, Perez et al., Clark et al., and Shibazaki et al. do not teach:
wherein the electronic element comprises a passive electronic component.
Chen ‘278 teaches:
wherein the electronic element [220, 219, paragraph [0029], Fig. 2a] comprises a passive electronic component [222, 221, Fig. 2a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen ‘278 into the teachings of Perez et al., Clark et al., and Shibazaki et al. to include wherein the electronic element comprises a passive electronic component, for the purpose of influencing the flow of power without requiring an external power source to function.
Regarding claim 7, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
However, Perez et al., Clark et al., and Shibazaki et al. do not teach:
wherein the electronic element comprises a controller chip configured to output a drive signal.
Chen ‘278 teaches:
wherein the electronic element [219] comprises a controller chip configured to output a drive signal [Paragraph [0029], Fig. 2a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen ‘278 into the teachings of Perez et al., Clark et al., and Shibazaki et al. to include wherein the electronic element comprises a controller chip configured to output a drive signal, for the purpose of controlling the input/output signal transmissions of the device.
Claims 8, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), and Shibazaki et al. (JP 2011054625 A) as applied to claim 1 above, and further in view of Chen ‘278 (US 20090253278 A1), and Voss (US 4827376 A).
Regarding claim 8, Perez et al., Clark et al., and Shibazaki et al. teach the semiconductor device according to claim 1.
Perez et al., Clark et al., and Shibazaki et al. do not teach:
a first lead disposed on the substrate obverse
and a semiconductor chip disposed on the first lead
Chen ‘278 teaches:
a first lead [221, 222 paragraph [0029], Fig. 2a] disposed on the substrate obverse surface [202, Fig. 2a].
a semiconductor chip [219, 220] disposed on the first lead [221, 222, Fig. 2a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen ‘278 into the teachings of Perez et al., Clark et al., and Shibazaki et al. to include a first lead disposed on the substrate obverse and a semiconductor chip disposed on the first lead, for the purpose of providing conductive paths to other electronic features, and to electrically connecting the semiconductor chip to the first lead.
Perez et al., Clark et al., Shibazaki et al., and Chen ‘278 do not teach:
The first lead having a higher thermal conductivity than the substrate.
Voss teaches:
The first lead [11, Col. 6, Lines 20-24] having a higher thermal conductivity than the substrate [Col. 1, Lines 43-46].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Voss into the teachings of Perez et al., Clark et al., Shibazaki et al., and Chen ‘278 to include the first lead having a higher thermal conductivity than the substrate, for the purpose of improving heat dissipation from the semiconductor chip.
Due to the finite number of acceptable elements, it would have been obvious to try a material for the first leads having a higher thermal conductivity than the substrate, for the purpose of transferring heat more effectively. [See MPEP 2143(I)(E) “Obvious To Try”]
Regarding claim 15, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Chen ‘278 further teaches:
wherein the overlapping wiring trace [330 “conductive connection”, paragraph [0041], Fig. 6a-6b] is electrically isolated from the electronic component.
Regarding claim 16, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Perez et al. further teaches:
wherein the semiconductor chip [22, Col. 3, Lines 65-66, Fig. 1] comprises a power transistor that controls electric power.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), Shibazaki et al. (JP 2011054625 A), Chen ‘278 (US 20090253278 A1), and Voss (US 4827376 A) as applied to claim 8 above, and further in view of Purdy et al. (GB 2099221 A).
Regarding claim 9, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Chen ‘278 further teaches:
comprising a bonding part [218, paragraph [0029], Fig. 2a, 2b] formed on the substrate obverse surface [202].
wherein the first lead [222, Fig. 2a, 2b] is bonded to the bonding part [218, Fig. 2a, 2b] by a bonding material [232a, Fig. 2a, 2b].
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
the bonding part containing a same electrically conductive material as the electrically conductive material of the conductive part.
Purdy et al. teaches:
the bonding part [22, paragraph [0035], Claim 5, Fig. 1] containing a same electrically conductive material as the electrically conductive material of the conductive part [20, paragraph [0035], Claim 5, Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Purdy et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include the bonding part containing a same electrically conductive material as the electrically conductive material of the conductive part, for the purpose of cheaper and simpler manufacturing, and to facilitate electric flow.
Due to a finite number of conductive materials, it would have been obvious to try the same electrically conductive material as the conductive part for the bonding part. [See MPEP 2143(I)(E) “Obvious To Try”]
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), Shibazaki et al. (JP 2011054625 A), Chen ‘278 (US 20090253278 A1), and Voss (US 4827376 A) as applied to claim 8 above, and further in view of Chen et al. (US 20050093121 A).
Regarding claim 10, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
wherein the first lead has a portion covered by the outer sealing resin and another portion exposed from the outer sealing resin.
Chen et al. teaches:
wherein the first lead [222 (right), paragraph [0030], Fig. 2] has a portion covered by the outer sealing resin [260, paragraph [0030], Fig. 2] and another portion exposed from the outer sealing resin [260].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include wherein the first lead has a portion covered by the outer sealing resin and another portion exposed from the outer sealing resin, for the purpose of electrically connecting the device with an external source.
Regarding claim 11, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
further comprising a second lead spaced apart from the first lead and bonded to the conductive part by an electrically conductive bonding material,
wherein the second lead has a portion covered by the outer sealing resin and a portion exposed from the outer sealing resin.
Chen et al. teaches:
further comprising a second lead [222 (left), Fig. 2] spaced apart from the first lead [222 (right)] and bonded to the conductive part [214 “metallic layers”, paragraph [0023], Fig. 2] by an electrically conductive bonding material [paragraph [0026], Fig. 2],
wherein the second lead [222 (left), Fig. 2] has a portion covered by the outer sealing resin [260, Fig. 2] and a portion exposed from the outer sealing resin [260, Fig. 2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include further comprising a second lead spaced apart from the first lead and bonded to the conductive part by an electrically conductive bonding material, wherein the second lead has a portion covered by the outer sealing resin and a portion exposed from the outer sealing resin, for the purpose of electrically connecting the device with an external source.
Regarding claim 12, Perez et al., Clark et al., Shibazaki et al., Chen ‘278, Voss and Chen et al. teach the semiconductor device according to claim 11.
Clark et al. further teaches:
the overlapping wiring trace [52] is connected to the first pad [47 (left), Fig. 6] and the second pad [47 (right), Fig. 6].
Chen et al. further teaches:
wherein the conductive part [214] includes:
a first pad [214, paragraph [0026-0027], Fig. 2] electrically bonded to the electronic component [230, paragraph [0026-0027], Fig. 2]; and
a second pad [214, paragraph [0026-0027], Fig. 2] electrically bonded to the second lead [222 (left), Fig. 2].
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Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). (MPEP 2125)
Regarding claim 13, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Clark et al. further teaches:
the overlapping wiring trace [52] is connected to the first pad [47 (left), Fig. 6] and the second pad [47 (right), Fig. 6].
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
wherein the conductive part includes:
a first pad electrically bonded to the electronic component; and
a second pad electrically connected to the semiconductor chip
Chen et al. teaches:
wherein the conductive part [214] includes:
a first pad [214] electrically bonded to the electronic component [230]; and
a second pad [214] electrically connected to the semiconductor chip [240, paragraph [0027], Fig. 2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include wherein the conductive part includes: a first pad electrically bonded to the electronic component; and a second pad electrically connected to the semiconductor chip, for the purpose of electrically connecting features of the device.
Regarding claim 14, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Clark et al. further teaches:
the overlapping wiring trace [52] is connected to the first pad [47 (left), Fig. 6] and the second pad [47 (right), Fig. 6].
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
further comprising a second electronic component disposed on the substrate obverse surface and electrically connected to the conductive part, wherein the conductive part includes:
a first pad electrically bonded to the electronic component; and
a second pad electrically bonded to the second electronic component.
Chen et al. teaches:
further comprising a second electronic component [240] disposed on the substrate obverse surface [213 “upper surface”, paragraph [0026], Fig. 2]] and electrically connected to the conductive part [214, Fig. 2], wherein the conductive part [214] includes:
a first pad [214, Fig. 2] electrically bonded to the electronic component [230]; and
a second pad [214, See Fig. 2] electrically bonded to the second electronic component [240].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chen et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include further comprising a second electronic component disposed on the substrate obverse surface and electrically connected to the conductive part, wherein the conductive part includes: a first pad electrically bonded to the electronic component; and a second pad electrically bonded to the second electronic component, for the purpose of electrically connecting features of the device, while increasing density of the device.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Perez et al. (US 6552430 B1), in view of Clark et al. (US 5592025 A), Shibazaki et al. (JP 2011054625 A), Chen ‘278 (US 20090253278 A1), and Voss (US 4827376 A) as applied to claim 8 above, and further in view of Kondou et al. (US 7535076 B2).
Regarding claim 17, Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss teach the semiconductor device according to claim 8.
Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss do not teach:
wherein the semiconductor chip includes a reverse electrode bonded to the first lead.
Kondou et al. teaches:
wherein the semiconductor chip [6, Col. 7, Lines 14-17, Fig. 7] includes a reverse electrode bonded to the first lead [28, Col. 7, Lines 14-17, Fig. 7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kondou et al. into the teachings of Perez et al., Clark et al., Shibazaki et al., Chen ‘278 and Voss to include wherein the semiconductor chip includes a reverse electrode bonded to the first lead, for the purpose of including a reverse electrode to function as an anode and a cathode to facilitate the flow of power, manufacturing at a lower cost and improve productivity.
Response to Arguments
Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-2, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that the current prior art of record does not teach the amendments to independent claim 1. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art the amended limitations of independent claim 1 can be overcome by newly cited source Shibazaki et al. (JP 2011054625 A). Newly cited source Shibazaki et al. (JP 2011054625 A) discloses in Fig. 3(A), the electronic component [22] includes an electronic element [control circuit inside 22] and an additional sealing resin [not given a numerical designation, talked on in paragraph [0025], [0031]] covering the electronic element [control circuit inside 22] in a manner such that an entirety of the electronic element [control circuit inside 22] is spaced apart from the outer sealing resin [16], and the additional sealing resin [not given a numerical designation, talked on in paragraph [0025], [0031]] is embedded within the outer sealing resin [16]. One of ordinary skill in the art would be motivated to combine Shibazaki et al. and primary reference Perez et al. (US 6552430 B1), for the purpose of protecting features within the device, generating less heat, and preventing short circuits.
Applicant argues on pages 2-3, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that claims 5 and 7 which depend on independent claim 1 should be in condition for allowance, due to the amendments to independent claim 1. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 3, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that claims 8, 15 and 16 which depend on independent claim 1 should be in condition for allowance, due to the amendments to independent claim 1. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 3, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that claim 9 which depends on independent claim 1 should be in condition for allowance, due to the amendments to independent claim 1. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on pages 3-4, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that claims 10-14 which depend on independent claim 1 should be in condition for allowance, due to the amendments to independent claim 1. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 4, Section: Claim Rejections – 35 U.S.C. §103, in remarks filed January 16, 2026 that claim 17 which depends on independent claim 1 should be in condition for allowance, due to the amendments to independent claim 1. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 4, Section: New Claim, in remarks filed January 16, 2026 that claim 22 was added, and due to the amendments to independent claim 1, new claim 22 should be in condition for allowance. Examiner disagrees with Applicant because the limitations of new claim 22 can be overcome by newly cited secondary reference Shibazaki et al. (JP 2011054625 A).
In summary, the amendments to independent claim 1 can be overcome by newly cited secondary reference Shibazaki et al. (JP 2011054625 A). New claim 22 can be overcome by newly cited secondary reference Shibazaki et al. (JP 2011054625 A). All claims directly or indirectly dependent on independent claim 1 are therefore rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 04/08/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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