DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Applicant’s arguments and amendments filed on 06/04/2026 canceling Claim 19 and amending Claims 1, 5, and 7. Claims 1 – 3, 5, 7 – 10, 13, 14, and 18 are examined.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Independent Claims 1, 5, and 7 and dependent Claims 2, 3, 8 – 10, 13, 14, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent Claims 1 and 7 and dependent Claims 2, 3, 8, 13, 14, 18, and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Independent Claim 1, ll. 4 - 5 and independent Claim 7, ll. 4 - 5 recites “a memory configured to store instructions; and processing circuitry coupled to the memory and configured to execute the instructions to:”. Therefore, Claims 1 and 7 are interpreted as claims with computer-implemented functional claim limitations. MPEP2161.01(I), seventh paragraph stated “Computer-implemented inventions are often disclosed and claimed in terms of their functionality. For computer-implemented inventions, the determination of the sufficiency of disclosure will require an inquiry into the sufficiency of both the disclosed hardware and the disclosed software due to the interrelationship and interdependence of computer hardware and software. The critical inquiry is whether the disclosure of the application relied upon reasonably conveys to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date. Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 682. 114 USPQ2d 1349, 1356 (citing Ariad Pharm., Inc. V. Eli Lilly & Co, 598 F.3d 1336, 1351, 94 USPQ2d 1161, 1172 (Fed. Cir. 2010) in the context of determining possession of a claimed means of accessing disparate databases).” As discussed below, the original disclosure failed to provide a disclosure of the computer, in this case the “processing circuit”, and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the computer-implemented invention.
The original Specification Para. [0035] disclosed “The processing circuit may be dedicated hardware, or may be a processor that executes programs stored in a memory. In the processing circuit, some functions may be realized by hardware, and the remaining functions may be realized by software or firmware. That is, the processing circuit can be realized by hardware, software, firmware, or a combination of these.” The original disclosure failed to provide a disclosure of the computer and algorithm, i.e., software, in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the language of the claims without any additional details. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Figs. 5, 7, and 8 just show a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “910: Processor”. In Figs. 5, 7, and 8 one-way or two-way arrows lines connect the “910: Processor” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 16 just shows a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “909: Electronic Circuit”. In Fig. 16 one-way or two-way arrows lines connect the “909: Electronic Circuit” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 26 just shows a rectangle labeled “83 – control unit” inside another rectangle labeled “910: Processor”. In Fig. 26 one-way or two-way arrows lines connect the “910: Processor” rectangle to three other rectangles and the assembly of rectangles form a “802: Server” which is connected to a rectangle labeled “801: Database”. The assembly of the “802: Server” rectangle with the “801: Database” rectangle formed an “800: OADR (Open Architecture Data Repository)” which communicated to a “40: management business device” that contained seven rectangles representing different “business devices”. Para. [0055] disclosed “The satellite constellation forming system 600 includes an electronic circuit 909 in place of the processor 910. The electronic circuit 909 is a dedicated electronic circuit that realizes the functions of the satellite constellation forming system 600. Specifically, the electronic circuit 909 is a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, a logic IC, a GA, an ASIC, or an FPGA. GA is an abbreviation for Gate Array. The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” Para. [0056] disclosed “Each of the processor and the electronic circuit is also called processing circuitry. That is, the functions of the satellite constellation forming system 600 are realized by the processing circuitry.” The original disclosure keeps repeating that the processing circuitry could be all hardware or a combination of hardware and software. Specification Para. [0055] disclosed that the claimed processing circuitry could be every type of computing device known in the art. The claimed processing circuitry could be a dedicated, i.e., custom designed to only perform the claimed functional limitations, electronic circuit [interpreted as a printed circuit board (PCB) populated with electronic components] which could be a single circuit (single PCB) or a composite circuit (two or more PCBs). The claimed processing circuitry could be a programmed processor or a parallel-programmed processor which is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing where software algorithms perform the functional limitations. As well known in the prior art, generic computers with generic CPU(s) were capable of running a wide variety of different software programs to perform a near infinite number of computer functions. The claimed processing circuitry could be “hard-wired” devices that do not run on software because the programming was burned into or designed into the device. A logic IC (Integrated Circuit) were semiconductor devices that perform boolean logic operations (AND, OR, NOT, etc.) on digital input signals. A gate array (GA) was a semi-custom ASIC which was an “Application-Specific Integrated Circuits”. As implied by the name, “Application-Specific Integrated Circuits” (ASIC) were integrated circuits customized for a specific task and the specific task cannot be changed once manufactured. ASIC were basically dedicated electronic circuits on a standard 18” x 24” PCB shrunk down to fit on a silicon chip smaller than a human thumbnail. Gate arrays (GA)s and “Application-Specific Integrated Circuits” (ASIC)s did not run on software because the programming was designed into the device, i.e., “hard-wired” to only run a single program. FPGAs (Field-Programmable Gate Arrays) were integrated circuits, i.e., a single computer chip, that were reconfigurable after manufacturing, offering flexibility, rapid prototyping, and faster time-to-market for low-to-medium volumes, though they are less power-efficient. FPGAs were manufactured with basic logic circuit and memory on a single computer chip. After purchasing a FPGA, a user would “flash”, i.e., burn-into, their specific program into the FPGA’s on chip memory so that the FPGA would only run that specific program until the FPGA’s on chip memory was erased and a new program was “flashed”, i.e., burned-into, the FPGA’s on chip memory.
If the claimed processing circuitry is interpreted as dedicated, i.e., custom designed, electronic circuit board(s) with one or more logic ICs, gate arrays (GA), “Application-Specific Integrated Circuits” (ASIC), and/or FPGAs (Field-Programmable Gate Arrays), then Applicant’s disclosure would have to describe the structure of the hardware and the programming, i.e., algorithms, that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. However, as discussed above, Applicant’s original disclosure failed to sufficiently describe details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms, to show possession of the claimed subject matter at the time of filing. In fact, Applicant’s original disclosure failed to describe any details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms. Therefore, it is impossible for Applicant’s original disclosure to show possession of the claimed subject matter at the time of filing.
If the claimed processing circuitry is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing, then Applicant’s disclosure would have to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. However, Applicant’s disclosure failed to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. Independent Claims 1 and 7, ll. 5 - 18 recites “processing circuitry coupled to the memory and configured to execute the instructions to: generate a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently, transmit the first orbit control command to the plurality of satellites, after the space object has passed through the passage region, generate a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes, and transmit the second orbit control command to the plurality of satellites”. Independent Claims 1 and 7, ll. 19 - 26 recites “the processing circuitry generates the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order, and”. Independent Claims 1 and 7, ll. 27 - 34 recites “the processing circuitry generates the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. Dependent Claims 2 and 3 recites “…processing circuitry generates the first orbit control command to form the satellite constellation” performing various computer implemented functions. The original disclosure failed to provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the claim language of the claims. Fig. 9 is a flowchart of the satellite constellation forming process (S100) where step (S102) was labeled “Form Passage Region”. Specification Paras. [0043] – [0045] basically repeat the claim limitations of Claims 1 and 7, ll. 5 - 13 and Claims 1 and 7, ll. 19 - 26 without any further details. Fig. 9 step (S104) was labeled “Restore to Previous State”. Specification Paras. [0052] – [0053] basically repeat the claim limitations of Claims 1 and 7, ll. 14 - 18 and Claims 1 and 7, ll. 27 - 34 without any further details. Specification Para. [0054] disclosed “In this embodiment, the functions of the satellite constellation forming system 600 are realized by software. As a variation, the functions of the satellite constellation forming system 600 may be realized by hardware.” Para. [0055] disclosed “The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” The original disclosure keeps repeating that the processing circuitry could be all hardware, all software, or a combination of hardware and software without disclosing any details. MPEP2161.01(I), third paragraph stated “Regents of the Univ. of Cal. v. Eli Lilly & Co., 119 F.3d 1559, 1568, 43 USPQ2d 1398, 1405-06 (Fed. Cir. 1997) ("The description requirement of the patent statute requires a description of an invention, not an indication of a result that one might achieve if one made that invention."). Problems satisfying the written description requirement for original claims often occur when claim language is generic or functional, or both. Ariad, 593 F.3d at 1349, 94 USPQ2d at 1171 ("The problem is especially acute with genus claims that use functional language to define the boundaries of a claimed genus. In such a case, the functional claim may simply claim a desired result, and may do so without describing species that achieve that result. But the specification must demonstrate that the applicant [inventor] has made a generic invention that achieves the claimed result and do so by showing that the applicant [inventor] has invented species sufficient to support a claim to the functionally-defined genus.") MPEP2161.01(I), sixth paragraph stated “Similarly, original claims may lack written description when the claims define the invention in functional language specifying a desired result but the specification does not sufficiently describe how the function is performed or the result is achieved. For software, this can occur when the algorithm or steps/procedure for performing the computer function are not explained at all or are not explained in sufficient detail (simply restating the function recited in the claim is not necessarily sufficient). In other words, the algorithm or steps/procedure taken to perform the function must be described with sufficient detail so that one of ordinary skill in the art would understand how the inventor intended the function to be performed.” The computer-implemented functional limitations of Claims 1 – 3 and 7 simply claim a desired result and the algorithm or steps/procedure for performing the computer functions are not explained at all or are not explained in sufficient detail because the Specification simply restates the functions recited in the claims. MPEP2161.01(I), eight paragraph stated “When examining computer-implemented functional claims, examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary (5th ed., 2002). Applicant may "express that algorithm in any understandable terms including as a mathematical formula, in prose, or as a flow chart, or in any other manner that provides sufficient structure." Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323, 1340 (Fed. Cir. 2008) (internal citation omitted). It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015) (reversing and remanding the district court’s grant of summary judgment of invalidity for lack of adequate written description where there were genuine issues of material fact regarding "whether the specification show[ed] possession by the inventor of how accessing disparate databases is achieved"). If the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention a rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, for lack of written description must be made.” For all the reasons discussed above, the original disclosure failed to provide a description of the computer and algorithm(s) in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the claimed invention. By failing to provide a description of the computer and algorithm(s) in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the claimed invention Applicant is trying to claim any and all means for achieving the claimed invention. Claims 2, 3, 8, 13, and 14 depend from Claim 1 and are rejected for the same reasons. Claim 18 depends from Claim 7 and is rejected for the same reasons.
Independent Claim 5 and dependent Claims 9 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Independent Claim 5, ll. 5 - 12 recites “generating via processing circuitry configured to execute instructions stored in a memory, a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently,”. Independent Claim 5, ll. 14 - 17 recites “after the space object has passed through the passage region, generating, via the processing circuitry, a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes,”. Independent Claim 5, ll. 20 - 27 recites “generating, via the processing circuitry, the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order, such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order”. Independent Claim 5, ll. 28 - 35 recites “generating, via the processing circuitry, the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. Therefore, Claims 5, 9, and 10 are interpreted as claims with computer-implemented functional claim limitations. MPEP2161.01(I), seventh paragraph stated “Computer-implemented inventions are often disclosed and claimed in terms of their functionality. For computer-implemented inventions, the determination of the sufficiency of disclosure will require an inquiry into the sufficiency of both the disclosed hardware and the disclosed software due to the interrelationship and interdependence of computer hardware and software. The critical inquiry is whether the disclosure of the application relied upon reasonably conveys to those skilled in the art that the inventor had possession of the claimed subject matter as of the filing date. Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 682. 114 USPQ2d 1349, 1356 (citing Ariad Pharm., Inc. V. Eli Lilly & Co, 598 F.3d 1336, 1351, 94 USPQ2d 1161, 1172 (Fed. Cir. 2010) in the context of determining possession of a claimed means of accessing disparate databases).” As discussed below, the original disclosure failed to provide a disclosure of the computer, in this case the “processing circuit”, and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the computer-implemented invention.
The original Specification Para. [0035] disclosed “The processing circuit may be dedicated hardware, or may be a processor that executes programs stored in a memory. In the processing circuit, some functions may be realized by hardware, and the remaining functions may be realized by software or firmware. That is, the processing circuit can be realized by hardware, software, firmware, or a combination of these.” The original disclosure failed to provide a disclosure of the computer and algorithm, i.e., software, in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the language of the claims without any additional details. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Figs. 5, 7, and 8 just show a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “910: Processor”. In Figs. 5, 7, and 8 one-way or two-way arrows lines connect the “910: Processor” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 16 just shows a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “909: Electronic Circuit”. In Fig. 16 one-way or two-way arrows lines connect the “909: Electronic Circuit” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 26 just shows a rectangle labeled “83 – control unit” inside another rectangle labeled “910: Processor”. In Fig. 26 one-way or two-way arrows lines connect the “910: Processor” rectangle to three other rectangles and the assembly of rectangles form a “802: Server” which is connected to a rectangle labeled “801: Database”. The assembly of the “802: Server” rectangle with the “801: Database” rectangle formed an “800: OADR (Open Architecture Data Repository)” which communicated to a “40: management business device” that contained seven rectangles representing different “business devices”. Para. [0055] disclosed “The satellite constellation forming system 600 includes an electronic circuit 909 in place of the processor 910. The electronic circuit 909 is a dedicated electronic circuit that realizes the functions of the satellite constellation forming system 600. Specifically, the electronic circuit 909 is a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, a logic IC, a GA, an ASIC, or an FPGA. GA is an abbreviation for Gate Array. The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” Para. [0056] disclosed “Each of the processor and the electronic circuit is also called processing circuitry. That is, the functions of the satellite constellation forming system 600 are realized by the processing circuitry.” The original disclosure keeps repeating that the processing circuitry could be all hardware or a combination of hardware and software. Specification Para. [0055] disclosed that the claimed processing circuitry could be every type of computing device known in the art. The claimed processing circuitry could be a dedicated, i.e., custom designed to only perform the claimed functional limitations, electronic circuit [interpreted as a printed circuit board (PCB) populated with electronic components] which could be a single circuit (single PCB) or a composite circuit (two or more PCBs). The claimed processing circuitry could be a programmed processor or a parallel-programmed processor which is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing where software algorithms perform the functional limitations. As well known in the prior art, generic computers with generic CPU(s) were capable of running a wide variety of different software programs to perform a near infinite number of computer functions. The claimed processing circuitry could be “hard-wired” devices that do not run on software because the programming was burned into or designed into the device. A logic IC (Integrated Circuit) were semiconductor devices that perform boolean logic operations (AND, OR, NOT, etc.) on digital input signals. A gate array (GA) was a semi-custom ASIC which was an “Application-Specific Integrated Circuits”. As implied by the name, “Application-Specific Integrated Circuits” (ASIC) were integrated circuits customized for a specific task and the specific task cannot be changed once manufactured. ASIC were basically dedicated electronic circuits on a standard 18” x 24” PCB shrunk down to fit on a silicon chip smaller than a human thumbnail. Gate arrays (GA)s and “Application-Specific Integrated Circuits” (ASIC)s did not run on software because the programming was designed into the device, i.e., “hard-wired” to only run a single program. FPGAs (Field-Programmable Gate Arrays) were integrated circuits, i.e., a single computer chip, that were reconfigurable after manufacturing, offering flexibility, rapid prototyping, and faster time-to-market for low-to-medium volumes, though they are less power-efficient. FPGAs were manufactured with basic logic circuit and memory on a single computer chip. After purchasing a FPGA, a user would “flash”, i.e., burn-into, their specific program into the FPGA’s on chip memory so that the FPGA would only run that specific program until the FPGA’s on chip memory was erased and a new program was “flashed”, i.e., burned-into, the FPGA’s on chip memory.
If the claimed processing circuitry is interpreted as dedicated, i.e., custom designed, electronic circuit board(s) with one or more logic ICs, gate arrays (GA), “Application-Specific Integrated Circuits” (ASIC), and/or FPGAs (Field-Programmable Gate Arrays), then Applicant’s disclosure would have to describe the structure of the hardware and the programming, i.e., algorithms, that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. However, as discussed above, Applicant’s original disclosure failed to sufficiently describe details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms, to show possession of the claimed subject matter at the time of filing. In fact, Applicant’s original disclosure failed to describe any details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms. Therefore, it is impossible for Applicant’s original disclosure to show possession of the claimed subject matter at the time of filing.
If the claimed processing circuitry is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing, then Applicant’s disclosure would have to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. However, Applicant’s disclosure failed to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. Independent Claim 5, ll. 5 - 12 recites “generating via processing circuitry configured to execute instructions stored in a memory, a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently,”. Independent Claim 5, ll. 13 recites “transmitting the first orbit control command to the plurality of satellites”. Independent Claim 5, ll. 14 - 17 recites “after the space object has passed through the passage region, generating, via the processing circuitry, a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes,”. Independent Claim 5, ll. 18 recites “transmitting the second orbit control command to the plurality of satellites”. Independent Claim 5, ll. 20 - 27 recites “generating, via the processing circuitry, the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order, such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order”. Independent Claim 5, ll. 28 - 35 recites “generating, via the processing circuitry, the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. The original disclosure failed to provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the claim language of the claims. Fig. 9 is a flowchart of the satellite constellation forming process (S100) where step (S102) was labeled “Form Passage Region”. Specification Paras. [0043] – [0045] basically repeat the claim limitations of Claim 5, ll. 5 - 12 and Claim 5, ll. 20 - 27 without any further details. Fig. 9 step (S104) was labeled “Restore to Previous State”. Specification Paras. [0052] – [0053] basically repeat the claim limitations of Claim 5, ll. 14 - 17 and Claim 5, ll. 28 - 35 without any further details. Specification Para. [0054] disclosed “In this embodiment, the functions of the satellite constellation forming system 600 are realized by software. As a variation, the functions of the satellite constellation forming system 600 may be realized by hardware.” Para. [0055] disclosed “The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” The original disclosure keeps repeating that the processing circuitry could be all hardware, all software, or a combination of hardware and software without disclosing any details. MPEP2161.01(I), third paragraph stated “Regents of the Univ. of Cal. v. Eli Lilly & Co., 119 F.3d 1559, 1568, 43 USPQ2d 1398, 1405-06 (Fed. Cir. 1997) ("The description requirement of the patent statute requires a description of an invention, not an indication of a result that one might achieve if one made that invention."). Problems satisfying the written description requirement for original claims often occur when claim language is generic or functional, or both. Ariad, 593 F.3d at 1349, 94 USPQ2d at 1171 ("The problem is especially acute with genus claims that use functional language to define the boundaries of a claimed genus. In such a case, the functional claim may simply claim a desired result, and may do so without describing species that achieve that result. But the specification must demonstrate that the applicant [inventor] has made a generic invention that achieves the claimed result and do so by showing that the applicant [inventor] has invented species sufficient to support a claim to the functionally-defined genus.") MPEP2161.01(I), sixth paragraph stated “Similarly, original claims may lack written description when the claims define the invention in functional language specifying a desired result but the specification does not sufficiently describe how the function is performed or the result is achieved. For software, this can occur when the algorithm or steps/procedure for performing the computer function are not explained at all or are not explained in sufficient detail (simply restating the function recited in the claim is not necessarily sufficient). In other words, the algorithm or steps/procedure taken to perform the function must be described with sufficient detail so that one of ordinary skill in the art would understand how the inventor intended the function to be performed.” The computer-implemented functional limitations of Claim 5 simply claim a desired result and the algorithm or steps/procedure for performing the computer functions are not explained at all or are not explained in sufficient detail because the Specification simply restates the functions recited in the claims. MPEP2161.01(I), eight paragraph stated “When examining computer-implemented functional claims, examiners should determine whether the specification discloses the computer and the algorithm (e.g., the necessary steps and/or flowcharts) that perform the claimed function in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor possessed the claimed subject matter at the time of filing. An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary (5th ed., 2002). Applicant may "express that algorithm in any understandable terms including as a mathematical formula, in prose, or as a flow chart, or in any other manner that provides sufficient structure." Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323, 1340 (Fed. Cir. 2008) (internal citation omitted). It is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015) (reversing and remanding the district court’s grant of summary judgment of invalidity for lack of adequate written description where there were genuine issues of material fact regarding "whether the specification show[ed] possession by the inventor of how accessing disparate databases is achieved"). If the specification does not provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention a rejection under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, for lack of written description must be made.” For all the reasons discussed above, the original disclosure failed to provide a description of the computer and algorithm(s) in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the claimed invention. By failing to provide a description of the computer and algorithm(s) in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the full scope of the claimed invention Applicant is trying to claim any and all means for achieving the claimed invention. Claims 9 and 10 depend from Claim 5 and are rejected for the same reasons.
Independent Claims 1, 5, and 7 and dependent Claims 2, 3, 8 – 10, 13, 14, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Independent Claims 1 and 7 and dependent Claims 2, 3, 8, 13, 14, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Independent Claim 1, ll. 4 - 5 and independent Claim 7, ll. 4 - 5 recites “a memory configured to store instructions; and processing circuitry coupled to the memory and configured to execute the instructions to:”. Independent Claims 1 and 7, ll. 5 - 18 recites “processing circuitry coupled to the memory and configured to execute the instructions to: generate a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently, transmit the first orbit control command to the plurality of satellites, after the space object has passed through the passage region, generate a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes, and transmit the second orbit control command to the plurality of satellites”. Independent Claims 1 and 7, ll. 19 - 26 recites “the processing circuitry generates the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order, and”. Independent Claims 1 and 7, ll. 27 - 34 recites “the processing circuitry generates the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. Dependent Claims 2 and 3 recites “…processing circuitry generates the first orbit control command to form the satellite constellation” performing various computer implemented functions. MPEP2164.06(c), third paragraph stated “In a typical computer application, system components are often represented in a "block diagram" format, i.e., a group of hollow rectangles representing the elements of the system, functionally labeled, and interconnected by lines. Such block diagram computer cases may be categorized into (A) systems that include but are more comprehensive than a computer and (B) systems wherein the block elements are totally within the confines of a computer.”. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Figs. 5, 7, and 8 just show a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “910: Processor”. In Figs. 5, 7, and 8 one-way or two-way arrows lines connect the “910: Processor” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 16 just shows a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “909: Electronic Circuit”. In Fig. 16 one-way or two-way arrows lines connect the “909: Electronic Circuit” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 26 just shows a rectangle labeled “83 – control unit” inside another rectangle labeled “910: Processor”. In Fig. 26 one-way or two-way arrows lines connect the “910: Processor” rectangle to three other rectangles and the assembly of rectangles form a “802: Server” which is connected to a rectangle labeled “801: Database”. The assembly of the “802: Server” rectangle with the “801: Database” rectangle formed an “800: OADR (Open Architecture Data Repository)” which communicated to a “40: management business device” that contained seven rectangles representing different “business devices”. In Figs. 5 and 8 a rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “910: Processor” rectangle. In Fig. 7 a dashed rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “910: Processor” rectangle and two solid rectangles labeled “510 Orbit Control Command Generation Unit” and labeled “520: Analytical Prediction Unit” are inside the dashed rectangle labeled “11 Satellite Constellation Forming Unit”. In Fig. 16 a rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “909: Electronic Circuit” rectangle. In Fig. 26 a rectangle labeled “83 Control Unit” is inside the “910: Processor” rectangle. In Figs. 5, 7, 8, 16, and 26 the rectangle labeled “910: Processor” or “909: Electronic Circuit” has a line connected to a rectangle labeled “950: Communication Device” which transmits an electronic signal “55: orbit control command”, i.e., radio waves or microwaves, from the “700: Ground Facility” to a “30: satellite” orbiting the planet Earth or sends an electronic signal to a “40: management business device” that contained seven rectangles representing different “business devices”, as shown in Fig. 26. Consequently, Applicant’s figures are categorized as “(A) systems that include but are more comprehensive than a computer”. In other words, Applicant’s claimed invention involves systems which include a computer as well as other system hardware and/or software components.
When determining whether “undue experimentation” would have been needed to make and use the claimed invention the following factors, MPEP 2164.01(a), are considered: (A) the breadth of the claims – applicant claims (Claim 1) a satellite constellation forming system and (Claim 7) a ground facility included in a satellite constellation forming system where both satellite constellation forming systems include “processing circuitry” (which could be all hardware or a combination of hardware and software) to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, and after the space object has passed through the passage region, restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes.; (B) the nature of the invention – For the reasons discussed above the claims are interpreted as MPEP 2164.06(c)(I) Block Elements More Comprehensive than a Computer, i.e., a system which includes a computer as well as other system hardware and/or software components; (C) The state of the prior art – Schilling (11,104,456) teaches, in Figs. 1 – 12 and Col. 2, ll. 30 – 60, a constellation of satellites (10) where each satellite had an onboard collision avoidance system so that each individual satellite would have automatically maneuvered itself to avoid a collision with another space object without contacting a ground station. Meek (2018/0022474A1) teaches, in Fig. 1A, Para. [0032], and Para. [0073], a satellite constellation (100) having a plurality of orbital planes (104 - at least seventeen orbital planes shown in Fig. 1A) in each of which a plurality of satellites (102) fly at a same average orbital altitude. Meek teaches, in Para. [0032], "All satellites 102 within a given plane are flown at the same altitude”. Meek teaches, in Para. [0073], "prior-art constellations wherein all of the satellites are at the same altitude". Schilling and Meek do not teach the details of Applicant’s claimed invention.; (D) The level of one of ordinary skill - MPEP 2164.06(c), second paragraph stated “In computer applications, it is not unusual for the claimed invention to involve two areas of prior art or more than one technology, e.g., an appropriately programmed computer and an area of application of said computer. White Consol. Indus. v. Vega Servo-Control, Inc., 214 USPQ 796, 821 (S.D.Mich. 1982). In regard to the "skilled in the art" standard, in cases involving both the art of computer programming, and another technology, the examiner must recognize that the knowledge of persons skilled in both technologies is the appropriate criteria for determining sufficiency. See In re Naquin, 398 F.2d 863, 158 USPQ 317 (CCPA 1968); In re Brown, 477 F.2d 946, 177 USPQ 691 (CCPA 1973); White Consol. Indus., 214 USPQ at 822, aff’d on related grounds, 713 F.2d 788, 218 USPQ 961 (Fed. Cir. 1983). Therefore a person of ordinary skill in the art would be a computer systems engineer with at least a Masters degree in Computer Systems Engineering and at least 5 years of relevant work experience designing and implementing complex IT infrastructures by combining hardware, software, and networking components. Computer systems engineers design, integrate, and maintains complex IT infrastructures by combining hardware, software, and networking components. They analyze user needs to build stable, secure systems, often working on cloud infrastructure, servers, and embedded technologies. Computer systems engineers bridge the gap between low-level hardware design and high-level software applications like collision avoidance programs for a constellation of satellites.; (E) the level of predictability in the art – low predictability per the sections of MPEP 2164.06(C)(I) and (C)(II) discussed below; (F) the amount of direction provided by the inventor – Applicant's disclosure does not teach how to make or use the invention because the Specification merely repeats the claim language without any additional details. The Specification failed to include any electronic circuit diagrams, programmed steps, algorithms (equations) or procedures that the computer processor performs to produce the claimed functions that required precisely coordinating with other complex assemblages. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the calculations performed by each box or how each box was precisely coordinating with other “black boxes”.
The original Specification Para. [0035] disclosed “The processing circuit may be dedicated hardware, or may be a processor that executes programs stored in a memory. In the processing circuit, some functions may be realized by hardware, and the remaining functions may be realized by software or firmware. That is, the processing circuit can be realized by hardware, software, firmware, or a combination of these.” The original disclosure failed to provide a disclosure of the computer and algorithm, i.e., software, in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the language of the claims without any additional details. As discussed above, Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Para. [0055] disclosed “The satellite constellation forming system 600 includes an electronic circuit 909 in place of the processor 910. The electronic circuit 909 is a dedicated electronic circuit that realizes the functions of the satellite constellation forming system 600. Specifically, the electronic circuit 909 is a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, a logic IC, a GA, an ASIC, or an FPGA. GA is an abbreviation for Gate Array. The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” Para. [0056] disclosed “Each of the processor and the electronic circuit is also called processing circuitry. That is, the functions of the satellite constellation forming system 600 are realized by the processing circuitry.” The original disclosure keeps repeating that the processing circuitry could be all hardware or a combination of hardware and software. Specification Para. [0055] disclosed that the claimed processing circuitry could be every type of computing device known in the art. The claimed processing circuitry could be a dedicated, i.e., custom designed to only perform the claimed functional limitations, electronic circuit [interpreted as a printed circuit board (PCB) populated with electronic components] which could be a single circuit (single PCB) or a composite circuit (two or more PCBs). The claimed processing circuitry could be a programmed processor or a parallel-programmed processor which is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing where software algorithms perform the functional limitations. As well known in the prior art, generic computers with generic CPU(s) were capable of running a wide variety of different software programs to perform a near infinite number of computer functions. The claimed processing circuitry could be “hard-wired” devices that do not run on software because the programming was burned into or designed into the device. A logic IC (Integrated Circuit) were semiconductor devices that perform boolean logic operations (AND, OR, NOT, etc.) on digital input signals. A gate array (GA) was a semi-custom ASIC which was an “Application-Specific Integrated Circuits”. As implied by the name, “Application-Specific Integrated Circuits” (ASIC) were integrated circuits customized for a specific task and the specific task cannot be changed once manufactured. ASIC were basically dedicated electronic circuits on a standard 18” x 24” PCB shrunk down to fit on a silicon chip smaller than a human thumbnail. Gate arrays (GA)s and “Application-Specific Integrated Circuits” (ASIC)s did not run on software because the programming was designed into the device, i.e., “hard-wired” to only run a single program. FPGAs (Field-Programmable Gate Arrays) were integrated circuits, i.e., a single computer chip, that were reconfigurable after manufacturing, offering flexibility, rapid prototyping, and faster time-to-market for low-to-medium volumes, though they are less power-efficient. FPGAs were manufactured with basic logic circuit and memory on a single computer chip. After purchasing a FPGA, a user would “flash”, i.e., burn-into, their specific program into the FPGA’s on chip memory so that the FPGA would only run that specific program until the FPGA’s on chip memory was erased and a new program was “flashed”, i.e., burned-into, the FPGA’s on chip memory.
If the claimed processing circuitry is broadly interpreted as dedicated, i.e., custom designed, electronic circuit board(s) with one or more logic ICs, gate arrays (GA), “Application-Specific Integrated Circuits” (ASIC), and/or FPGAs (Field-Programmable Gate Arrays) populating the electronic circuit board(s), then Applicant’s disclosure failed to sufficiently describe details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms, to show enablement of the full scope of the claimed subject matter at the time of filing. In fact, Applicant’s original disclosure failed to describe any details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms. Therefore, it is impossible for Applicant’s original disclosure to show enablement of the full scope of the claimed subject matter at the time of filing. MPEP 2164.06(a)(I), second paragraph stated “A disclosure of an electrical circuit apparatus, depicted in the drawings by block diagrams with functional labels, was held to be nonenabling in In re Gunn, 537 F.2d 1123, 1129, 190 USPQ 402, 406 (CCPA 1976), where there was no indication in the specification as to whether the parts represented by boxes were "off the shelf" or must be specifically constructed or modified for applicant’s system. Also there were no details in the specification of how the parts should be interconnected, timed and controlled so as to obtain the specific operations desired by the applicant.” The Board in In re Gunn focused on the fact that the drawings were "block diagrams, i.e., a group of rectangles representing the elements of the system, functionally labeled and interconnected by lines." 442 F.2d at 991, 169 USPQ at 727. The specification did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. The Board further questioned whether the selection and assembly of the required components could be carried out routinely by persons of ordinary skill in the art. Similarly in this case, Applicant’s original disclosure did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. There was no indication in Applicant’s Specification as to whether the parts represented by the “black boxes” were "off the shelf" or must be specifically constructed or modified for applicant’s system (Para. [0035] disclosed “The processing circuit may be dedicated hardware,…”, i.e., specifically designed and constructed for Applicant’s invention.). Also there were no details in Applicant’s Specification of how the parts should be interconnected, timed and controlled so as to obtain the full scope of the specific operations desired by Applicant’s claimed invention. Therefore, similar to In re Gunn, Applicant’s disclosure has failed to apprise one of ordinary skill how to make and use the full scope of the claimed invention.
If the claimed processing circuitry is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing, then Applicant’s disclosure would have to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure enabled the full scope of the claimed invention at the time of filing. However, Applicant’s disclosure failed to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure FAILED TO ENABLE the full scope of the claimed invention at the time of filing. Independent Claims 1 and 7, ll. 5 - 18 recites “processing circuitry coupled to the memory and configured to execute the instructions to: generate a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently, transmit the first orbit control command to the plurality of satellites, after the space object has passed through the passage region, generate a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes, and transmit the second orbit control command to the plurality of satellites”. Independent Claims 1 and 7, ll. 19 - 26 recites “the processing circuitry generates the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order, and”. Independent Claims 1 and 7, ll. 27 - 34 recites “the processing circuitry generates the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. Dependent Claims 2 and 3 recites “…processing circuitry generates the first orbit control command to form the satellite constellation” performing various computer implemented functions. The original disclosure failed to provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the original disclosure enabled the full scope of the claimed invention at the time of filing. The original Specification merely repeats the claim language of the claims. Fig. 9 is a flowchart of the satellite constellation forming process (S100) where step (S102) was labeled “Form Passage Region”. Specification Paras. [0043] – [0045] basically repeat the claim limitations of Claims 1 and 7, ll. 5 - 13 and Claims 1 and 7, ll. 19 - 26 without any further details. Fig. 9 step (S104) was labeled “Restore to Previous State”. Specification Paras. [0052] – [0053] basically repeat the claim limitations of Claims 1 and 7, ll. 14 - 18 and Claims 1 and 7, ll. 27 - 34 without any further details. MPEP 2164.06(c)(II), third paragraph stated “In programming applications where the software disclosure only includes a flowchart, as the complexity of functions and the generality of the individual components of the flowchart increase, the basis for challenging the sufficiency of such a flowchart becomes more reasonable because the likelihood of more than routine experimentation being required to generate a working program from such a flowchart also increases.” As stated above, the single flowchart rectangle (S102) labeled “Form Passage Region” encompassed a plurality of complex functions recited in Claims 1 and 7, ll. 5 - 13 and Claims 1 and 7, ll. 19 - 26. Similarly, the single flowchart rectangle (S104) labeled “Restore to Previous State” encompassed a plurality of complex functions recited in Claims 1 and 7, ll. 14 - 18 and Claims 1 and 7, ll. 27 - 34. Consequently, the basis for challenging the sufficiency of the Fig. 9 flowchart is reasonable because the likelihood of more than routine experimentation being required to generate a working program from such a basic flowchart is increased. MPEP 2164.06(a)(I), second paragraph stated “In In re Donohue, 550 F.2d 1269, 193 USPQ 136 (CCPA 1977), the lack of enablement was caused by lack of information in the specification about a single block labeled "LOGIC" in the drawings. See also Union Pac. Res. Co. v. Chesapeake Energy Corp., 236 F.3d 684, 57 USPQ2d 1293 (Fed. Cir. 2001) (Claims directed to a method of determining the location of a horizontal borehole in the earth failed to comply with enablement requirement of 35 U.S.C. 112 because certain computer programming details used to perform claimed method were not disclosed in the specification, and the record showed that a person of skill in art would not understand how to "compare" or "rescale" data as recited in the claims in order to perform the claimed method.” As discussed above, Applicant’s Specification failed to sufficiently describe the algorithms, i.e., programs, that detailed how Applicant performed the computer-implemented functional limitations packed into the two blocks labeled “S102 - Form Passage Region” and “S104 - Restore to Previous State” in Fig. 9 or packed into the rectangles labeled “910: Processor” in Figs. 5, 7, 8, and 26 or labeled “909: Electronic Circuit” in Fig. 16. Similarly, the computer programming details, i.e., algorithms, that Applicant used to perform the claimed computer-implemented functional limitations were not disclosed in Applicant’s Specification since the Specification only repeated the claim limitations which recited the results achieved by the invention. Therefore, similar to In re Donohue and Union Pac. Res. Co. v. Chesapeake Energy Corp, Applicant’s disclosure has failed to apprise one of ordinary skill how to make and use the full scope of the claimed invention.
Specification Para. [0054] disclosed “In this embodiment, the functions of the satellite constellation forming system 600 are realized by software. As a variation, the functions of the satellite constellation forming system 600 may be realized by hardware.” Para. [0055] disclosed “The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” The original disclosure keeps repeating that the processing circuitry could be all hardware, all software, or a combination of hardware and software without disclosing any details. MPEP 2164.06(a)(I), fourth paragraph stated “An adequate disclosure of a device may require details of how complex components are constructed and perform the desired function. The claim before the court in In re Scarbrough, 500 F.2d 560, 182 USPQ 298 (CCPA 1974), was directed to a system which comprised several component parts (e.g., computer, timing and control mechanism, A/D converter, etc.) only by generic name and overall ultimate function. The court concluded that there was not an enabling disclosure because the specification did not describe how "complex elements known to perform broadly recited functions in different systems would be adaptable for use in Appellant’s particular system with only a reasonable amount of experimentation" and that "an unreasonable amount of work would be required to arrive at the detailed relationships appellant says that he has solved." 500 F.2d at 566, 182 USPQ at 302”. As discussed above, Applicant’s satellite constellation forming system comprised several component parts (e.g., computer/processor/electronic circuit, input interface, output interface, memory, auxiliary storage device, ground-based communication device, satellite-based communication device, etc.) only by generic name and overall ultimate function. Applicant’s disclosure did not describe how "complex elements known to perform broadly recited functions in different systems would be adaptable for use in Appellant’s particular system with only a reasonable amount of experimentation". Applicant’s disclosure failed to describe Applicant’s software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure FAILED TO ENABLE the full scope of the claimed invention at the time of filing. MPEP 2164.06(c)(I), second paragraph stated “…where the specification provides in a block diagram disclosure of a complex system that includes a microprocessor and other system components controlled by the microprocessor, a mere reference to a commercially available microprocessor, without any description of the precise operations to be performed by the microprocessor, fails to disclose how such a microprocessor would be properly programmed to (1) either perform any required calculations or (2) coordinate the other system components in the proper timed sequence to perform the functions disclosed and claimed. If a particular program is disclosed in such a system, the program should be carefully reviewed to ensure that its scope is commensurate with the scope of the functions attributed to such a program in the claims. In re Brown, 477 F.2d at 951, 177 USPQ at 695. If (1) the disclosure fails to disclose any program and (2) more than routine experimentation would be required of one skilled in the art to generate such a program, the examiner clearly would have a reasonable basis for challenging the sufficiency of such a disclosure.”. Since Applicant failed to sufficiently disclose details of the hardware components that made up the complex satellite constellation forming system and failed to sufficiently disclose details of Applicant’s algorithm, i.e., software that performed the calculations and coordinated the timing and control of all the hardware components, Applicant’s disclosure failed to enable the full scope of the claimed invention which encompasses all known and unknown ways of performing the claimed computer-implemented functions.; (G) the existence of working examples - applicant has not stated whether or not a working example exists; and (H) the quantity of experimentation needed to make or use the invention based on the content of the disclosure – it has been held that “an adequate disclosure of a device may require details of how complex components are constructed and perform the desired function", In re Scarbrough, 500 F.2d 560, 182 USPQ 298 (CCPA 1974), MPEP 2164.06(a)(I)]. In In re Ghiron, 442 F.2d 985, 991-92, 169 USPQ 723, 727-28 (CCPA 1971), functional "block diagrams" were insufficient to enable a person skilled in the art to practice the claimed invention with only a reasonable degree of experimentation because the claimed invention required a "modification to prior art overlap computers," and because "many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages. … It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work. …", MPEP 2164.06(II). Even if a potential infringer could, with undue experimentation, design a complex IT system and write a program to run on said complex IT system to perform the claimed computer-implemented functions of Claims 1 and 7, it would be impossible to tell if the potential infringer’s IT system and program would avoid infringing on Applicant’s claimed invention, i.e., the computer hardware, the computer software, or the combination of computer hardware and computer software, because Applicant’s disclosure failed to disclose any details of how the computer-implemented functions of Claims 1 and 7 are performed by Applicant. Claims 2, 3, 8, 13, and 14 depend from Claim 1 and are rejected for the same reasons. Claim 18 depends from Claim 7 and is rejected for the same reasons.
Independent Claim 5 and dependent Claims 9 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Independent Claim 5, ll. 5 - 12 recites “generating via processing circuitry configured to execute instructions stored in a memory, a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently,”. Independent Claim 5, ll. 13 recites “transmitting the first orbit control command to the plurality of satellites”. Independent Claim 5, ll. 14 - 17 recites “after the space object has passed through the passage region, generating, via the processing circuitry, a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes,”. Independent Claim 5, l. 18 recites “transmitting the second orbit control command to the plurality of satellites”. Independent Claim 5, ll. 20 - 27 recites “generating, via the processing circuitry, the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order, such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order”. Independent Claim 5, ll. 28 - 35 recites “generating, via the processing circuitry, the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. Therefore, Claims 5, 9, and 10 are interpreted as method claims with computer-implemented functional claim limitations. MPEP2164.06(c)(II), second paragraph stated “Regardless of whether a disclosure involves block elements more comprehensive than a computer or block elements totally within the confines of a computer, USPTO personnel, when analyzing method claims, must recognize that the specification must be adequate to teach how to practice the claimed method. If such practice requires a particular apparatus, then the application must provide a sufficient disclosure of that apparatus if such is not already available. See In re Ghiron, 442 F.2d 985, 991, 169 USPQ 723, 727 (CCPA 1971) and In re Gunn, 537 F.2d 1123, 1128, 190 USPQ 402, 406 (CCPA 1976)”. MPEP2164.06(c), third paragraph stated “In a typical computer application, system components are often represented in a "block diagram" format, i.e., a group of hollow rectangles representing the elements of the system, functionally labeled, and interconnected by lines. Such block diagram computer cases may be categorized into (A) systems that include but are more comprehensive than a computer and (B) systems wherein the block elements are totally within the confines of a computer.”. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Figs. 5, 7, and 8 just show a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “910: Processor”. In Figs. 5, 7, and 8 one-way or two-way arrows lines connect the “910: Processor” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 16 just shows a rectangle labeled “11 - satellite constellation forming unit” inside another rectangle labeled “909: Electronic Circuit”. In Fig. 16 one-way or two-way arrows lines connect the “909: Electronic Circuit” rectangle to five other rectangles and the assembly of rectangles form a “700: Ground Facility”. Fig. 26 just shows a rectangle labeled “83 – control unit” inside another rectangle labeled “910: Processor”. In Fig. 26 one-way or two-way arrows lines connect the “910: Processor” rectangle to three other rectangles and the assembly of rectangles form a “802: Server” which is connected to a rectangle labeled “801: Database”. The assembly of the “802: Server” rectangle with the “801: Database” rectangle formed an “800: OADR (Open Architecture Data Repository)” which communicated to a “40: management business device” that contained seven rectangles representing different “business devices”. In Figs. 5 and 8 a rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “910: Processor” rectangle. In Fig. 7 a dashed rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “910: Processor” rectangle and two solid rectangles labeled “510 Orbit Control Command Generation Unit” and labeled “520: Analytical Prediction Unit” are inside the dashed rectangle labeled “11 Satellite Constellation Forming Unit”. In Fig. 16 a rectangle labeled “11 Satellite Constellation Forming Unit” is inside the “909: Electronic Circuit” rectangle. In Fig. 26 a rectangle labeled “83 Control Unit” is inside the “910: Processor” rectangle. In Figs. 5, 7, 8, 16, and 26 the rectangle labeled “910: Processor” or “909: Electronic Circuit” has a line connected to a rectangle labeled “950: Communication Device” which transmits an electronic signal “55: orbit control command”, i.e., radio waves or microwaves, from the “700: Ground Facility” to a “30: satellite” orbiting the planet Earth or sends an electronic signal to a “40: management business device” that contained seven rectangles representing different “business devices”, as shown in Fig. 26. Consequently, Applicant’s figures are categorized as “(A) systems that include but are more comprehensive than a computer”. In other words, Applicant’s claimed invention involves systems which include a computer as well as other system hardware and/or software components.
When determining whether “undue experimentation” would have been needed to make and use the claimed invention the following factors, MPEP 2164.01(a), are considered: (A) the breadth of the claims – applicant claims (Claim 5) a satellite constellation forming method comprising forming a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, and after the space object has passed through the passage region, restoring the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes; (B) the nature of the invention – For the reasons discussed above the claims are interpreted as MPEP 2164.06(c)(I) Block Elements More Comprehensive than a Computer, i.e., a system which includes a computer as well as other system hardware and/or software components; (C) The state of the prior art – Schilling (11,104,456) teaches, in Figs. 1 – 12 and Col. 2, ll. 30 – 60, a constellation of satellites (10) where each satellite had an onboard collision avoidance system so that each individual satellite would have automatically maneuvered itself to avoid a collision with another space object without contacting a ground station. Meek (2018/0022474A1) teaches, in Fig. 1A, Para. [0032], and Para. [0073], a satellite constellation (100) having a plurality of orbital planes (104 - at least seventeen orbital planes shown in Fig. 1A) in each of which a plurality of satellites (102) fly at a same average orbital altitude. Meek teaches, in Para. [0032], "All satellites 102 within a given plane are flown at the same altitude”. Meek teaches, in Para. [0073], "prior-art constellations wherein all of the satellites are at the same altitude". Schilling and Meek do not teach the details of Applicant’s claimed invention.; (D) The level of one of ordinary skill - MPEP 2164.06(c), second paragraph stated “In computer applications, it is not unusual for the claimed invention to involve two areas of prior art or more than one technology, e.g., an appropriately programmed computer and an area of application of said computer. White Consol. Indus. v. Vega Servo-Control, Inc., 214 USPQ 796, 821 (S.D.Mich. 1982). In regard to the "skilled in the art" standard, in cases involving both the art of computer programming, and another technology, the examiner must recognize that the knowledge of persons skilled in both technologies is the appropriate criteria for determining sufficiency. See In re Naquin, 398 F.2d 863, 158 USPQ 317 (CCPA 1968); In re Brown, 477 F.2d 946, 177 USPQ 691 (CCPA 1973); White Consol. Indus., 214 USPQ at 822, aff’d on related grounds, 713 F.2d 788, 218 USPQ 961 (Fed. Cir. 1983). Therefore a person of ordinary skill in the art would be a computer systems engineer with at least a Masters degree in Computer Systems Engineering and at least 5 years of relevant work experience designing and implementing complex IT infrastructures by combining hardware, software, and networking components. Computer systems engineers design, integrate, and maintains complex IT infrastructures by combining hardware, software, and networking components. They analyze user needs to build stable, secure systems, often working on cloud infrastructure, servers, and embedded technologies. Computer systems engineers bridge the gap between low-level hardware design and high-level software applications like collision avoidance programs for a constellation of satellites.; (E) the level of predictability in the art – low predictability per the sections of MPEP 2164.06(C)(I) and (C)(II) discussed below; (F) the amount of direction provided by the inventor – Applicant's disclosure does not teach how to make or use the invention because the Specification merely repeats the claim language without any additional details. The Specification failed to include any electronic circuit diagrams, programmed steps, algorithms (equations) or procedures that the computer processor performs to produce the claimed functions that required precisely coordinating with other complex assemblages. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the calculations performed by each box or how each box was precisely coordinating with other “black boxes”.
The original Specification Para. [0035] disclosed “The processing circuit may be dedicated hardware, or may be a processor that executes programs stored in a memory. In the processing circuit, some functions may be realized by hardware, and the remaining functions may be realized by software or firmware. That is, the processing circuit can be realized by hardware, software, firmware, or a combination of these.” The original disclosure failed to provide a disclosure of the computer and algorithm, i.e., software, in sufficient detail to demonstrate to one of ordinary skill in the art that the inventor possessed the invention. The original Specification merely repeats the language of the claims without any additional details. As discussed above, Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the specific hardware of box/module and no descriptions of the algorithm, i.e., calculations performed by software of each box/module. Para. [0055] disclosed “The satellite constellation forming system 600 includes an electronic circuit 909 in place of the processor 910. The electronic circuit 909 is a dedicated electronic circuit that realizes the functions of the satellite constellation forming system 600. Specifically, the electronic circuit 909 is a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, a logic IC, a GA, an ASIC, or an FPGA. GA is an abbreviation for Gate Array. The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” Para. [0056] disclosed “Each of the processor and the electronic circuit is also called processing circuitry. That is, the functions of the satellite constellation forming system 600 are realized by the processing circuitry.” The original disclosure keeps repeating that the processing circuitry could be all hardware or a combination of hardware and software. Specification Para. [0055] disclosed that the claimed processing circuitry could be every type of computing device known in the art. The claimed processing circuitry could be a dedicated, i.e., custom designed to only perform the claimed functional limitations, electronic circuit [interpreted as a printed circuit board (PCB) populated with electronic components] which could be a single circuit (single PCB) or a composite circuit (two or more PCBs). The claimed processing circuitry could be a programmed processor or a parallel-programmed processor which is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing where software algorithms perform the functional limitations. As well known in the prior art, generic computers with generic CPU(s) were capable of running a wide variety of different software programs to perform a near infinite number of computer functions. The claimed processing circuitry could be “hard-wired” devices that do not run on software because the programming was burned into or designed into the device. A logic IC (Integrated Circuit) were semiconductor devices that perform boolean logic operations (AND, OR, NOT, etc.) on digital input signals. A gate array (GA) was a semi-custom ASIC which was an “Application-Specific Integrated Circuits”. As implied by the name, “Application-Specific Integrated Circuits” (ASIC) were integrated circuits customized for a specific task and the specific task cannot be changed once manufactured. ASIC were basically dedicated electronic circuits on a standard 18” x 24” PCB shrunk down to fit on a silicon chip smaller than a human thumbnail. Gate arrays (GA)s and “Application-Specific Integrated Circuits” (ASIC)s did not run on software because the programming was designed into the device, i.e., “hard-wired” to only run a single program. FPGAs (Field-Programmable Gate Arrays) were integrated circuits, i.e., a single computer chip, that were reconfigurable after manufacturing, offering flexibility, rapid prototyping, and faster time-to-market for low-to-medium volumes, though they are less power-efficient. FPGAs were manufactured with basic logic circuit and memory on a single computer chip. After purchasing a FPGA, a user would “flash”, i.e., burn-into, their specific program into the FPGA’s on chip memory so that the FPGA would only run that specific program until the FPGA’s on chip memory was erased and a new program was “flashed”, i.e., burned-into, the FPGA’s on chip memory.
If the claimed processing circuitry is broadly interpreted as dedicated, i.e., custom designed, electronic circuit board(s) with one or more logic ICs, gate arrays (GA), “Application-Specific Integrated Circuits” (ASIC), and/or FPGAs (Field-Programmable Gate Arrays) populating the electronic circuit board(s), then Applicant’s disclosure failed to sufficiently describe details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms, to show enablement of the full scope of the claimed subject matter at the time of filing. In fact, Applicant’s original disclosure failed to describe any details of Applicant’s dedicated/custom hardware and Applicant’s custom programming, i.e., algorithms. Therefore, it is impossible for Applicant’s original disclosure to show enablement of the full scope of the claimed subject matter at the time of filing. MPEP 2164.06(a)(I), second paragraph stated “A disclosure of an electrical circuit apparatus, depicted in the drawings by block diagrams with functional labels, was held to be nonenabling in In re Gunn, 537 F.2d 1123, 1129, 190 USPQ 402, 406 (CCPA 1976), where there was no indication in the specification as to whether the parts represented by boxes were "off the shelf" or must be specifically constructed or modified for applicant’s system. Also there were no details in the specification of how the parts should be interconnected, timed and controlled so as to obtain the specific operations desired by the applicant.” The Board in In re Gunn focused on the fact that the drawings were "block diagrams, i.e., a group of rectangles representing the elements of the system, functionally labeled and interconnected by lines." 442 F.2d at 991, 169 USPQ at 727. The specification did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. The Board further questioned whether the selection and assembly of the required components could be carried out routinely by persons of ordinary skill in the art. Similarly in this case, Applicant’s original disclosure did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. There was no indication in Applicant’s Specification as to whether the parts represented by the “black boxes” were "off the shelf" or must be specifically constructed or modified for applicant’s system (Para. [0035] disclosed “The processing circuit may be dedicated hardware,…”, i.e., specifically designed and constructed for Applicant’s invention.). Also there were no details in Applicant’s Specification of how the parts should be interconnected, timed and controlled so as to obtain the full scope of the specific operations desired by Applicant’s claimed invention. Therefore, similar to In re Gunn, Applicant’s disclosure has failed to apprise one of ordinary skill how to make and use the full scope of the claimed invention.
If the claimed processing circuitry is interpreted as a generic computer with either a single CPU (central processing unit) or two or more CPU (central processing unit) configured for parallel processing, then Applicant’s disclosure would have to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure enabled the full scope of the claimed invention at the time of filing. However, Applicant’s disclosure failed to describe the software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure FAILED TO ENABLE the full scope of the claimed invention at the time of filing. Independent Claim 5, ll. 5 - 12 recites “generating via processing circuitry configured to execute instructions stored in a memory, a first orbit control command to form a passage region for a space object to pass through at an orbital altitude of the satellite constellation by controlling a relative angle in an azimuth direction between orbital planes of the plurality of orbital planes before the space object passes through the orbital altitude of the satellite constellation from above the satellite constellation, the passage region being a region between orbital planes located adjacently of the plurality of orbital planes where there are no orbital planes between the orbital planes located adjacently or there are few intersection points between the orbital planes located adjacently,”. Independent Claim 5, ll. 13 recites “transmitting the first orbit control command to the plurality of satellites”. Independent Claim 5, ll. 14 - 17 recites “after the space object has passed through the passage region, generating, via the processing circuitry, a second orbit control command to restore the satellite constellation to a state before the passage region is formed by restoring the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes,”. Independent Claim 5, l. 18 recites “transmitting the second orbit control command to the plurality of satellites”. Independent Claim 5, ll. 20 - 27 recites “generating, via the processing circuitry, the first orbit control command to narrow the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to form the passage region by simultaneously changing orbital altitudes of all satellites in orbital planes located adjacently and maintaining a state in which average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are raised in a sequential order, such that the relative angle in the azimuth direction between orbital planes located adjacently is narrowed by a first azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes raised in the sequential order”. Independent Claim 5, ll. 28 - 35 recites “generating, via the processing circuitry, the second orbit control command to restore the relative angle in the azimuth direction between orbital planes of the plurality of orbital planes so as to restore the satellite constellation to a state before the passage region is formed by maintaining a state in which the average orbital altitudes of the orbital planes located adjacently arranged in the azimuth direction are lowered in a sequential order such that the relative angle in the azimuth direction between orbital planes located adjacently is restored by a second azimuth offset resulting from the orbital planes located adjacently being maintained at the average orbital altitudes lowered in the sequential order”. The original disclosure failed to provide a disclosure of the computer and algorithm in sufficient detail to demonstrate to one of ordinary skill in the art that the original disclosure enabled the full scope of the claimed invention at the time of filing. The original Specification merely repeats the claim language of the claims. Fig. 9 is a flowchart of the satellite constellation forming process (S100) where step (S102) was labeled “Form Passage Region”. Specification Paras. [0043] – [0045] basically repeat the claim limitations of Claim 5, ll. 5 - 13 and Claim 5, ll. 20 - 27 without any further details. Fig. 9 step (S104) was labeled “Restore to Previous State”. Specification Paras. [0052] – [0053] basically repeat the claim limitations of Claim 5, ll. 14 - 18 and Claim 5, ll. 28 - 35 without any further details. MPEP 2164.06(c)(II), third paragraph stated “In programming applications where the software disclosure only includes a flowchart, as the complexity of functions and the generality of the individual components of the flowchart increase, the basis for challenging the sufficiency of such a flowchart becomes more reasonable because the likelihood of more than routine experimentation being required to generate a working program from such a flowchart also increases.” As stated above, the single flowchart rectangle (S102) labeled “Form Passage Region” encompassed a plurality of complex functions recited in Claim 5, ll. 5 - 13 and Claim 5, ll. 20 - 27. Similarly, the single flowchart rectangle (S104) labeled “Restore to Previous State” encompassed a plurality of complex functions recited in Claim 5, ll. 14 - 18 and Claim 5, ll. 28 - 35. Consequently, the basis for challenging the sufficiency of the Fig. 9 flowchart is reasonable because the likelihood of more than routine experimentation being required to generate a working program from such a basic flowchart is increased. MPEP 2164.06(a)(I), second paragraph stated “In In re Donohue, 550 F.2d 1269, 193 USPQ 136 (CCPA 1977), the lack of enablement was caused by lack of information in the specification about a single block labeled "LOGIC" in the drawings. See also Union Pac. Res. Co. v. Chesapeake Energy Corp., 236 F.3d 684, 57 USPQ2d 1293 (Fed. Cir. 2001) (Claims directed to a method of determining the location of a horizontal borehole in the earth failed to comply with enablement requirement of 35 U.S.C. 112 because certain computer programming details used to perform claimed method were not disclosed in the specification, and the record showed that a person of skill in art would not understand how to "compare" or "rescale" data as recited in the claims in order to perform the claimed method.” As discussed above, Applicant’s Specification failed to sufficiently describe the algorithms, i.e., programs, that detailed how Applicant performed the computer-implemented functional limitations packed into the two blocks labeled “S102 - Form Passage Region” and “S104 - Restore to Previous State” in Fig. 9 or packed into the rectangles labeled “910: Processor” in Figs. 5, 7, 8, and 26 or labeled “909: Electronic Circuit” in Fig. 16. Similarly, the computer programming details, i.e., algorithms, that Applicant used to perform the claimed computer-implemented functional limitations were not disclosed in Applicant’s Specification since the Specification only repeated the claim limitations which recited the results achieved by the invention. Therefore, similar to In re Donohue and Union Pac. Res. Co. v. Chesapeake Energy Corp, Applicant’s disclosure has failed to apprise one of ordinary skill how to make and use the full scope of the claimed invention.
Specification Para. [0054] disclosed “In this embodiment, the functions of the satellite constellation forming system 600 are realized by software. As a variation, the functions of the satellite constellation forming system 600 may be realized by hardware.” Para. [0055] disclosed “The functions of the satellite constellation forming system 600 may be realized by one electronic circuit, or may be distributed among and realized by a plurality of electronic circuits. As another variation, some of the functions of the satellite constellation forming system 600 may be realized by the electronic circuit, and the rest of the functions may be realized by software.” The original disclosure keeps repeating that the processing circuitry could be all hardware, all software, or a combination of hardware and software without disclosing any details. MPEP 2164.06(a)(I), fourth paragraph stated “An adequate disclosure of a device may require details of how complex components are constructed and perform the desired function. The claim before the court in In re Scarbrough, 500 F.2d 560, 182 USPQ 298 (CCPA 1974), was directed to a system which comprised several component parts (e.g., computer, timing and control mechanism, A/D converter, etc.) only by generic name and overall ultimate function. The court concluded that there was not an enabling disclosure because the specification did not describe how "complex elements known to perform broadly recited functions in different systems would be adaptable for use in Appellant’s particular system with only a reasonable amount of experimentation" and that "an unreasonable amount of work would be required to arrive at the detailed relationships appellant says that he has solved." 500 F.2d at 566, 182 USPQ at 302”. As discussed above, Applicant’s satellite constellation forming system comprised several component parts (e.g., computer/processor/electronic circuit, input interface, output interface, memory, auxiliary storage device, ground-based communication device, satellite-based communication device, etc.) only by generic name and overall ultimate function. Applicant’s disclosure did not describe how "complex elements known to perform broadly recited functions in different systems would be adaptable for use in Appellant’s particular system with only a reasonable amount of experimentation". Applicant’s disclosure failed to describe Applicant’s software algorithms that performed all the claimed functional limitations in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the original disclosure FAILED TO ENABLE the full scope of the claimed invention at the time of filing. MPEP 2164.06(c)(I), second paragraph stated “…where the specification provides in a block diagram disclosure of a complex system that includes a microprocessor and other system components controlled by the microprocessor, a mere reference to a commercially available microprocessor, without any description of the precise operations to be performed by the microprocessor, fails to disclose how such a microprocessor would be properly programmed to (1) either perform any required calculations or (2) coordinate the other system components in the proper timed sequence to perform the functions disclosed and claimed. If a particular program is disclosed in such a system, the program should be carefully reviewed to ensure that its scope is commensurate with the scope of the functions attributed to such a program in the claims. In re Brown, 477 F.2d at 951, 177 USPQ at 695. If (1) the disclosure fails to disclose any program and (2) more than routine experimentation would be required of one skilled in the art to generate such a program, the examiner clearly would have a reasonable basis for challenging the sufficiency of such a disclosure.”. Since Applicant failed to sufficiently disclose details of the hardware components that made up the complex satellite constellation forming system and failed to sufficiently disclose details of Applicant’s algorithm, i.e., software that performed the calculations and coordinated the timing and control of all the hardware components, Applicant’s disclosure failed to enable the full scope of the claimed invention which encompasses all known and unknown ways of performing the claimed computer-implemented functions.; (G) the existence of working examples - applicant has not stated whether or not a working example exists; and (H) the quantity of experimentation needed to make or use the invention based on the content of the disclosure – it has been held that “an adequate disclosure of a device may require details of how complex components are constructed and perform the desired function", In re Scarbrough, 500 F.2d 560, 182 USPQ 298 (CCPA 1974), MPEP 2164.06(a)(I)]. In In re Ghiron, 442 F.2d 985, 991-92, 169 USPQ 723, 727-28 (CCPA 1971), functional "block diagrams" were insufficient to enable a person skilled in the art to practice the claimed invention with only a reasonable degree of experimentation because the claimed invention required a "modification to prior art overlap computers," and because "many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages. … It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work. …", MPEP 2164.06(II). Even if a potential infringer could, with undue experimentation, design a complex IT system and write a program to run on said complex IT system to perform the claimed computer-implemented functions of Claim 5, it would be impossible to tell if the potential infringer’s IT system and program would avoid infringing on Applicant’s claimed invention, i.e., the computer hardware, the computer software, or the combination of computer hardware and computer software, because Applicant’s disclosure failed to disclose any details of how the computer-implemented functions of Claim 5 are performed by Applicant. Claims 9 and 10 depend from Claim 5 and are rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Arguments
Applicant's arguments filed 06/04/2026 have been fully considered but they are not persuasive.
Applicant argues on Pgs. 10 – 13 that the original disclosure described the claimed algorithm in three forms recognized by Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323, 1340, 86 USPQ2d 1609, 1623 (Fed. Cir. 2008). These arguments are not persuasive as discussed in the 35 USC §112(a) rejections above which cites other caselaw in addition to Finisar Corp. On Pg. 12, second paragraph Applicant cites Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 19 USPQ2d 1111 (Fed. Cir. 1991) which wasn’t cited in the Office Action mailed on 04/01/2026. On Pg. 12, second paragraph continuing on to Pg. 13 Applicant further cites Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 94 USPQ2d 1161 (Fed. Cir. 2010) cited by Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 682. 114 USPQ2d 1349, 1356 and argues that the caselaw is misplaced. Examiner disagrees. The Patent Trial and Appeal Board is the proper venue to decide competing arguments over caselaw. Examiner maintains that all the 35 USC §112(a) rejections citing various caselaw with analysis are proper.
Applicant argues on Pgs. 13, last paragraph continuing on to Pg. 17 that eight Wands factors were satisfied. Examiner disagrees and maintains the 35 USC §112(a) lack of enablement rejections. For Factor (A) Applicant argues that the amendments of independent Claims 1, 5, and 7 narrowed the breadth of the claimed invention and thus overcame the Office Action's full-scope concern. Examiner disagrees because the Wands analysis must consider all the evidence related to each of the Wands factors, and any conclusion of nonenablement must be based on the evidence as a whole. For Factor (B) Applicant argues that the claimed invention is “directed to a satellite-constellation control procedure rather than to a generic information-technology architecture”. This is not persuasive the claimed invention requires a complex IT system which includes a computer as well as other system hardware and/or software components that transmit and receive communication signals between a constellation of satellites constantly moving a very high speed in orbit over planet Earth. As discussed above, Applicant’s satellite constellation forming system comprised several component parts (e.g., computer/processor/electronic circuit, input interface, output interface, memory, auxiliary storage device, ground-based communication device, satellite-based communication device, etc.) only by generic name and overall ultimate function. Applicant’s disclosure did not describe how "complex elements known to perform broadly recited functions in different systems would be adaptable for use in Appellant’s particular system with only a reasonable amount of experimentation". For Factor (C) Applicant argues that “The hardware components recited in the published specification - processor 910, memory 921, auxiliary storage device 922, input interface 930, output interface 940, and communication device 950 (paragraph [0091]) - are, for example, computing components that a person of ordinary skill in the art would be able to assemble without further direction from the specification.” Examiner disagrees because it was held in In re Ghiron, 442 F.2d 985, 991-92, 169 USPQ 723, 727-28 (CCPA 1971), functional "block diagrams" were insufficient to enable a person skilled in the art to practice the claimed invention with only a reasonable degree of experimentation because the claimed invention required a "modification to prior art overlap computers," and because "many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages. … It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work. …", MPEP 2164.06(II). For Factor (D) Applicant argues that a POSITA “…is fully equipped to implement off-the-shelf conventional computing components in conformance with a specification that identifies them by name and describes their interconnection.” This is not persuasive because the arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) (“An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness.”); MPEP 2145. Applicant’s conclusory attorney arguments are not supported by any factual evidence in the record. Furthermore, it was held in In re Ghiron, 442 F.2d 985, 991-92, 169 USPQ 723, 727-28 (CCPA 1971), functional "block diagrams" were insufficient to enable a person skilled in the art to practice the claimed invention with only a reasonable degree of experimentation because the claimed invention required a "modification to prior art overlap computers," and because "many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages. … It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work. …", MPEP 2164.06(II). For Factor (E) Applicant argues that orbital mechanics are predictable therefore “The Office Action's assertion of "low predictability" is unsupported”. This is not persuasive because the "low predictability" analysis is based on the entire claimed invention which encompassed more than just calculations of orbital mechanics. For Factor (F) Applicant argues that Figs. 9 – 15 and 17 – 22 and Paragraphs [0091] – [0096], [0103] – [0124] and [0147] provide sufficient descriptions. This is not persuasive because Applicant's disclosure does not teach how to make or use the invention because the Specification merely repeats the claim language without any additional details. The Specification failed to include any electronic circuit diagrams, programmed steps, algorithms (equations) or procedures that the computer processor performs to produce the claimed functions that required precisely coordinating with other complex assemblages. Figs. 5, 7, 8, 16, and 26 are block diagrams with a bunch of labeled boxes/modules where each box/module was essentially a “black box” where there are no descriptions of the calculations performed by each box or how each box was precisely coordinating with other “black boxes”. For Factor (G) Applicant argues that “The published specification provides at least two worked examples (the polar-orbit embodiment of paragraphs [0110]-[0118] with Figures 10-15, and the non-polar embodiment of paragraphs [0140]-[0148] with Figures 17-22).” This is not persuasive because the cited figures and paragraphs describe prophetic examples. Prophetic examples describe an embodiment of the invention based on predicted results rather than work actually conducted or results actually achieved. For Factor (H) Applicant argues that “the quantity of experimentation needed for a person of ordinary skill in the art to practice the claimed subject matter is, at most, routine”. This is not persuasive because the arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) (“An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness.”); MPEP 2145. Applicant’s conclusory attorney arguments are not supported by any factual evidence in the record. Furthermore, it was held in In re Ghiron, 442 F.2d 985, 991-92, 169 USPQ 723, 727-28 (CCPA 1971), functional "block diagrams" were insufficient to enable a person skilled in the art to practice the claimed invention with only a reasonable degree of experimentation because the claimed invention required a "modification to prior art overlap computers," and because "many of the components which appellants illustrate as rectangles in their drawing necessarily are themselves complex assemblages. … It is common knowledge that many months or years elapse from the announcement of a new computer by a manufacturer before the first prototype is available. This does not bespeak of a routine operation but of extensive experimentation and development work. …", MPEP 2164.06(II). Finally, Applicant argues “The Office Action's reliance on In re Gunn, 537 F.2d 1123 (CCPA 1976), In re Donohue, 550 F.2d 1269 (CCPA 1977), and In re Scarbrough, 500 F.2d 560 (CCPA 1974), is also misplaced” because “the published specification identifies the ground facility components by specific reference numerals and describes their function (paragraphs [0091]- [0096]), describes their interconnection ("[t]he processor 910 is connected with other hardware components via signal lines and controls these other hardware components" at paragraph [0091]), and identifies specific implementing structures for the processing circuitry (paragraphs [0085]-[0088], [0129]-[0132], identifying the processing circuitry as a processor with memory, or alternatively as one or more of a single circuit, composite circuit, programmed processor, parallel-programmed processor, logic IC, gate array, ASIC, or FPGA)”. This is not persuasive because the original disclosure failed to describe specific off the shelf components. Applicant failed to cite factual evidence that the ground facility can be bought “off the shelf” at the time of Applicant’s invention. MPEP 2164.06(a)(I), second paragraph stated “A disclosure of an electrical circuit apparatus, depicted in the drawings by block diagrams with functional labels, was held to be nonenabling in In re Gunn, 537 F.2d 1123, 1129, 190 USPQ 402, 406 (CCPA 1976), where there was no indication in the specification as to whether the parts represented by boxes were "off the shelf" or must be specifically constructed or modified for applicant’s system. Also there were no details in the specification of how the parts should be interconnected, timed and controlled so as to obtain the specific operations desired by the applicant.” The Board in In re Gunn focused on the fact that the drawings were "block diagrams, i.e., a group of rectangles representing the elements of the system, functionally labeled and interconnected by lines." 442 F.2d at 991, 169 USPQ at 727. The specification did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. The Board further questioned whether the selection and assembly of the required components could be carried out routinely by persons of ordinary skill in the art. Similarly in this case, Applicant’s original disclosure did not particularly identify each of the elements represented by the blocks or the relationship therebetween, nor did it specify particular apparatus intended to carry out each function. There was no indication in Applicant’s Specification as to whether the parts represented by the “black boxes” were "off the shelf" or must be specifically constructed or modified for applicant’s system (Para. [0035] disclosed “The processing circuit may be dedicated hardware,…”, i.e., specifically designed and constructed for Applicant’s invention.). Also there were no details in Applicant’s Specification of how the parts should be interconnected, timed and controlled so as to obtain the full scope of the specific operations desired by Applicant’s claimed invention. Therefore, similar to In re Gunn, Applicant’s disclosure has failed to apprise one of ordinary skill how to make and use the full scope of the claimed invention. The rejections are maintained.
Correspondence
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/LORNE E MEADE/Primary Examiner, Art Unit 3741
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