Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Non-Final office action mailed on 10/1/2025, the applicant has filed a response on 12/17/2025, amending claims 1, 3-11 and 13-20. Claims 2 and 12 have been cancelled. Claim 21 has been added. Claims 1, 3-11 and 13-21 are pending in this application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-7, 11 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2017/0061917).
Regarding claim 1, Chen discloses a pixel driving circuit (see Fig. 2), comprising:
a pixel electrode (see pixel electrode in annotated Fig. 2 reproduced below);
a charging module electrically connected to a data line, a scanning line, and the pixel electrode, wherein the charging module is configured to write a signal of the data line to the pixel electrode under the control of a signal of the scanning line (para[0033]; para[0035]; see e.g. the claimed charging module comprising transistor T2 connected to a data line 2, gate line 1(N) and the pixel electrode, and configured to write a signal of the data line 2 to the pixel electrode under the control of the gate line 1(N), as shown in annotated Fig. 2 reproduced below); and
a discharging module electrically connected to a signal control line, a discharge electrode, and the pixel electrode, wherein the discharging module is configured to connect the pixel electrode to the discharging electrode under the control of a signal of the signal control line (para[0028]-para[0031]; para[0035]-para[0036]; see e.g. discharge module 3 comprising transistor T1 connected to gate line 1(N-1)(claimed signal control line), a discharge electrode and the pixel electrode, and configured to connect the pixel electrode to the discharge electrode under the control of a signal from gate line 1(N-1), as shown in annotated Fig. 2 reproduced below)[[.]];
wherein the pixel driving circuit further comprises:
a storage capacitor, wherein a first electrode of the storage capacitor is the pixel electrode, a second electrode of the storage capacitor is a first common electrode, and the discharge electrode comprises the first common electrode (para[0035]; see liquid crystal capacitor C as the claimed storage capacitor in Fig. 2, based on the broadest reasonable interpretation of the claim limitations since all capacitors store energy);
wherein the first common electrode is a common electrode on an array substrate side (para[0028]; para[0030]; para[0035]; ” An embodiment of the present invention provides an array substrate, as shown in FIG. 2”; “the array substrate includes a common electrode line Vcom” and “The common electrode and the pixel electrode in each pixel unit constitute a liquid crystal capacitor C”; accordingly, the discharge electrode (first common electrode) is a common electrode on an array substrate side).
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Regarding claim 3, Chen discloses all the claim limitations as applied above (see claim 1). In addition, Chen discloses a liquid crystal capacitor, wherein a first electrode of the liquid crystal capacitor is the pixel electrode, a second electrode of the liquid crystal capacitor is a second common electrode, and the discharge electrode comprises the second common electrode (para[0035]; see the liquid crystal capacitor C in Fig. 2; it is noted that the second electrode of the liquid crystal capacitor (discharge electrode in Fig. 2 reproduced above) is also the claimed second common electrode, based on the broadest reasonable interpretation of the claimed limitations).
Regarding claim 4, Chen discloses all the claim limitations as applied above (see claim 1). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the scanning line, one of a source and a drain of the first transistor is electrically connected to the data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to gate line 1(N), one of a source and a drain connected to data line 2, and the other one of the source and the drain connected to the pixel electrode, as shown in annotated Fig. 2 reproduced above).
Regarding claim 5, Chen discloses all the claim limitations as applied above (see claim 1). In addition, Chen discloses the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the signal control line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 connected with a gate terminal connected to gate line 1(N-1)(claimed signal control line), one of a source and a drain connected to the pixel electrode, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above).
Regarding claim 6, Chen discloses all the claim limitations as applied above (see claim 1). In addition, Chen discloses a plurality of scanning lines extending in a transverse direction that are sequentially arranged from top to bottom (see plurality of gate lines 1 in Fig. 2), a plurality of data lines extending in a longitudinal direction that are sequentially arranged from left to right and insulated from the plurality of scanning lines (see plurality of data lines 2 in Fig. 2), and a plurality of sub-pixels arranged in an array that are defined by the plurality of scanning lines and the plurality of data lines (para[0028]; “the plurality of gate lines 1 and the plurality of data lines 2 divide the array substrate into a plurality of pixel units arranged in multiple rows”, the plurality of pixel units taken as the claimed sub-pixels);
wherein, both M and N are preset as positive integers, N is greater than or equal to 2, and the charging module is electrically connected to the Mth data line, the Nth scanning line, and the pixel electrode in the Nth row and the Mth column (as shown in annotated Fig. 2 reproduced above, taking e.g. N=3 and M=1, transistor T2 of the claimed charging module is connected to the M data line 2, the N gate line 1, and the pixel electrode in the Nth row and the Mth column);
wherein, the signal control line is the (N-1)th scanning line, and the discharging module is electrically connected to the (N-1)th scanning line, the discharge electrode, and the pixel electrode in the Nth row and the Mth column (see the claimed signal control line is the N-1 gate line 1, the discharge module 3 is connected to the N-1 gate line 1, the discharge electrode, and the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above).
Regarding claim 7, Chen discloses all the claim limitations as applied above (see claim 6). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth column (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to the N gate line 1, one of a source and a drain connected to the M data line 2, and the other one of the source and the drain connected to the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above);
the discharging module comprises:
a second transistor, wherein a gate of the second transistor is electrically connected to the (N-1)th scanning line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 with a gate terminal connected to the N-1 gate line 1 (claimed N-1 signal control line), one of a source and a drain connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above);
wherein both the first transistor and the second transistor are N-type transistors or P-type transistors (see in Fig. 2 transistors T2 and T1 are N-type transistors).
Regarding claims 11 and 13-17, these claims are analogous to claims 1 and 3-7, except they are display panel claims comprising a driving circuit with same limitations as the driving circuit in claims 1 and 3-7 (see para[0002], para[0005], para[0010] and para[0039] of Chen), respectively, and therefore they are rejected for the same reasons as claims 1 and 3-7 above, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Zhang et al. (US 2021/0074227).
Regarding claim 8, Chen discloses all the claim limitations as applied above (see claim 1). In addition, Chen discloses a plurality of scanning lines extending in a transverse direction that are sequentially arranged from top to bottom (see plurality of gate lines 1 in Fig. 2), a plurality of data lines extending in a longitudinal direction that are sequentially arranged from left to right and insulated from the plurality of scanning lines (see plurality of data lines 2 in Fig. 2), and a plurality of sub-pixels arranged in an array that are defined by the plurality of scanning lines and the plurality of data lines (para[0028]; “the plurality of gate lines 1 and the plurality of data lines 2 divide the array substrate into a plurality of pixel units arranged in multiple rows”, the plurality of pixel units taken as the claimed sub-pixels);
wherein, both M and N are preset as positive integers, and the charging module is electrically connected to the Mth data line, the Nth scanning line, and the pixel electrode in the Nth row and the Mth column (as shown in annotated Fig. 2 reproduced above, taking e.g. N=3 and M=1, transistor T2 of the claimed charging module is connected to the M data line 2, the N gate line 1, and the pixel electrode in the Nth row and the Mth column);
wherein, the discharging module is electrically connected to the discharge electrode, and the pixel electrode in the Nth row and the Mth column (see the discharge module 3 is connected to the discharge electrode, and the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above); wherein,
the charging module writes a signal of the Mth data line into the pixel electrode in the Nth row and the Mth column when the signal of the Nth scanning line has a first polarity (para[0033]; para[0037]; para[0039]; para[0042]; “the gate driving unit 4 applies a high level to the N.sup.th row of gate line, and the source driving unit 5 inputs a gray-scale voltage to the pixel electrode of the pixel unit in the N.sup.th row, so that the pixel unit in the N.sup.th row normally displays”, that is, the transistor T2 of the claimed charging module writes a gray-scale voltage of the M data line 2 into the pixel electrode in the Nth row and the Mth column when the N gate line 1 has a high level with a certain first polarity during a polarity reversal process of liquid crystals);
the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode (para[0036]; “the discharge transistor T1 in the pixel unit in the N.sup.th row is turned on, then the pixel electrode in the N.sup.th row is connected to the common electrode line Vcom, so charges on the pixel electrode in the N.sup.th row are discharged to the common electrode, and the voltage of the pixel electrode in the N.sup.th row is consistent with that of Vcom”), wherein the first polarity is one of a positive polarity and a negative polarity (para[0037]; para[0039]; para[0042]; it is clear that during the polarity reversal process of liquid crystals, the polarity of the high level signal applied to the N.sup.th row of gate line is one of a positive polarity and a negative polarity).
However, Chen does not appear to expressly disclose wherein, the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line; the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, and the second polarity is the other one of the positive polarity and the negative polarity.
Zhang discloses a signal control line is an Nth scanning line, and a discharging module is electrically connected to the Nth scanning line, a discharge electrode, and a pixel electrode in an Nth row and Mth column, wherein, both M and N are preset as positive integers (regarding Figs. 9-10, the claimed signal control line is an Nth gate line, the claim discharging module comprises transistor T2 connected to the Nth gate line, a discharge/common electrode 4, and a pixel/drive electrode 5 in the Nth row and the Nth column (claimed Mth column); para[0038]); a charging module writes a signal of the Mth data line into the pixel electrode in the Nth row and the Mth column when the signal of the Nth scanning line has a first polarity (para[0032]-para[0033]; para[0035]; regarding Figs. 9-10, “The first switch T1 is configured to apply a drive signal (Data) to a first electrode (e.g., the drive electrode 5) when the first switch T1 receives a control signal (Gate)”; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor” and e.g., “The logic level of the control signal (Gate) to turn on the first transistor T1 is a high level”, the claimed charging module comprising the first transistor T1); the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, wherein the first polarity is one of a positive polarity and a negative polarity, and the second polarity is the other one of the positive polarity and the negative polarity (para[0032]-para[0033]; para[0035]; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor”; “The logic level of the control signal (Gate) to turn on the second transistor T2 is the low level”; “When the control signal (Gate) is at the low level, even if there is a leakage current through the first transistor T1 to the drive electrode 5, the second transistor T2, which is turned on, can discharge the drive electrode 5”, by “short-circuit[ing] the first electrode (e.g., the drive electrode 5) to the second electrode (e.g., the common electrode 4)”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s invention, with the teachings in Zhang’s invention, to have the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line; the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, and the second polarity is the other one of the positive polarity and the negative polarity, for the advantage of alternatively using different types of transistors to charge and discharge the drive/pixel electrode, and still be able to discharge the drive/pixel electrode even in the presence of a leakage current through the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claim 9, Chen and Zhang disclose all the claim limitations as applied above (see claim 8). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth column (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to the N gate line 1, one of a source and a drain connected to the M data line 2, and the other one of the source and the drain connected to the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above);
the discharging module comprises:
a second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 with a gate terminal connected to the N-1 gate line 1 (claimed N-1 signal control line), one of a source and a drain connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above);
wherein the first transistor is an N-type transistor or a P-type transistor, and the second transistor is a P-type transistor or an N-type transistor (see in Fig. 2 transistors T2 and T1 are N-type transistors, based on the broadest reasonable interpretation of the claimed limitations).
In addition, in the combination Zhang discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line (see a gate of transistor T1 (claimed charging module) connected to the Nth gate line, as shown in Figs. 9-10); the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line (see a gate of transistor T2 (claimed discharging module) connected to the Nth gate line, as shown in Figs. 9-10), and the first transistor is an N-type transistor or a P-type transistor, and the second transistor is a P-type transistor or an N-type transistor (para[0033]; “the first switch T1 is a p-channel transistor and the second switch T2 is an n-channel transistor”; or “the first switch T1 is an n-channel transistor and the second switch T2 is a p-channel transistor”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a gate of the second transistor is electrically connected to the Nth scanning line, as taught by Zhang, for the advantage of using different types of transistors connected to a same scanning line to charge and discharge the drive/pixel electrode, and discharge the drive/pixel electrode even in the presence of a leakage current through the transistor of the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claims 18-19, these claims are analogous to claims 8-9, respectively, and therefore they are rejected for the same reasons as claims 8-9 above, respectively.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Dong et al. (US 2018/0047364).
Regarding claim 10, Chen discloses all the claim limitations as applied above (see claim 1). However, Chen does not appear to expressly disclose the discharge electrode is a ground terminal.
Dong discloses a discharge electrode is a ground terminal (para[0062]; para[0078]; e.g. “storage capacitors of respective pixels… can be discharged to the ground”, which “avoids… flicker of the liquid crystal panel due to the incomplete release of the charge” and “the voltage on the common electrode, the voltage on the data lines, and the voltage on the pixel electrode can be synchronously discharged rapidly with the same potential via the ground path”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s invention, with the teachings in Dong’s invention, to have the discharge electrode is a ground terminal, for the advantage of a rapid discharge to avoid flicker of a liquid crystal panel due to the incomplete release of charge (para[0062]; para[0078]).
Regarding claim 20, this claim is analogous to claim 10, and therefore it is rejected for the same reasons as claim 10 above.
Claim 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Yen et al. (US 2008/0309840).
Regarding claim 21, Chen discloses a pixel driving circuit (see Fig. 2), comprising:
a pixel electrode (see pixel electrode in annotated Fig. 2 reproduced below);
a charging module electrically connected to a data line, a scanning line, and the pixel electrode, wherein the charging module is configured to write a signal of the data line to the pixel electrode under the control of a signal of the scanning line (para [0033]; para[0035]; see e.g. the claimed charging module comprising transistor T2 connected to a data line 2, gate line 1(N) and the pixel electrode, and configured to write a signal of the data line 2 to the pixel electrode under the control of the gate line 1(N), as shown in annotated Fig. 2 reproduced below); and
a discharging module electrically connected to a signal control line, a discharge electrode, and the pixel electrode, wherein the discharging module is configured to connect the pixel electrode to the discharging electrode under the control of a signal of the signal control line (para[0028]-para[0031]; para[0035]-para[0036]; see e.g. discharge module 3 comprising transistor T1 connected to gate line 1(N-1)(claimed signal control line), a discharge electrode and the pixel electrode, and configured to connect the pixel electrode to the discharge electrode under the control of a signal from gate line 1(N-1), as shown in annotated Fig. 2 reproduced below);
wherein the pixel driving circuit further comprises:
a storage capacitor, wherein a first electrode of the storage capacitor is the pixel electrode, a second electrode of the storage capacitor is a first common electrode, and the discharge electrode comprises the first common electrode (para[0035]; see liquid crystal capacitor C as the claimed storage capacitor in Fig. 2, based on the broadest reasonable interpretation of the claim limitations since all capacitors store energy);
wherein the first common electrode is a common electrode on an array substrate side (para[0028]; para[0030]; para[0035]; ” An embodiment of the present invention provides an array substrate, as shown in FIG. 2”; “the array substrate includes a common electrode line Vcom” and “The common electrode and the pixel electrode in each pixel unit constitute a liquid crystal capacitor C”; accordingly, the discharge electrode (first common electrode) is a common electrode on an array substrate side); and
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However, Chen does not appear to expressly disclose the discharge electrode is configured to be connected to a voltage whose polarity is opposite to a polarity of a current voltage applied to the pixel electrode.
Yen discloses a discharge electrode is configured to be connected to a voltage whose polarity is opposite to a polarity of a current voltage applied to a pixel electrode (see in Fig. 1(a) a discharge/common electrode connected to a voltage whose polarity is opposite to a polarity of a voltage applied to a pixel electrode; para[0004]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s invention, with the teachings in Yen’s invention, to have the discharge electrode is configured to be connected to a voltage whose polarity is opposite to a polarity of a current voltage applied to the pixel electrode for the known advantage of controlling alignment of LC (liquid crystals) as decided by an electric field applied to them (para[0004]).
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
Regarding claim 1 (and similar claims 11 and 21), the applicant argues on pages 11-12 of the remarks that “Chen discloses a liquid crystal capacitor, but does not disclose, teach, or otherwise suggest a storage capacitor having the claimed connection structure”, allegedly because “the present specification explicitly identifies a liquid crystal capacitor (Clc) as a capacitor distinct from the claimed storage capacitor”.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “a liquid crystal capacitor (Clc) as a capacitor distinct from the claimed storage capacitor”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). As shown in the above rejection, Chen discloses a storage capacitor, wherein a first electrode of the storage capacitor is the pixel electrode, a second electrode of the storage capacitor is a first common electrode, and the discharge electrode comprises the first common electrode (para[0035]; see liquid crystal capacitor C as the claimed storage capacitor in Fig. 2, based on the broadest reasonable interpretation of the claim limitations since all capacitors store energy).
Moreover, regarding newly added claim 21, the applicant argues on page 12 of the remarks that “amended claim 21 further recites: "wherein the discharge electrode is configured to be connected to a voltage whose polarity is opposite to a polarity of a current voltage applied to the pixel electrode"”, and “The cited prior art does not disclose, teach, or otherwise suggest such a discharge electrode configuration”. Applicant’s argument with respect to claim(s) 21 has been considered but is moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The newly added limitation has now been treated on the merits as shown in the above rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623