Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Non-Final Office Action mailed on 4/16/2026, the applicant has filed a response on 7/15/2026, amending claims 1, 6-9, 11 and 16-19. Claims 2-3 and 12-13 have been cancelled. No claim has been added. Claims 1, 4-11 and 14-21 are pending in this application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations “the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth; the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode; wherein both the first and the second transistor are N-type transistors or P-type transistors”, as claimed in claims 7 and 17, must be shown or the feature(s) canceled from the claim(s). None of the drawings show the gates of the first and second transistors being connected to a same scanning line, when the first and second transistors are of a same type. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitations in amended claims 7 and 17 “the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth; the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode; wherein both the first and the second transistor are N-type transistors or P-type transistors” are not supported by the disclosure of the invention as originally filed, and therefore introduce new matter. Neither the drawings or the specification as originally filed disclose the gates of the first and second transistors being connected to a same scanning line when the first and second transistors are of a same type. Accordingly, subject matter in amended claims 7 and 17 was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, it recites “a gate of the first transistor is electrically connected to the Nth scanning line”, “a gate of the second transistor is electrically connected to the Nth scanning line”, and “both the first and the second transistor are N-type transistors or P-type transistors”. However, given claim 7 depends from claim 1, it is unclear how “in response to a first voltage level of the scanning line, the charging module writes the signal of the data line to the pixel electrode while the discharging module is turned off, and in response to a second voltage level of the scanning line opposite to the first voltage level, the discharging module connects the pixel electrode to the discharge electrode while the charging module is turned off”, as claimed in claimed 1, when the gates of the first and the second transistors are connected to the same scanning line, and the first and the second transistors are of a same type, as claimed in claim 7.
Regarding claim 17, it is analogous to claim 7, contains the same issue, and is therefore rejected for the same reasons as claim 7 above.
Appropriate corrections are required. The claims will be interpreted as best understood.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 11 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Yen et al. (US 2008/0309840), and further in view of Hao (US 2018/0356662).
Regarding claim 1, Chen discloses a pixel driving circuit (see Fig. 2), comprising:
a pixel electrode (see pixel electrode in annotated Fig. 2 reproduced below);
a charging module electrically connected to a data line, a scanning line, and the pixel electrode, wherein the charging module is configured to write a signal of the data line to the pixel electrode under the control of a signal of the scanning line (para[0033]; para[0035]; see e.g. the claimed charging module comprising transistor T2 connected to a data line 2, gate line 1(N) and the pixel electrode, and configured to write a signal of the data line 2 to the pixel electrode under the control of the gate line 1(N), as shown in annotated Fig. 2 reproduced below); and
a discharging module electrically connected to a signal control line, a discharge electrode, and the pixel electrode, wherein the discharging module is configured to connect the pixel electrode to the discharge electrode under the control of a signal of the signal control line (para[0028]-para[0031]; para[0035]-para[0036]; see e.g. discharge module 3 comprising transistor T1 connected to gate line 1(N-1)(claimed signal control line), a discharge electrode and the pixel electrode, and configured to connect the pixel electrode to the discharge electrode under the control of a signal from gate line 1(N-1), as shown in annotated Fig. 2 reproduced below);
wherein the discharge electrode comprises a common electrode (para[0028]; para[0030]-para[0031]; “a second [discharge] electrode of the discharge transistor T1 is connected with the low-level signal terminal, namely connected with the common electrode line Vcom);
wherein the pixel driving circuit further comprises:
a liquid crystal capacitor, wherein the liquid crystal capacitor is formed by the pixel electrode and the common electrode (para[0035]; “The common electrode and the pixel electrode in each pixel unit constitute a liquid crystal capacitor C”);
wherein the charging module and the discharging module are configured such that, in response to a first voltage level of the scanning line, the charging module writes the signal of the data line to the pixel electrode while the discharging module is turned off (referring to Fig. 2 below, “the pixel electrode is connected with the source driving unit 5 through the switching transistor T2, and the on and off states of the switching transistor T2 are controlled by the current row (the N.sup.th row) of gate line”; “When the gate driving unit 4 stops applying the high level to the (N−1).sup.th row of gate line, the gray-scale voltage of the pixel electrode in the (N−1).sup.th row is kept unchanged for a frame of time, so the discharge transistor T1 in the pixel unit in the N.sup.th row is cut off”; accordingly, while the discharge transistor T1 is turned off, that is, while a low level is applied to the (N−1).sup.th row of gate line, the switching transistor T2 is turned on because “the gate driving unit 4 applies a high level to the N.sup.th row of gate line, and the source driving unit 5 inputs a gray-scale voltage to the pixel electrode of the pixel unit in the N.sup.th row, so that the pixel unit in the N.sup.th row normally displays”; para[0035]; para[0037]), and in response to a second voltage level of the scanning line opposite to the first voltage level, the discharging module connects the pixel electrode to the discharge electrode while the charging module is turned off (“When the gate driving unit 4 applies a high level to the (N−1).sup.th row of gate line, the pixel units in the (N−1).sup.th row display, meanwhile, the discharge transistor T1 in the pixel unit in the N.sup.th row is turned on, then the pixel electrode in the N.sup.th row is connected to the common electrode line Vcom, so charges on the pixel electrode in the N.sup.th row are discharged to the common electrode, and the voltage of the pixel electrode in the N.sup.th row is consistent with that of Vcom”, clearly given that the switching transistor T2 is turned off; para[0035]-para[0036]).
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However, Chen does not appear to expressly disclose wherein the discharge electrode comprises a first common electrode and a second common electrode; wherein the pixel driving circuit further comprises: a storage capacitor, wherein the storage capacitor is formed by the pixel electrode and the first common electrode; and the liquid crystal capacitor is formed by the pixel electrode and the second common electrode; wherein the first common electrode is a common electrode on an array substrate side, and the second common electrode is a common electrode on a color film substrate side.
Yen discloses a discharge electrode comprises a first common electrode (see discharge electrode comprising a first common electrode connected to storage capacitor Cs in Fig. 2; para[0021]) and a second common electrode (see the discharge electrode comprising a second common electrode connected to liquid crystal capacitor LC in Fig. 2; para[0021]); a pixel driving circuit (pixel circuit 200 in Fig. 2; para[0021]) comprising: a storage capacitor, wherein the storage capacitor is formed by a pixel electrode and the first common electrode (see storage capacitor Cs in Fig. 2, formed by a pixel electrode and the first common electrode; para[0021]); a liquid crystal capacitor, wherein the liquid crystal capacitor is formed by the pixel electrode and the second common electrode (see liquid crystal capacitor LC, formed by the pixel electrode and the second common electrode; para[0021]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s invention, with the teachings in Yen’s invention, to have the discharge electrode comprises a first common electrode and a second common electrode; the pixel driving circuit further comprises: a storage capacitor, wherein the storage capacitor is formed by the pixel electrode and the first common electrode; and the liquid crystal capacitor is formed by the pixel electrode and the second common electrode, for the advantage of having the conventionally known configuration of a storage capacitor in parallel with the liquid crystal capacitor, allowing the potential of a pixel electrode to be retained (see para[0005] of Yoshida et al. (2013/0250226) as evidentiary support).
Chen and Yen do not appear to expressly disclose owever, lkmknjcthe first common electrode is a common electrode on an array substrate side, and the second common electrode is a common electrode on a color film substrate side.
Hao discloses a storage capacitor is formed by a pixel electrode and a first common electrode, the first common electrode is a common electrode on an array substrate side (para[0048]; regarding Fig. 4, “One side of both the first storage capacitor CST1 and the first liquid crystal capacitor CLC1 are connected to the drain of the first thin film transistor T1 (claimed pixel electrode)”; “The other side of the first storage capacitor CST1 is connected to a common electrode on one side of the array substrate” (claimed first common electrode)), and a liquid crystal capacitor is formed by the pixel electrode and a second common electrode, the second common electrode is a common electrode on a color film substrate side (para[0048]; “One side of both the first storage capacitor CST1 and the first liquid crystal capacitor CLC1 are connected to the drain of the first thin film transistor T1 (claimed pixel electrode)”; “The other side of the first liquid crystal capacitor CLC1 is connected to a common electrode one side of the color film substrate” (claimed first common electrode)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s and Yen’s combination, with the teachings in Hao’s invention, to have owever, lkmknjcthe first common electrode is a common electrode on an array substrate side, and the second common electrode is a common electrode on a color film substrate side, for the advantage using a known configuration which is part of a solution to increase viewing angle in liquid crystal displays (para [0004]).
Regarding claim 4, Chen, Yen and Hao disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the scanning line, one of a source and a drain of the first transistor is electrically connected to the data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to gate line 1(N), one of a source and a drain connected to data line 2, and the other one of the source and the drain connected to the pixel electrode, as shown in annotated Fig. 2 reproduced above).
Regarding claim 5, Chen, Yen and Hao disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the signal control line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 connected with a gate terminal connected to gate line 1(N-1)(claimed signal control line), one of a source and a drain connected to the pixel electrode, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above).
Regarding claims 11 and 14-15, these claims are analogous to claims 1 and 4-5, except they are display panel claims comprising a driving circuit with same limitations as the driving circuit in claims 1 and 4-5, respectively (see para[0002], para[0005], para[0010] and para[0039] of Chen; para[0010] of Yen; para[0001] of Hao), and therefore they are rejected for the same reasons as claims 1 and 4-5 above, respectively.
Claims 6-9 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Yen et al. (US 2008/0309840) and Hao (US 2018/0356662), and further in view of Zhang et al. (US 2021/0074227).
Regarding claim 6, Chen, Yen and Hao disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses a plurality of scanning lines extending in a transverse direction that are sequentially arranged from top to bottom (see plurality of gate lines 1 in Fig. 2), a plurality of data lines extending in a longitudinal direction that are sequentially arranged from left to right and insulated from the plurality of scanning lines (see plurality of data lines 2 in Fig. 2), and a plurality of sub-pixels arranged in an array that are defined by the plurality of scanning lines and the plurality of data lines (para[0028]; “the plurality of gate lines 1 and the plurality of data lines 2 divide the array substrate into a plurality of pixel units arranged in multiple rows”, the plurality of pixel units taken as the claimed sub-pixels);
wherein, both M and N are preset as positive integers, N is greater than or equal to 2, and the charging module is electrically connected to the Mth data line, the Nth scanning line, and the pixel electrode in the Nth row and the Mth column (as shown in annotated Fig. 2 reproduced above, taking e.g. N=3 and M=1, transistor T2 of the claimed charging module is connected to the M data line 2, the N gate line 1, and the pixel electrode in the Nth row and the Mth column);
wherein, the signal control line is the (N-1)th scanning line, and the discharging module is electrically connected to the (N-1)th scanning line, the discharge electrode, and the pixel electrode in the Nth row and the Mth column (see the claimed signal control line is the N-1 gate line 1, the discharge module 3 is connected to the N-1 gate line 1, the discharge electrode, and the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above).
However, Chen, Yen and Hao do not appear to expressly disclose the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line, the discharge electrode, and the pixel electrode in the Nth row and the Mth column.
Zhang discloses a signal control line is an Nth scanning line, and a discharging module is electrically connected to the Nth scanning line, a discharge electrode, and a pixel electrode in an Nth row and Mth column (regarding Figs. 9-10, the claimed signal control line is an Nth gate line, the claim discharging module comprises transistor T2 connected to the Nth gate line, a discharge/common electrode 4, and a pixel/drive electrode 5 in the Nth row and the Nth column (claimed Mth column); para[0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s, Yen’s and Hao’s combination, with the teachings in Zhang’s invention, to have the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line, the discharge electrode, and the pixel electrode in the Nth row and the Mth column, for the advantage of alternatively using different types of transistors to charge and discharge the drive/pixel electrode, and still be able to discharge the drive/pixel electrode even in the presence of a leakage current through the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claim 7, as best understood, Chen, Yen, Hao and Zhang disclose all the claim limitations as applied above (see claim 6). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth column (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to the N gate line 1, one of a source and a drain connected to the M data line 2, and the other one of the source and the drain connected to the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above);
the discharging module comprises:
a second transistor, wherein a gate of the second transistor is electrically connected to the (N-1)th scanning line, one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 with a gate terminal connected to the N-1 gate line 1 (claimed N-1 signal control line), one of a source and a drain connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above);
wherein both the first transistor and the second transistor are N-type transistors or P-type transistors (see in Fig. 2 transistors T2 and T1 are N-type transistors).
In addition, Zhang discloses the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line (regarding Figs. 9-10, the claim discharging module comprises transistor T2 connected to the Nth gate line; para[0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the discharging module comprises:
a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line, for the advantage of alternatively using different types of transistors to charge and discharge the drive/pixel electrode, and still be able to discharge the drive/pixel electrode even in the presence of a leakage current through the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claim 8, Chen, Yen and Hao disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses a plurality of scanning lines extending in a transverse direction that are sequentially arranged from top to bottom (see plurality of gate lines 1 in Fig. 2), a plurality of data lines extending in a longitudinal direction that are sequentially arranged from left to right and insulated from the plurality of scanning lines (see plurality of data lines 2 in Fig. 2), and a plurality of sub-pixels arranged in an array that are defined by the plurality of scanning lines and the plurality of data lines (para[0028]; “the plurality of gate lines 1 and the plurality of data lines 2 divide the array substrate into a plurality of pixel units arranged in multiple rows”, the plurality of pixel units taken as the claimed sub-pixels);
wherein, both M and N are preset as positive integers, and the charging module is electrically connected to the Mth data line, the Nth scanning line, and the pixel electrode in the Nth row and the Mth column (as shown in annotated Fig. 2 reproduced above, taking e.g. N=3 and M=1, transistor T2 of the claimed charging module is connected to the M data line 2, the N gate line 1, and the pixel electrode in the Nth row and the Mth column);
wherein, the discharging module is electrically connected to the discharge electrode, and the pixel electrode in the Nth row and the Mth column (see the discharge module 3 is connected to the discharge electrode, and the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above); wherein,
the charging module writes a signal of the Mth data line into the pixel electrode in the Nth row and the Mth column when the signal of the Nth scanning line has a first polarity (para[0033]; para[0037]; para[0039]; para[0042]; “the gate driving unit 4 applies a high level to the N.sup.th row of gate line, and the source driving unit 5 inputs a gray-scale voltage to the pixel electrode of the pixel unit in the N.sup.th row, so that the pixel unit in the N.sup.th row normally displays”, that is, the transistor T2 of the claimed charging module writes a gray-scale voltage of the M data line 2 into the pixel electrode in the Nth row and the Mth column when the N gate line 1 has a high level with a certain first polarity during a polarity reversal process of liquid crystals);
the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode (para[0036]; “the discharge transistor T1 in the pixel unit in the N.sup.th row is turned on, then the pixel electrode in the N.sup.th row is connected to the common electrode line Vcom, so charges on the pixel electrode in the N.sup.th row are discharged to the common electrode, and the voltage of the pixel electrode in the N.sup.th row is consistent with that of Vcom”), wherein the first polarity is one of a positive polarity and a negative polarity (para[0037]; para[0039]; para[0042]; it is clear that during the polarity reversal process of liquid crystals, the polarity of the high level signal applied to the N.sup.th row of gate line is one of a positive polarity and a negative polarity).
However, Chen, Yen and Hao do not appear to expressly disclose wherein, the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line; the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, and the second polarity is the other one of the positive polarity and the negative polarity; wherein, in response to the first polarity, the charging module is turned on and the discharging module is turned off, and in response to the second polarity, the charging module is turned off and the discharging module is turned on.
Zhang discloses a signal control line is an Nth scanning line, and a discharging module is electrically connected to the Nth scanning line, a discharge electrode, and a pixel electrode in an Nth row and Mth column, wherein, both M and N are preset as positive integers (regarding Figs. 9-10, the claimed signal control line is an Nth gate line, the claim discharging module comprises transistor T2 connected to the Nth gate line, a discharge/common electrode 4, and a pixel/drive electrode 5 in the Nth row and the Nth column (claimed Mth column); para[0038]); a charging module writes a signal of the Mth data line into the pixel electrode in the Nth row and the Mth column when the signal of the Nth scanning line has a first polarity (para[0032]-para[0033]; para[0035]; regarding Figs. 9-10, “The first switch T1 is configured to apply a drive signal (Data) to a first electrode (e.g., the drive electrode 5) when the first switch T1 receives a control signal (Gate)”; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor” and e.g., “The logic level of the control signal (Gate) to turn on the first transistor T1 is a high level”, the claimed charging module comprising the first transistor T1); the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, wherein the first polarity is one of a positive polarity and a negative polarity, and the second polarity is the other one of the positive polarity and the negative polarity (para[0032]-para[0033]; para[0035]; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor”; “The logic level of the control signal (Gate) to turn on the second transistor T2 is the low level”; “When the control signal (Gate) is at the low level, even if there is a leakage current through the first transistor T1 to the drive electrode 5, the second transistor T2, which is turned on, can discharge the drive electrode 5”, by “short-circuit[ing] the first electrode (e.g., the drive electrode 5) to the second electrode (e.g., the common electrode 4)”); wherein, in response to the first polarity, the charging module is turned on and the discharging module is turned off (para[0032]-para[0033]; para[0035]; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor”; “The logic level of the control signal (Gate) to turn on the first transistor T1 is a high level”, the claimed charging module comprising the first transistor T1, and “The logic level of the control signal (Gate) to turn on the second transistor T2 is the low level”, the claimed discharging module comprising the second transistor T2; thus, when the logic level of the control signal is the high level (claimed first polarity) the first transistor T1 is turned on and the second transistor T2 is turned off), and in response to the second polarity, the charging module is turned off and the discharging module is turned on (para[0032]-para[0033]; para[0035]; “as shown in FIG. 9, the first transistor T1 may be an n-channel transistor, and the second transistor T2 may be a p-channel transistor”; “The logic level of the control signal (Gate) to turn on the first transistor T1 is a high level”, the claimed charging module comprising the first transistor T1, and “The logic level of the control signal (Gate) to turn on the second transistor T2 is the low level”, the claimed discharging module comprising the second transistor T2; thus, when the logic level of the control signal is the low level (claimed second polarity) the first transistor T1 is turned off and the second transistor T2 is turned on).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in in Chen’s, Yen’s and Hao’s combination, with the teachings in Zhang’s invention, to have the signal control line is the Nth scanning line, and the discharging module is electrically connected to the Nth scanning line; the discharging module connects the pixel electrode in the Nth row and the Mth column with the discharge electrode when the signal of the Nth scanning line has a second polarity, and the second polarity is the other one of the positive polarity and the negative polarity; wherein, in response to the first polarity, the charging module is turned on and the discharging module is turned off, and in response to the second polarity, the charging module is turned off and the discharging module is turned on, for the advantage of alternatively using different types of transistors to charge and discharge the drive/pixel electrode, and still be able to discharge the drive/pixel electrode even in the presence of a leakage current through the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claim 9, Chen, Yen, Hao and Zhang disclose all the claim limitations as applied above (see claim 8). In addition, Chen discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line, one of a source and a drain of the first transistor is electrically connected to the Mth data line, and the other one of the source and the drain of the first transistor is electrically connected to the pixel electrode in the Nth row and the Mth column (para[0033]; para[0035]; see the claimed charging module comprising transistor T2 with a gate terminal connected to the N gate line 1, one of a source and a drain connected to the M data line 2, and the other one of the source and the drain connected to the pixel electrode in the Nth row and the Mth column, as shown in annotated Fig. 2 reproduced above);
the discharging module comprises:
a second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain of the second transistor is electrically connected to the discharge electrode (para[0028]-para[0031]; para[0035]-para[0036]; see discharge module 3 comprising transistor T1 with a gate terminal connected to the N-1 gate line 1 (claimed N-1 signal control line), one of a source and a drain connected to the pixel electrode in the Nth row and the Mth column, and the other one of the source and the drain connected to the discharge electrode, as shown in annotated Fig. 2 reproduced above).
In addition, in the combination Zhang discloses the charging module comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the Nth scanning line (see a gate of transistor T1 (claimed charging module) connected to the Nth gate line, as shown in Figs. 9-10); the discharging module comprises: a second transistor, wherein a gate of the second transistor is electrically connected to the Nth scanning line (see a gate of transistor T2 (claimed discharging module) connected to the Nth gate line, as shown in Figs. 9-10), and the first transistor is an N-type transistor [[or]] and the second transistor is a P-type transistor, or the first transistor is a P-type transistor [[or]] and the second transistor is an N-type transistor (para[0033]; “the first switch T1 is an n-channel transistor and the second switch T2 is a p-channel transistor”, or “the first switch T1 is a p-channel transistor and the second switch T2 is an n-channel transistor”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a gate of the second transistor is electrically connected to the Nth scanning line, and the first transistor is an N-type transistor and the second transistor is a P-type transistor, or the first transistor is a P-type transistor and the second transistor is an N-type transistor, as also taught by Zhang, for the advantage of using different types of transistors connected to a same scanning line to charge and discharge the drive/pixel electrode, and discharge the drive/pixel electrode even in the presence of a leakage current through the transistor of the charging module to the drive/pixel electrode (para[0035]; para[0038]).
Regarding claims 16-19, these claims are analogous to claims 6-9, respectively, and therefore they are rejected for the same reasons as claims 6-9 above, respectively.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Yen et al. (US 2008/0309840) and Hao (US 2018/0356662), and further in view of Dong et al. (US 2018/0047364).
Regarding claim 10, Chen, Yen and Hao disclose all the claim limitations as applied above (see claim 1). However, Chen, Yen and Hao do not appear to expressly disclose the discharge electrode is a ground terminal.
Dong discloses a discharge electrode is a ground terminal (para[0062]; para[0078]; e.g. “storage capacitors of respective pixels… can be discharged to the ground”, which “avoids… flicker of the liquid crystal panel due to the incomplete release of the charge” and “the voltage on the common electrode, the voltage on the data lines, and the voltage on the pixel electrode can be synchronously discharged rapidly with the same potential via the ground path”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s, Yen’s and Hao’s combination, with the teachings in Dong’s invention, to have the discharge electrode is a ground terminal, for the advantage of a rapid discharge to avoid flicker of a liquid crystal panel due to the incomplete release of charge (para[0062]; para[0078]).
Regarding claim 20, this claim is analogous to claim 10, and therefore it is rejected for the same reasons as claim 10 above.
Claim 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0061917), in view of Xie (US 2018/0031908).
Regarding claim 21, Chen discloses a pixel driving circuit (see Fig. 2), comprising:
a pixel electrode (see pixel electrode in annotated Fig. 2 reproduced below);
a charging module electrically connected to a data line, a scanning line, and the pixel electrode, wherein the charging module is configured to write a signal of the data line to the pixel electrode under the control of a signal of the scanning line (para [0033]; para[0035]; see e.g. the claimed charging module comprising transistor T2 connected to a data line 2, gate line 1(N) and the pixel electrode, and configured to write a signal of the data line 2 to the pixel electrode under the control of the gate line 1(N), as shown in annotated Fig. 2 reproduced below); and
a discharging module electrically connected to a signal control line, a discharge electrode, and the pixel electrode, wherein the discharging module is configured to connect the pixel electrode to the discharging electrode under the control of a signal of the signal control line (para[0028]-para[0031]; para[0035]-para[0036]; see e.g. discharge module 3 comprising transistor T1 connected to gate line 1(N-1)(claimed signal control line), a discharge electrode and the pixel electrode, and configured to connect the pixel electrode to the discharge electrode under the control of a signal from gate line 1(N-1), as shown in annotated Fig. 2 reproduced below);
wherein the pixel driving circuit further comprises:
a storage capacitor, wherein a first electrode of the storage capacitor is the pixel electrode, a second electrode of the storage capacitor is a first common electrode, and the discharge electrode comprises the first common electrode (para[0035]; see liquid crystal capacitor C as the claimed storage capacitor in Fig. 2, based on the broadest reasonable interpretation of the claim limitations since all capacitors store energy);
wherein the first common electrode is a common electrode on an array substrate side (para[0028]; para[0030]; para[0035]; ” An embodiment of the present invention provides an array substrate, as shown in FIG. 2”; “the array substrate includes a common electrode line Vcom” and “The common electrode and the pixel electrode in each pixel unit constitute a liquid crystal capacitor C”; accordingly, the discharge electrode (first common electrode) is a common electrode on an array substrate side).
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However, Chen does not appear to expressly disclose the discharge electrode is configured to receive, in response to a current voltage of the pixel electrode having a third polarity, a voltage signal having a fourth polarity opposite to the third polarity, wherein the third polarity is one of a positive polarity and a negative polarity, and the fourth polarity is the other one of the positive polarity and the negative polarity.
Xie discloses a first common electrode is configured to receive, in response to a current voltage of a pixel electrode having a third polarity, a voltage signal having a fourth polarity opposite to the third polarity, wherein the third polarity is one of a positive polarity and a negative polarity, and the fourth polarity is the other one of the positive polarity and the negative polarity (para[0005]; “voltages having opposite polarities are applied to the common electrode and the pixel electrode”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Chen’s invention, with the teachings in Xie’s invention, to have the discharge/first common electrode is configured to receive, in response to a current voltage of the pixel electrode having a third polarity, a voltage signal having a fourth polarity opposite to the third polarity, wherein the third polarity is one of a positive polarity and a negative polarity, and the fourth polarity is the other one of the positive polarity and the negative polarity, for the advantage of controlling alignment of liquid crystals in a certain direction as decided by an electric field applied to them (see para[0005]).
Response to Arguments
Applicant's arguments filed on 7/15/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 11, newly added limitations have now been treated on the merits as shown in the above rejection which has been modified in the same fashion as the amended claims. However, the applicant argues on page 12 of the remarks that “Chen Does Not Teach Complementary Charging/Discharging Modules Controlled by the Same Scanning Line”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “Charging/Discharging Modules Controlled by the Same Scanning Line”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In addition, regarding claims 1 and 11, the applicant argues on page 13 of the remarks that “Zhang Does Not Teach or Suggest Applying Its Microfluidic Leakage Prevention Architecture to LCD Pixel Voltage Holding”. These arguments with respect to claim(s) 1 and 11 have been considered but are moot because the rejection of these claims does not rely on the Zhang reference.
Regarding claim 21, the applicant argues on page 14 of the remarks that “The ". Xie does not disclose: - a discharging module, - discharging a pixel electrode, - or applying an opposite-polarity voltage signal to a discharge electrode for pixel discharge purposes”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As shown in the above rejection, Xie disclose a first common electrode is configured to receive, in response to a current voltage of a pixel electrode having a third polarity, a voltage signal having a fourth polarity opposite to the third polarity, wherein the third polarity is one of a positive polarity and a negative polarity, and the fourth polarity is the other one of the positive polarity and the negative polarity (para[0005]; “voltages having opposite polarities are applied to the common electrode and the pixel electrode”). Note that in the combination with Chen, the discharge electrode comprises the first common electrode.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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