DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 12/18/2025 has been considered by Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-12, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al (US 2013/0135284 A1).
Claim 1, Tseng (Fig. 2-11) discloses a GOA circuit (Fig. 3; Paragraph [0007]; wherein discloses a gate driver on array (GOA)) comprising multi-stage cascaded GOA modules (SR1 and SR2; Fig. 3), wherein each stage GOA module (Fig. 3) of the GOA modules (Fig. 3; Paragraph [0007]; wherein discloses a gate driver on array (GOA)) comprises a first GOA unit (501; Fig. 5), a pull-up unit (M11; Fig. 5), a pull-down unit (M22; Fig. 5) and a plurality of second GOA units (450, 460, and 470; Fig. 5), the first GOA unit (501; Fig. 5) comprises an input terminal (IN1; Fig. 5), a pull-down terminal (IN2; Fig. 5) and an output terminal (OT1; Fig. 5), and the second GOA unit (450, 460, and 470; Fig. 5) comprises an input terminal (B2(N); Fig. 5) and an output terminal (OUT1, OUT2, and OUT3; Fig. 5), and
wherein the input terminal (IN1; Fig. 5) of the first GOA unit (501; Fig. 5) of an n-th stage GOA module (309; Fig. 3) is connected to the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of an (n-i1)-th stage GOA module (307; Fig. 3), so that the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n-i1)-th stage GOA module (307; Fig. 3) is configured to pull up (M11; Fig. 5) the input terminals (B2(N); Fig. 5) of the plurality of second GOA units (450, 460, and 470; Fig. 5) of the n-th stage GOA module (309; Fig. 3) through an input terminal (IN11; Fig. 5) of the pull-up unit (M11; Fig. 5) of the n-th stage GOA module (309; Fig. 3), so that the output terminals (OUT1, OUT2, and OUT3; Fig. 5) of the plurality of second GOA units (450, 460, and 470; Fig. 5) of the n-th stage GOA module (309; Fig. 3) sequentially output a plurality of scan drive signals (G(N), G(N+1), and G(N+2); Fig. 8);
the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the n-th stage GOA module (311; Fig. 3) is connected to the input terminal (IN1; Fig. 5) of the first GOA unit (501; Fig. 5) of an (n+ 1)-th stage GOA module (313; Fig. 3) and the pull-down terminal (IN2; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n-1)-th stage GOA module (305; Fig. 3); and
the pull-down terminal (IN2; Fig. 5) of the first GOA unit (501; Fig. 5) of the n-th stage GOA module (305; Fig. 3) is connected to the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n+1)-th stage GOA module (311; Fig. 3), so that the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n+1)-th stage GOA module (311; Fig. 3) is configured to pull down the input terminals (B2(N) and M66; Fig. 5) and the output terminals (OUT1; OUT2, and OUT3; Fig. 5; Paragraph [0042] and [0046]) of the plurality of second GOA units (M71, M72, and M73; Fig. 5) of the n-th stage GOA module (305; Fig. 3) through the pull-down unit (M2; Fig. 5) of the n-th stage GOA module (305; Fig. 3).
Claim 10, Tseng (Fig. 2-11) discloses a display panel (Fig. 2) comprising a GOA circuit (Fig. 3; Paragraph [0007]; wherein discloses a gate driver on array (GOA)) comprising multi-stage cascaded GOA modules (SR1 and SR2; Fig. 3), wherein each stage GOA module (Fig. 3) of the GOA modules (Fig. 3; Paragraph [0007]; wherein discloses a gate driver on array (GOA)) comprises a first GOA unit (501; Fig. 5), a pull-up unit (M11; Fig. 5), a pull-down unit (M22; Fig. 5) and a plurality of second GOA units (450, 460, and 470; Fig. 5), the first GOA unit (501; Fig. 5) comprises an input terminal (IN1; Fig. 5), a pull-down terminal (IN2; Fig. 5) and an output terminal (OT1; Fig. 5), and the second GOA unit (450, 460, and 470; Fig. 5) comprises an input terminal (B2(N); Fig. 5) and an output terminal (OUT1, OUT2, and OUT3; Fig. 5), and
wherein the input terminal (IN1; Fig. 5) of the first GOA unit (501; Fig. 5) of an n-th stage GOA module (309; Fig. 3) is connected to the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of an (n-i1)-th stage GOA module (307; Fig. 3), so that the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n-i1)-th stage GOA module (307; Fig. 3) is configured to pull up (M11; Fig. 5) the input terminals (B2(N); Fig. 5) of the plurality of second GOA units (450, 460, and 470; Fig. 5) of the n-th stage GOA module (309; Fig. 3) through an input terminal (IN11; Fig. 5) of the pull-up unit (M11; Fig. 5) of the n-th stage GOA module (309; Fig. 3), so that the output terminals (OUT1, OUT2, and OUT3; Fig. 5) of the plurality of second GOA units (450, 460, and 470; Fig. 5) of the n-th stage GOA module (309; Fig. 3) sequentially output a plurality of scan drive signals (G(N), G(N+1), and G(N+2); Fig. 8);
the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the n-th stage GOA module (311; Fig. 3) is connected to the input terminal (IN1; Fig. 5) of the first GOA unit (501; Fig. 5) of an (n+ 1)-th stage GOA module (313; Fig. 3) and the pull-down terminal (IN2; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n-1)-th stage GOA module (305; Fig. 3); and
the pull-down terminal (IN2; Fig. 5) of the first GOA unit (501; Fig. 5) of the n-th stage GOA module (305; Fig. 3) is connected to the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n+1)-th stage GOA module (311; Fig. 3), so that the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n+1)-th stage GOA module (311; Fig. 3) is configured to pull down the input terminals (B2(N) and M66; Fig. 5) and the output terminals (OUT1; OUT2, and OUT3; Fig. 5; Paragraph [0042] and [0046]) of the plurality of second GOA units (M71, M72, and M73; Fig. 5) of the n-th stage GOA module (305; Fig. 3) through the pull-down unit (M2; Fig. 5) of the n-th stage GOA module (305; Fig. 3).
Claims 2 and 11, Tseng (Fig. 2-11) discloses wherein the first GOA unit (501; Fig. 5) further comprises a first clock signal terminal (CCK1; Fig. 5), and the first GOA units (501; Fig. 5) of the multi-stage cascaded GOA modules (SR1; Fig. 3) sequentially output signals (OT1; Fig. 5) according to a first clock signal input (CCK1; Fig. 7) from the first clock signal terminal (CCK1; Fig. 5).
Claims 3 and 12, Tseng (Fig. 2-11) discloses wherein the second GOA unit (M33, M44, and M55; Fig. 5) further comprises a second clock signal terminal (CK1, CK2, and CK3; Fig. 5), and the plurality of second GOA units (M33, M44, and M55; Fig. 5) of each stage GOA module (Fig. 3) sequentially output the plurality of scan drive signals (Paragraph [0031]) according to a second clock signal (CK1, CK2, and CK3; Fig. 7) input from the second clock signal terminal (CK1, CK2, and CK3; Fig. 5).
Claims 8 and 17, Tseng (Fig. 2-11) discloses wherein the pull-down unit (M22; Fig. 5) of the n-th GOA module (309; Fig. 3) comprises a forty-first transistor (M22; Fig. 5), a gate of the forty-first transistor (M22; Fig. 5) is connected to the pull-down terminal (IN2; Fig. 5; wherein figure shows both IN22 and IN2 receiving the same control signal k(N+9)) of the first GOA unit (501; Fig. 5) of the n-th GOA module (309; Fig. 3), a source of the forty-first transistor (M22; Fig. 5) is connected to a constant voltage low potential (Vss2; Fig. 5), and a drain of the forty-first transistor (M22; Fig. 5) is connected to pull-up terminals (B2(N); Fig. 5) of the plurality of second GOA units (M33, M44, and M55; Fig. 5) of the n-th GOA module (309; Fig. 5).
Claims 9 and 18, Tseng (Fig. 2-11) discloses wherein eight clock cycle signals 9Fig. 7; wherein figure shows a plurality of clock signals) are used at the first clock signal terminal (Paragraph [0053]), with any two successive clock cycle signals are separated by half a clock cycle (3H; Fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al (US 2013/0135284 A1) in view of Zhang (US 2017/0116924 A1).
Claims 4 and 13, Tseng discloses the GOA circuit according to claim 2 and the display panel according to claim 11.
Tseng does not expressly disclose wherein the first GOA unit of the n-th stage GOA module comprises a thirteenth transistor, a twenty-second transistor, a thirty-first transistor, and a forty-third transistor, and
wherein a gate and a source of the thirteenth transistor are both connected to the input terminal of the first GOA unit of the n-th stage GOA module, and a drain of the thirteenth transistor is connected to a first pull-up node;
a gate of the twenty-second transistor is connected to the first pull-up node, a source of the twenty-second transistor is connected to the first clock signal terminal, and a drain of the twenty- second transistor is connected to the output terminal of the first GOA unit of the n-th stage GOA module; and
a gate of the thirty-first transistor and a gate of the forty-third transistor are connected to the pull-down terminal of the first GOA unit of the n-th stage GOA module, a source of the thirty-first transistor and a source of the forty-third transistor are connected to a constant voltage low potential, a drain of the thirty-first transistor is connected to the output terminal of the first GOA unit of the n- th stage GOA module, and a drain of the forty-third transistor is connected to the first pull-up node.
Zhang (Fig. 1-6) discloses wherein the first GOA unit (11 and 14; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages) comprises a thirteenth transistor (T1; Fig. 2), a twenty-second transistor (T9; Fig. 2), a thirty-first transistor (T10; Fig. 2), and a forty-third transistor (T3; Fig. 2), and
wherein a gate and a source of the thirteenth transistor (T1; Fig. 2) are both connected to the input terminal (Input1; Fig. 2) of the first GOA unit (11 and 14; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages), and a drain of the thirteenth transistor (T1; Fig. 2) is connected to a first pull-up node (Q1; Fig. 2);
a gate of the twenty-second transistor (T9; Fig. 2) is connected to the first pull-up node (Q1; Fig. 2), a source of the twenty-second transistor (T9; Fig. 2) is connected to the first clock signal terminal (CLK2; Fig. 2), and a drain of the twenty-second transistor (T9; Fig. 2) is connected to the output terminal (Output1; Fig. 2) of the first GOA unit (11 and 14; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages); and
a gate of the thirty-first transistor (T10; Fig. 2) and a gate of the forty-third transistor (T3; Fig. 2) are connected to the pull-down terminal (Q2; Fig. 2) of the first GOA unit (11 and 14; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages), a source of the thirty-first transistor (T10; Fig. 2) and a source of the forty-third transistor (T3; Fig. 2) are connected to a constant voltage low potential (V1; Fig. 2), a drain of the thirty-first transistor (T10; Fig. 2) is connected to the output terminal (Output1; Fig. 2) of the first GOA unit (11 and 14; Fig. 2) of the n- th stage GOA module (Fig. 4; wherein figure shows a plurality of stages), and a drain of the forty-third transistor (T3; Fig. 2) is connected to the first pull-up node (Q1; Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Tseng’s gate driving circuit by applying a first GOA unit, as taught by Zhang, so to use a gate driving circuit with a first GOA unit for providing the gate driving signal and the reset signal of the pixel electrode through two circuits respectively, the display driving circuit and the display device according to the embodiments of the present disclosure may simplify the display driving circuit (Paragraph [0089]).
Claims 7 and 16, Zhang (Fig. 1-6) discloses wherein the pull-up unit (T7; Fig. 2) of the n-th stage GOA module (Fig. 4) comprises an eleventh transistor (T7; Fig. 2), a gate and a drain of the eleventh transistor (T7; Fig. 2) is connected to the input terminal (Input1; Fig. 2) of the first GOA unit (11 and 14; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages), and a drain of the eleventh transistor (T7; Fig. 2) is connected to pull-up terminals (Q3; Fig. 2) of the plurality of second GOA units (T12; Fig. 2) of the n-th stage GOA module (Fig. 4; wherein figure shows a plurality of stages).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Tseng’s gate driving circuit by applying a first GOA unit, as taught by Zhang, so to use a gate driving circuit with a first GOA unit for providing the gate driving signal and the reset signal of the pixel electrode through two circuits respectively, the display driving circuit and the display device according to the embodiments of the present disclosure may simplify the display driving circuit (Paragraph [0089]).
Claims 5, 6, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al (US 2013/0135284 A1) in view of Kim et al (US 2007/0104307 A1).
Claims 5 and 14, Tseng discloses the GOA circuit according to claim 3 and the display panel according to claim 12.
Tseng does not expressly disclose wherein any second GOA unit of the second GOA units of the n-th stage GOA module comprises a twenty-first transistor, a thirty-second transistor, a forty-second transistor, and an inverter, and
wherein a gate of the twenty-first transistor is connected to a pull-up terminal of the second GOA unit of the n-th stage GOA module, a drain of the forty-second transistor, and an input terminal of the inverter, a source of the twenty-first transistor is connected to the second clock signal terminal, and a drain of the twenty-first transistor is connected to the output terminal of the any second GOA unit of the n-th stage GOA module; and
a gate of the thirty-second transistor and a gate of the forty-second transistor are connected to an output terminal of the inverter, a source of the thirty-second transistor and a source of the forty-second transistor are connected to a constant voltage low potential, a drain of the thirty-second transistor is connected to the output terminal of the any second GOA unit of the n-th GOA module, and a drain of the forty-second transistor is connected to the pull-up terminal of the second GOA unit of the n-th GOA module.
Kim (Fig. 2-45) discloses wherein any second GOA unit (ST3502; Fig. 35; ST3802 and ST3803; Fig. 38; wherein figure shows embodiments in which the multiple stages are connected to the same input signal and the first stage is output to the next first stage; therefore the Examiner is reading the stage ST3502 in figure 35 and the stages ST3802 and ST3803 in figure 38 as the second GOA unit) of the second GOA units (ST3507; Fig. 37) of the n-th stage GOA module (Fig. 37) comprises a twenty-first transistor (Tru; Fig. 37), a thirty-second transistor (Trd2; Fig. 37), a forty-second transistor (Tr3; Fig. 37), and an inverter (Fig. 37; wherein figure shows elements Tr5, Tr6, Tr7, and Tr9 arranged in the same configuration as shown in Applicant’s Figure 5 elements T51, T52, T53, and T54), and
wherein a gate of the twenty-first transistor (Tru; Fig. 37) is connected to a pull-up terminal (Q; Fig. 37) of the second GOA unit (ST3504; Fig. 37) of the n-th stage GOA module (Fig. 37), a drain of the forty-second transistor (Tr3; Fig. 37), and an input terminal of the inverter (Fig. 37; wherein figure shows gate electrodes of Tr6 and Tr9 being connected to node Q which is the same configuration as shown in Applicant’s Figure 5 elements T52 and T54), a source of the twenty-first transistor (Tru; Fig. 37) is connected to the second clock signal terminal (CLK4; Fig. 37), and a drain of the twenty-first transistor (Tru; Fig. 37) is connected to the output terminal (to fourth gate line; Fig. 37) of the any second GOA unit (ST3504; Fig. 37) of the n-th stage GOA module (Fig. 37); and
a gate of the thirty-second transistor (Trd2; Fig. 37) and a gate of the forty-second transistor (Tr3; Fig. 37) are connected to an output terminal (Fig. 37; wherein figure shows electrodes of Tr7 and Tr9 being connected to node QB2 which is the same configuration as shown in Applicant’s Figure 5 elements T53 and T54) of the inverter (Fig. 37; wherein figure shows elements Tr5, Tr6, Tr7, and Tr9 arranged in the same configuration as shown in Applicant’s Figure 5 elements T51, T52, T53, and T54), a source of the thirty-second transistor (Trd2; Fig. 37) and a source of the forty-second transistor (Tr3; Fig. 37) are connected to a constant voltage low potential (Vdc2; Fig. 37), a drain of the thirty-second transistor (Trd2; Fig. 37) is connected to the output terminal (to fourth gate line; Fig. 37) of the any second GOA unit (ST3504; Fig. 37) of the n-th GOA module (Fig. 37), and a drain of the forty-second transistor (Tr3; Fig. 37) is connected to the pull-up terminal (Q; Fig. 37) of the second GOA unit (ST3504; Fig. 37) of the n-th GOA module (Fig. 37).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Tseng’s gate driving circuit by applying a circuit arranged of second gate driving circuit, as taught by Kim, so to use a gate driving circuit with a circuit arranged of second gate driving circuit for providing a shift register having a reduced number of switching devices to reduce the size and manufacturing cost of the shift register (Paragraph [0017]).
Claims 6 and 15, Kim (Fig. 2-45) discloses wherein the inverter (Fig. 37; wherein figure shows elements Tr5, Tr6, Tr7, and Tr9 arranged in the same configuration as shown in Applicant’s Figure 5 elements T51, T52, T53, and T54) comprises a fifty-first transistor (Tr5; Fig. 37), a fifty-second transistor (Tr6; Fig. 37), a fifty-third transistor (Tr7; Fig. 37), and a fifty-fourth transistor (Tr9; Fig. 37), and
wherein a gate and a source of the fifty-first transistor (Tr5; Fig. 37) are connected to a low frequency control signal (Vac2; Fig. 37; Paragraph [0080]; wherein discloses voltage source that varies from frame to frame), and a drain of the fifty-first transistor (Tr5; Fig. 37), a drain of the fifty-second transistor (Tr6; Fig. 37) and a gate of the fifty-third transistor (Tr7; Fig. 37) are connected (Node N; Fig. 37);
a gate of the fifty-second transistor (Tr6; Fig. 37) and a gate of the fifty-fourth transistor (Tr9; Fig. 37) are connected to the pull-up terminal CQ(n) (Q; Fig. 37) of the second GOA unit (ST3504; Fig. 37), and a source of the fifty-second transistor (Tr6; Fig. 37) and a source of the fifty-fourth transistor (Tr9; Fig. 37) are connected to the constant voltage low potential (Vdc2; Fig. 37); and
a source of the fifty-third transistor (Tr7; Fig. 37) is connected to a low frequency control signal (Vac2; Fig. 37), and a drain of the fifty-third transistor (Tr7; Fig. 37) and a drain of the fifty-fourth transistor (Tr9; Fig. 37) are connected with each other (QB2; Fig. 37) and connected to the output terminal (QB2; Fig. 37) of the inverter (Fig. 37; wherein figure shows elements Tr5, Tr6, Tr7, and Tr9 arranged in the same configuration as shown in Applicant’s Figure 5 elements T51, T52, T53, and T54).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Tseng’s gate driving circuit by applying a circuit arranged of second gate driving circuit, as taught by Kim, so to use a gate driving circuit with a circuit arranged of second gate driving circuit for providing a shift register having a reduced number of switching devices to reduce the size and manufacturing cost of the shift register (Paragraph [0017]).
Response to Arguments
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
With respect to claims 1 and 10, the Applicant argued in the submitted response on pages 10-12, that the cited prior art reference does not teach the output terminal feature (Feature 3) of the claimed limitation.
The Examiner respectfully disagrees with this argument. Specifically the Claim states that an output terminal of the current first GOA unit is both connected to the input terminal of the next first GOA and the pull down terminal of a previous first GOA unit. To better point to this element the Examiner pointed to the Figure 3 of Tseng et al (US 2013/0135284 A1) shown below:
PNG
media_image1.png
736
528
media_image1.png
Greyscale
Wherein the rejection was “the output terminal (OT1; Fig. 5) of the first GOA unit (501; Fig. 5) of the n-th stage GOA module (311; Fig. 3) is connected to the input terminal (IN1; Fig. 5) of the first GOA unit (501; Fig. 5) of an (n+ 1)-th stage GOA module (313; Fig. 3) and the pull-down terminal (IN2; Fig. 5) of the first GOA unit (501; Fig. 5) of the (n-1)-th stage GOA module (305; Fig. 3);”. Wherein the Examiner highlighted the current stage first GOA (SR1) 311, the next stage first GOA (SR1) 313, and the previous stage first GOA (SR1) 305. The output terminal OT1 in figure 5 is shown to be k[N+9] in figure 3 for current stage first GOA (SR1) 311. The input terminal IN1 figure 5 is shown to be k[N+9] in figure 3 for the next stage first GOA (SR1) 313. The pull down terminal IN2 figure 5 is shown to be k[N+9] in figure 3 for the previous stage first GOA (SR1) 305. Therefore based on this understanding the Examiner maintains the rejection that the prior art reference of Tseng shows an output terminal of a current stage is connected to the input terminal of the next stage and the previous stage.
the Applicant further argued in the submitted response on pages 12-14, that the cited prior art reference does not teach the pull-down feature (Feature 4) of the claimed limitation.
The Examiner respectfully disagrees with this argument. Specifically the Claim states that an pull-down terminal (IN2; Fig. 5) of the current first GOA stage (305; Fig. 3) is connected to the output terminal (OT1; Fig. 5) of the next first GOA stage (311; Fig. 3), and that the output terminal (OT1; Fig. 5) of the next first GOA stage (311; Fig. 3) is configured to pull-down both the input terminal and the output terminals of current second GOA stage (305; Fig. 3) through the pull down unit of the current GOA stage.
Look at the Applicant’s figure 5 which shows the pull-down unit (T41; Fig. 3) of the current stage to pull down CQ(n) and G(n), and figure 6 further shows pull down signal applied to transistor T41 which then controls the inverter (30) so that it can control transistors T42 and T32. Now looking at the prior art reference of Tseng in figure 5 which is shown below:
PNG
media_image2.png
502
791
media_image2.png
Greyscale
Wherein highlighted figure 5 shows the pull-down unit (M2; Fig. 5) being controlled by the signal received at the pull-down terminal (IN2; Fig. 5) so that pull down control unit (580; Fig. 5) can control of voltage node A(N) which then controls the pull down of node B2(N) and the pull-down of output terminals (OUT1-OUT3; Fig. 5) as required by the current claims. Therefore based on this understanding the Examiner maintains the rejection that the prior art reference of Tseng shows a pull-down unit of a current stage used to pull-down the input terminal and the output terminals of the second GOA units as claimed.
With respect to dependent claims 2-9 and 11-18, the Examiner maintains the rejection of the previous office action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Adam J Snyder/ Primary Examiner, Art Unit 2623 03/09/2026