DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are pending in this office action.
Claims 1-6 are amended.
Response to Arguments
Applicant's arguments filed 10/03/2025 have been fully considered but they are not persuasive.
Amendment to the specification(abstract) is accepted and made of record.
The rejection under 35 USC 101 abstract idea.
The double patenting rejection is still maintained.
Applicant’s argument:
Applicant respectfully disagrees with the grounds of rejection. In element 12 in FIG. 3 of Masaki, the process corresponding to "MOD (N, 4)" is executed independently, separate from loop processing, and does not teach or suggest "one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number" in claim 1.
Moreover, Masaki does not disclose "a sum of the remainder and the designated unroll stage number," as further recited in claim 1.
Additionally, none of the other cited references, nor any combination thereof, remedy the deficient teachings of Masaki. Therefore, claim 1 is patentable for at least these reasons.
Examiner response:
The issue in the argument is that art of record fail to discloses executing the loop with unrolling factor equal to sum of the remainder and the designated unroll stage number as a unroll stage number. For example, in fig. 3 of the else statement add the a statement to the loop stage that is 4, become 5 by adding an extra statement to the statements.
Masaki first check the remainder of if is not zero, and if the determination is positive(remainder>0) the statement is added as a loop body. When unrolling is performed, it is determined in processing step whether the number of repetitions specified is a constant, and if it is a constant, it is determined in processing step whether there is a fraction that is the remainder of dividing the number of repetitions by n, and if there is a fraction, adds the number of vector operation sequences corresponding to the fraction. the number of operations corresponding to the fraction, and the unrolling process for this loop is completed. This result into increasing the length of one pass of the loop times and reduce the number of iterations, thereby increasing the range in which vector instructions can be executed continuously.
Because the number of times the original loop is executed is not always divisible by the unroll factor, a compensation loop/code often has to be generated to execute the remaining of instructions of the original loop that are not executed by the unrolled loop.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "…specified by the specification unit…" in line 12 There is insufficient antecedent basis for this limitation in the claim.
Independents claims2-4 inherits the same deficiency of claim 1 and also rejected under the same rationale.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12,093,691 Although the claims at issue are not identical, they are not patentably distinct from each. Mapping of independents claim is as follow where corresponding limitations have same cues:
Application 17/795,946
Patent:12,093,691
1. A loop unrolling processing apparatus comprising:
at least one processor configured to execute:
a specification configured to specify a description part of an arithmetic expression that represents loop processing from an input source program;
a generation unit configured to generate arithmetic expressions that represent executing,
In case where a remainder in case where dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number,
and executing loop processing with the designated unroll stage number after the processing of one loop;
and a replacement unit configured to replace the arithmetic expression of the description part specified by the specification unit with the arithmetic expressions generated by the generation unit to decrease the number of looping times;
1.A loop unrolling processing apparatus comprising:
And a processor configured to execute the instructions to
specify a description part of an arithmetic expression that represents loop processing from an input source program;
generate arithmetic expression, wherein the arithmetic expression include:
arithmetic expression that represents executing the loop processing whose number of looping times is a quotient obtained by dividing R by (M-L), with the unroll stage number M when R-Q*(M-L)>0 is not satisfied, and then executing, when a remainder obtained by dividing R by (M-L) is other than 0, processing of one loop with sum of the remainder and L as the unroll stage number,
and then executing loop processing with the unroll stage number L,
replace the arithmetic expression of the specified description part with the generated arithmetic expressions generated
Independent claim 5
Independent claim 3
Impendent claim 6
Impendent claim 4
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al US20100107147A1 in view of Masaki et al JP S63-314675 A .
As per claim 1, Cha discloses a loop unrolling processing apparatus comprising:
at least one processor configured to execute:
a specification configured to specify a description part of an arithmetic expression that represents loop processing from an input source program:
[0026] The analyzer 122 analyzes intermediate codes of a source application in order to perform various optimization procedures to improve run-time performance of a program generated by the compiler 100. According to some implementations, the analyzer 122 analyzes intermediate codes to generate a data dependence graph (DDG) for a loop unrolled instructions”; Fig. 2A include a loop with an arithmetic expression”
[0038] Referring to FIG. 2A, a simple program loop is shown in a block 210. An instruction "a[i]=b[i]+c[i]" in the loop 210 can be represented by an assembly code 220 that is to be executed in a target machine.”
a generation unit configured to generate arithmetic expressions that represent executing:
[0027] “The unroller 124 determines the number of optimized loop unrolling times that improves program performance, and performs loop unrolling based on the determined number of optimized loop unrolling times. When source codes are transformed into machine codes by a compiler, for example, a DO loop, a WHILE loop, and a FOR loop are included. When compilation of these loops is optimized, run-time performance of a program generated by a compiler can be significantly improved. Loop unrolling is used to optimize processing of the loops”;
[0039] When loop unrolling is performed twice, the assembly code 220 is represented in order of the instruction {circle around (1)}, the instruction {circle around (2)}, the instruction {circle around (3)}, the instruction {circle around (4)}, an instruction {circle around (5)}, an instruction {circle around (6)}, an instruction {circle around (7)}, and an instruction {circle around (8)} as shown in a block 230.
and executing loop processing with the designated unroll stage number after the processing of one loop:
[0034]”To this end, the unroller 124 allocates an unroll_group_number, which is given based on an order in which a loop body is replicated by loop unrolling, in units of loop bodies. The unroller 124 can add an unroll_group_number to each instruction included in a loop body so that an unroll_group_number can be reflected when the instruction scheduler 126 determines a priority of each instruction.
and a replacement unit configured to replace the arithmetic expression of the description part specified by the specification unit with the arithmetic expressions generated by the generation unit:
[0027] “The unroller 124 determines the number of optimized loop unrolling times that improves program performance, and performs loop unrolling based on the determined number of optimized loop unrolling times. When source codes are transformed into machine codes by a compiler, for example, a DO loop, a WHILE loop, and a FOR loop are included. When compilation of these loops is optimized, run-time performance of a program generated by a compiler can be significantly improved. Loop unrolling is used to optimize processing of the loops”; Fig. 2A block 230 replaces block 210 during execution.
to decrease the number of looping times:
[0037]” Therefore, a probability that a register spill occurs is decreased, whereby the number of memory access times is decreased, and an execution time of a compiled program, power consumption and the program size can be decreased”.
But not explicitly:
In a case where a remainder in a case where dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number
Masaki discloses:
In a case where a remainder in a case where dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number:
page 5 first paragraph: “generate a program with the same configuration as the loop, which executes the loop a number of times equal to the remainder of the number of iterations of the loop, and is expanded into a program corresponding to n repetitions, and a loop program with the number of repetitions set to 1/n is generated as a program following the generated program.”;
page 6 paragraph[8]” In processing step 23, it is determined whether the number of repetitions is a constant, and if it is a constant, it is determined in processing step 24 whether there is a remainder after dividing the number of repetitions by n. If there is no fraction, the process ends, and if there is a fraction, processing step 25 After the loop, add the number of vector operations corresponding to the fraction and complete the process.”;
Examiner interpretation:
the remainder(MOD(number of iteration, n)) of dividing number of iteration to the unrolling factor n is added(as instruction) to the loop body after expansion as shown in 12 fig. 3
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Masaki into teachings of Cha to reduce or minimize a register spill that can be generated during instruction scheduling for an unrolled loop in a compiler. The compiler 100 performs instruction scheduling in consideration of optimization of an unrolling step, thereby performing efficient compiling [Cha 0033].
As per claim 5, cha discloses a loop unrolling processing method comprising: specifying a description part of an arithmetic expression that represents loop processing from an input source program:
[0026]”The analyzer 122 analyzes intermediate codes of a source application in order to perform various optimization procedures to improve run-time performance of a program generated by the compiler 100. According to some implementations, the analyzer 122 analyzes intermediate codes to generate a data dependence graph (DDG) for a loop unrolled instructions”;
[[0038] Referring to FIG. 2A, a simple program loop is shown in a block 210. An instruction "a[i]=b[i]+c[i]" in the loop 210 can be represented by an assembly code 220 that is to be executed in a target machine.”
generating arithmetic expressions that represent executing:
[0027] “The unroller 124 determines the number of optimized loop unrolling times that improves program performance, and performs loop unrolling based on the determined number of optimized loop unrolling times. When source codes are transformed into machine codes by a compiler, for example, a DO loop, a WHILE loop, and a FOR loop are included. When compilation of these loops is optimized, run-time performance of a program generated by a compiler can be significantly improved. Loop unrolling is used to optimize processing of the loops”;
[0039] When loop unrolling is performed twice, the assembly code 220 is represented in order of the instruction {circle around (1)}, the instruction {circle around (2)}, the instruction {circle around (3)}, the instruction {circle around (4)}, an instruction {circle around (5)}, an instruction {circle around (6)}, an instruction {circle around (7)}, and an instruction {circle around (8)} as shown in a block 230.
and executing loop processing with the designated unroll stage number after the processing of one loop:
[0034]”To this end, the unroller 124 allocates an unroll_group_number, which is given based on an order in which a loop body is replicated by loop unrolling, in units of loop bodies. The unroller 124 can add an unroll_group_number to each instruction included in a loop body so that an unroll_group_number can be reflected when the instruction scheduler 126 determines a priority of each instruction.
and replacing the arithmetic expression of the description part with the generated arithmetic expressions:
[0027]“The unroller 124 determines the number of optimized loop unrolling times that improves program performance, and performs loop unrolling based on the determined number of optimized loop unrolling times. When source codes are transformed into machine codes by a compiler, for example, a DO loop, a WHILE loop, and a FOR loop are included. When compilation of these loops is optimized, run-time performance of a program generated by a compiler can be significantly improved. Loop unrolling is used to optimize processing of the loops”;
[0039] When loop unrolling is performed twice, the assembly code 220 is represented in order of the instruction {circle around (1)}, the instruction {circle around (2)}, the instruction {circle around (3)}, the instruction {circle around (4)}, an instruction {circle around (5)}, an instruction {circle around (6)}, an instruction {circle around (7)}, and an instruction {circle around (8)} as shown in a block 230.
Examiner interpretation:
block of arithmetic expression 230 of fig. 2A replaces block of arithmetic expression 210 withing the body of the loop subjected to unrolling.
But not explicitly:
In a case where a remainder in a case where a dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number to decrease the number of looping times;
Masaki discloses:
In a case where a remainder in a case where a dividing the number of looping times of the loop processing by a designated unroll stage number is other than 0, processing of one loop with a sum of the remainder and the designated unroll stage number as a unroll stage number:
page 5 first paragraph: “generate a program with the same configuration as the loop, which executes the loop a number of times equal to the remainder of the number of iterations of the loop, and is expanded into a program corresponding to n repetitions, and a loop program with the number of repetitions set to 1/n is generated as a program following the generated program.”;
page 6 paragraph[8]” In processing step 23, it is determined whether the number of repetitions is a constant, and if it is a constant, it is determined in processing step 24 whether there is a remainder after dividing the number of repetitions by n. If there is no fraction, the process ends, and if there is a fraction, processing step 25 After the loop, add the number of vector operations corresponding to the fraction and complete the process.”;
Examiner interpretation:
the remainder(MOD(number of iteration, n)) of dividing number of iteration to the unrolling factor n is added to the loop body after expansion as shown in 12 fig. 3
to decrease the number of looping times:
[0037]” Therefore, a probability that a register spill occurs is decreased, whereby the number of memory access times is decreased, and an execution time of a compiled program, power consumption and the program size can be decreased”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Masaki into teachings of Cha to reduce or minimize a register spill that can be generated during instruction scheduling for an unrolled loop in a compiler. The compiler 100 performs instruction scheduling in consideration of optimization of an unrolling step, thereby performing efficient compiling [Cha 0033].
Claim 6 is non-transitory computer-readable recording medium claim corresponding to method claim 5 and rejected under the same rational set forth in connection with the rejection of claim 5 above.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al US20100107147A1 in view of Masaki et al JP S63-314675 and Nguyen et al US6035125B1.
As per claim 2, the rejection of claim 1 is incorporated and furthermore Cha does not explicitly disclose:
wherein the generation unit generates, in a case where the number of looping times of the loop processing described in the input source program is less than the designated unroll stage number, the arithmetic expressions that include an arithmetic expression that represents loop processing same as the loop processing.
Nguyen discloses:
wherein the generation unit is configured to generate, in a case where the number of looping times of the loop processing described in the input source program is less than the designated unroll stage number, the arithmetic expressions that include an arithmetic expression that represents loop processing same as the loop processing.
Col 2 lines 39-45 “The first major step is to expand the separate unrolled loop body by the specified unroll factor UF[j]. The second major step is to adjust the loop header for the current loop. If the loop's iteration count, COUNT[j], is known to be less than or equal to the unroll factor, UF[j], then the loop header is simply an assignment of the index variable to the lower-bound expression;”
Examiner interpretation:
The loop is a set of arithmetic expression as shown in table A, table B or Table C in Col 3, 4 and 5.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Nguyen into teachings of Cha and Masaki to reduce or minimize the proportion of the object code comprising lower frequency execution remainder loops, substantially reduces the compile-time of unrolled multiple nested loops and reducing the code size that results after the unrolling transformation is performed.[Nguyen col 2 lines 25-32].
As per claim 3, the rejection of claim 1 is incorporated and furthermore Cha does not explicitly disclose:
wherein the generation unit is configured to generate, in case where the the number of looping times of the loop processing described in the input source program is less than the designated unroll stage number, the arithmetic expressions that include an arithmetic expression that represents processing of one loop with the number of looping times as the unroll stage number.
Nguyen discloses:
wherein the generation unit is configured to generate, in case where the the number of looping times of the loop processing described in the input source program is less than the designated unroll stage number, the arithmetic expressions that include an arithmetic expression that represents processing of one loop with the number of looping times as the unroll stage number.
Col 2 lines 42-52 “. If the loop's iteration count, COUNT[j], is known to be less than or equal to the unroll factor, UF[j], then the loop header is simply an assignment of the index variable to the lower-bound expression; otherwise, the loop header is adjusted so that the unrolled loop's iteration count equals .left brkt-bot.COUNT[j]/UF[j].right brkt-bot., a rounded down truncation of the division. The third major step is to generate a remainder loop nest, if needed. The body of the remainder loop nest is a single copy of the input loop body. The body of the remainder loop is a cross product of unrolled copies from loops 1 . . . j-1 and single copies from loops j . . . k. The remainder loop is not created if it is determined at compile time that the loop length COUNT[j] is a multiple of the unroll factor UF[j].”;
Examiner interpretation:
The loop is a set of arithmetic expression as shown in table A, table B or Table C in Col 3, 4 and 5.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Nguyen into teachings of Cha and Masaki to reduce or minimize the proportion of the object code comprising lower frequency execution remainder loops, substantially reduces the compile-time of unrolled multiple nested loops and reducing the code size that results after the unrolling transformation is performed.[Nguyen col 2 lines 25-32].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cha et al US20100107147A1 in view of Masaki et al JP S63-314675 and Ogawa et al US20060080642A1.
As per claim 4, the rejection of claim 1 is incorporated and furthermore Cha discloses:
wherein the generation unit is configured to accept designation of the unroll stage number:
[0011] “In another general aspect, a compiling method includes analyzing intermediate codes of a source application, performing loop unrolling, and allocating an unroll_group_number in units of loop bodies during the loop unrolling in an order in which a loop body is replicated by the loop unrolling, and scheduling instructions based on the unroll_group_number”;
[0034]“To this end, the unroller 124 allocates an unroll_group_number, which is given based on an order in which a loop body is replicated by loop unrolling, in units of loop bodies. The unroller 124 can add an unroll_group_number to each instruction included in a loop body so that an unroll_group_number can be reflected when the instruction scheduler 126 determines a priority of each instruction”;
But not explicitly:
the unroll stage number is according to a predetermined format described in the input source program;
Ogawa discloses:
the unroll stage number is according to a predetermined format described in the input source program;
[0203] “A pragma "#pragma_loop_unrolling", which is the hint information as described above, that specifies loop unrolling, is a directive given by the user to the compiler to perform the loop unrolling optimization for the loop process (e.g. "for", "while" and "do") that follows immediately after the description of the pragma. For example, the pragma "#pragma_loop_unrolling" is written in the function "func1" of the program 101, and it is instructed by the user to perform loop unrolling on the for-loop process that follows immediately after the description of the pragma. Here, the number of iterations for unrolling should be 2”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Ogawa into teachings of Cha and Masaki to reduce or minimize the proportion of the object code comprising lower frequency execution remainder loops, substantially reduces the compile-time of unrolled multiple nested loops and reducing the code size that results after the unrolling transformation is performed.[Nguyen col 2 lines 25-32].
Pertinent arts
US9038042B2:
A loop-count register may store a loop count, which may be derived from a total loop count divided by a number of processing elements to use in executing the loop instructions and adjusted in accordance with a stage count and rounded in accordance with a loop-unroll factor.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAHIM BOURZIK whose telephone number is (571)270-7155. The examiner can normally be reached Monday-Friday (8-4:30).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Y Mui can be reached at 571-270-2738. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRAHIM BOURZIK/Examiner, Art Unit 2191 /WEI Y MUI/Supervisory Patent Examiner, Art Unit 2191
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