Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/28/2022, 12/13/2023, and 11/10/2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements mentioned above, all portions which have not been struck out, are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “rotation operation on the plurality of elements of the output register in which the sum of the result value and a value present in the second end element before said rotation is placed in the first end element of the output register” must be shown or the feature(s) canceled from the claim(s). The Examiner notes that there are many other claimed features not shown in the drawings dated 11/10/2025, as well as many components and features in these drawings which are not described in the specification nor claims. The Examiner notes that the applicant seemingly added a wrong drawing set, dated 11/10/2025, which appears to belong to a different application. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, and 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, claim 2 recites the limitation of: “wherein the vector unit is configured to perform said processing i) of the first input vector and second input vector by performing a multiply accumulate operation on the input vectors”. It is unclear if the “i)” in the claim limitation is meant to be understood as a step being taken as part of claim 2, if it is meant to reference back to the claim 1 step i), or if it is simply a typographical error. For purposes of examination, the Examiner interprets the claim limitation to be: “wherein the vector unit is configured to perform said processing ”.
Regarding claim 5, claim 5 recites the limitation of: “wherein the vector processing instruction includes an operated specifying the input register”. From this claim limitation it is unclear if the vector processing instruction performs an operation specifying the input register, or if there is another “operated” component which was omitted from the claim limitation. For purposes of examination, the Examiner interprets the limitation as: “wherein the vector processing instruction includes an operation specifying the input register”.
Regarding claim 13, claim 13 recites the limitation of: “A computer system comprising the processing unit according to claim 1, programmed to perform the method according to claim 9.” A single claim which recites both an apparatus and method steps is indefinite. See MPEP 2173.05(p)(II).
Allowable Subject Matter
Claims 1, 3, 4, and 6-12 are allowed.
Claims 2, 5, and 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claim 1, the applicant claims a processing unit for processing an output vector, the processing unit of claim 1 comprising:
an output register having a plurality of elements for holding different components of the output vector, the plurality of elements including a first end element and a second end element; and a vector unit for processing at least two input vectors to generate respective result values; wherein the processing unit is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit, wherein the instruction set includes a vector processing instruction defined by a corresponding opcode, the vector processing instruction causing the processing unit to: i) process, using the vector unit, a first input vector and a second input vector to generate a result value; ii) perform a rotation operation on the plurality of elements of the output register in which the sum of the result value and a value present in the second end element before said rotation is placed in the first end element of the output register.
With regards to claim 9, the applicant claims a method performed by a processing unit for processing an output vector, the method of claim 9 comprising:
generating an output vector at an output register having a plurality of elements for holding different components of the output vector, the plurality of elements including a first end element and a second end element, wherein the processing unit is configured to execute machine code instructions, each instruction being an instance of a predefined set of instruction types in an instruction set of the processing unit, wherein the instruction set includes a vector processing instruction defined by a corresponding opcode, the method comprising the vector processing instruction causing the processing unit to implement a vector processing operation of: i) processing, using the vector unit, a first input vector and a second input vector to generate a result value; and ii) performing a rotation operation on the plurality of elements of the output register in which the sum of the result value and a value present in the second end element before said rotation is placed in the first end element of the output register.
The primary reason for indication of allowable subject matter is the above italicized claim limitations in combination with the remaining claim limitations including intervening claims.
Moudgill, (WO 2009/073787 A1), hereinafter “Moudgill”, teaches a processing circuit which computes multiply sum operations [0064], and which allows the processor to perform register shift or rotate operations [0003], and [0040]. However, Moudgill is silent with respect to the above highlighted limitation in combination with the remaining limitations.
Chua et al., (U.S. Patent application publication 2009/0248769 A1), hereinafter “Chua”, teaches a multiply accumulate engine which has registers performing rotation operations (see figures 2, and 7). However, Chua is silent with respect to the above highlighted limitation in combination with the remaining limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME ANTHONY KLOSTERMAN II whose telephone number is (571)272-0541. The examiner can normally be reached Monday- Friday 8:30am - 3:30pm ET.
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/J.A.K./Examiner, Art Unit 2182 /EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182