DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is FINAL and is in response to the amendment filed March 19th, 2026. Claims 1-13 are pending, of which claims 1-12 are currently rejected, and claim 12 is objected to.
Response to Arguments
The amendment filed March 19th, 2026 has been entered. Claims 1-13 remain pending in the application. Applicant’s amendments to the Claims have overcome every objection, and 112(b) rejection previously set forth in the Non-Final Office Action mailed December 29th, 2025.
Specification Objections
Applicant has amended the title and this new title is sufficient. Additionally, Applicant has amended the specification and resolved the previous objection to the specification. Therefore, the objection to the specification has been withdrawn.
Claim Objections
Applicant has amended claims and resolved the previous claim objections. Therefore, the previous claim objections have been withdrawn.
Claim Rejections – 35 USC § 112
Applicant has amended claims and resolved the antecedent basis issues. Therefore, the previous rejections under 35 U.S.C. 112(b) have been withdrawn.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are not persuasive.
Specifically on Pg. 9 of Applicant’s Remarks, Applicant alleges that Almahali et al. ("FPGA-Accelerated Hadoop Cluster for Deep Learning Computations", 2015) included in the IDS filed on 07/29/2022 (hereinafter “Almahali”), excludes the use of fixed hardware configuration and a computing node.
Examiner respectfully disagrees. While Almahali emphasizes the use of FPGA’s (Almahali: Pg. 565), Almahali explicitly states that the use of the FPGA’s are used for acceleration purposes. Additionally, as can be seen in Figure 2 (Pg. 570), the entire computing node has only one portion of it that is reconfigurable, the Partial Reconfigurable Region. The rest of the computing node is in fact fixed. Furthermore, in Fig. 3 (Pg. 571), within the Mapper block and with regards to the Mapper() function it can be seen that some of the processing may be done by an FPGA-based node (not all nodes are FPGA-based as further discussed on Pg. 570 discussion of Fig. 3 Point 4 and continued onto Col 2 Lines 1-3), while other processing may be done by the CPU i.e., the fixed circuitry. Therefore, Almahali does in fact include fixed hardware configuration and a computing node.
New reasons of rejection have been made by Examiner that are necessitated by the amendments. See Claim Rejections - 35 USC § 103 and Claim Rejections - 35 USC § 102.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by A. Almahali et al. ("FPGA-Accelerated Hadoop Cluster for Deep Learning Computations", 2015) included in the IDS filed on 07/29/2022 (hereinafter “Almahali”).
Regarding claim 1, Almahali teaches:
An information processing circuit comprises:
a first information processing circuit, having a fixed circuit configuration in hardware, that performs layer operations in deep learning (CNN comprised of FPGA-accelerated and non-accelerated computation nodes, the various nodes labeled as Mapper (as first and second information processing circuits) being used for layer operations in deep learning, shown in Pg. 571 Fig. 4 and discussed on Pg. 570 Col. 2 section B having as outputs trained weight parameters, FPGA as programmable accelerator; Pg. 566 Col. 1 third paragraph CNN operations run on various computing nodes within the network of nodes, i.e., the circuitries as discussed with respect to Fig. 4);
a second information processing circuit that performs the layer operations in deep learning on input data by means of a programmable accelerator (CNN comprised of FPGA-accelerated and non-accelerated computation nodes, the various nodes labeled as Mapper (as first and second information processing circuits) being used for layer operations in deep learning, shown in Pg. 571 Fig. 4 and discussed on Pg. 570 Col. 2 section B having as outputs trained weight parameters, FPGA as programmable accelerator; Pg. 566 Col. 1 third paragraph CNN operations run on various computing nodes within the network of nodes, i.e., the circuitries as discussed with respect to Fig. 4; Pg. 570 Fig. 3 additionally shows the hardware configuration); and
an integration circuit integrates a calculation result of the first information processing circuit with a calculation result of the second information processing circuit, and output an integration result (Pg. 571 Fig. 4 Reducer as integration circuit, takes calculation results from 1st and 2nd info processing circuits and produces an integration result, also discussed on Pg. 571 Col.2 Section B; Pg. 570 Fig. 3 additionally shows the hardware configuration), wherein the first information processing circuit includes:
a parameter value output circuit in which parameters of deep learning are circuited (Pg. 571 Fig. 5 shows kernel of FPGA convolutions, weights FIFO output as parameter value output circuit for directing of CNN weights i.e., parameters); and
a sum-of-product circuit that performs a sum-of-product operation using the input data and the parameters (Pg. 570 Col. 2 Section B Lines 16-19 reducer combines weights after training i.e., a sum; Pg. 571 Col. 2 Fig. 5 sum-of-products operations occurring with respect to weights i.e., parameters and input values; Pg. 571 Col. 1 last paragraph and Col. 2 first paragraph describe the sum-of-products circuitry).
Regarding claim 2, Almahali teaches:
The information processing circuit according to claim 1, wherein the integration circuit accepts the calculation results of the first information processing circuit and the second information processing circuit as inputs, integrates the calculation results by calculating a weighted sum of accepted inputs, and output the integration result (Pg. 571 Fig. 5 takes input of weights i.e., parameters from mappers to kernel depicted (this kernel occurring in reducer), and carries out a weighted sum to produce the integration result which is output to the results FIFO).
Regarding claim 3, Almahali teaches:
The information processing circuit according to claim 1, wherein the integration circuit accepts the calculation results of the first information processing circuit and the second information processing circuit as inputs to the layers in deep learning, and integrates the calculation results by performing a predetermined calculation using the calculation results, and outputs the integration result (Pg. 571 Col. 2 Section D computations carried out for layer of CNN for deep learning operations, outputting the calculation results as discussed in Pg. 571 Col.2 Section B).
Regarding claim 4, Almahali teaches:
The information processing circuit according to any one of claim 1, wherein the integration circuit performs layer operations in deep learning by means of another programmable accelerator (Pg. 570 Col. 2 section B, FPGA as programmable accelerator for layer operations in deep learning).
Regarding claim 5, Almahali teaches:
The information processing circuit according to any one of claim 1, wherein the integration circuit inputs the same input data as the input data accepted by the first information processing circuit and the second information processing circuit, and weights calculation results of the first information processing circuit and the second information processing circuit based on weighting parameters determined according to the input data (Pg. 571 Fig. 5 shows kernel of FPGA convolutions, weights FIFO output as parameter value output circuit for directing of CNN weights i.e., parameters as determined by training via first and second processing circuits (nodes/Mappers), weighted sum carried out with respect to weights and inputs from the Image FIFO output, the image data as input data that was also used to train the weight data, as such it was input to the Mapper nodes i.e., first and second processing circuits).
Claims 9-10 recite the method practiced by the information processing circuit of claims 1-2 respectively and are therefore rejected for the same reasons therein.
Claims 11-12 recite the non-transitory computer readable recording medium storing a program executing deep learning with instructions to execute the method practiced by the information processing circuit of claims 1-2 respectively and are therefore rejected for the same reasons therein. Almahali additionally discloses a processor and memory, which can be used for storing program instructions to be carried out on the FPGA (Almahali: Pg. 570 Col 2 Section C and PG. 571 Col. 1 first paragraph).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Almahali further in view of Huang et al. (US 2020/0410337 A1) (hereinafter “Huang”).
Regarding claim 6, while Almahali teaches the information processing circuit according to claim 1, as well as a first and second information processing circuit for outputting respective calculation results in deep learning (Almahali: CNN comprised of computing nodes, the various nodes labeled as Mapper (as first and second information processing circuits) being used for layer operations in deep learning, shown in Pg. 571 Fig. 4 and discussed on Pg. 570 Col. 2 section B having as outputs trained weight parameters, FPGA as programmable accelerator; Pg. 566 Col. 1 third paragraph CNN operations run on various computing nodes within the FPGA, i.e., the circuitries as discussed with respect to Fig. 4) and an integration circuit for outputting an integration result (Almahali: Pg. 571 Fig. 4 Reducer as integration circuit, takes calculation results from 1st and 2nd info processing circuits and produces an integration result, also discussed on Pg. 571 Col.2 Section B; Pg. 570 Fig. 3 additionally shows the hardware configuration), Almahali does not explicitly teach these operations occurring in an intermediate layer for an intermediate layer.
However, Huang teaches neural network with multiple processing nodes including input layers, intermediate layers (hidden layers) and output layer, each of the layers carrying out sum of products operations (Huang: ¶ 0036). In combining Almahali with Huang, this would allow for all layers of deep learning of Almahali to have the same structure in order to carry out sum of products operations.
It would be obvious before the effective filing date of the claimed invention to combine the intermediate layers for sum of product operations as taught by Huang with the information processing circuit structure as taught by Almahali as both teachings are directed towards sum of product operations in a deep learning setting. One with ordinary skill in the art would be motivated to combine the teachings because this would allow for the circuit to take in many more inputs and carry out operations with many more weights than if the structure were only on one layer (Huang: ¶ 0036).
Almahali in view of Huang therefore teaches:
The information processing circuit according to claim 1,
wherein
the first information processing circuit outputs a calculation result of an intermediate layer in deep learning,
the second information processing circuit performs the layer operation in deep learning using the calculation result of the intermediate layer as input data; and
the integration circuit integrates the calculation result of the intermediate layer,
the calculation result of the first information processing circuit and the calculation result of the second information processing circuit,
and outputs the integration result.
Regarding claim 7, Almahali in view of Huang further teaches:
The information processing circuit according to claim 6,
wherein the first information processing circuit outputs an output from the intermediate layer that performs feature extraction as the calculation result (Huang: ¶ 0056 CNN operations at of the layers are used for extraction of features of input image).
It would be obvious before the effective filing date of the claimed invention to combine the feature extraction at an intermediate layer as taught by Huang with the information processing circuit structure as taught by Almahali as both teachings are directed towards sum of products operations for deep learning. One with ordinary skill in the art would be motivated to combine the teachings in order to be able to obtain an output feature map for neural network operations (Huang: ¶ 0056).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Almahali further in view of Wang et al. (US 2020/0334539) (hereinafter “Wang”).
Regarding claim 8, while Almahali teaches the information processing circuit according to claim 1, as well as a learning circuit for learning of parameters (Almahali: Pg. 572 Col. 1 Section B system is trained via MNIST learning system, MNIST classifies data based on labels, and this is used in order to train the network to train and learn parameters i.e., weights), Almahali does not explicitly teach the learning circuit correcting based on a difference between a calculation result and a correct answer label.
However, Wang teaches a calculation result is for a sum of products operation (Wang: ¶ 0098), and the difference between the predicted outcome i.e., calculation result and the label i.e., correct label answer is computed, tuning being carried out in order to training to be more accurate (Wang: ¶ 0078).
It would be obvious before the effective filing date of the claimed invention to combine the difference calculation in order to tune the learning of parameters as taught by Wang with the information processing circuit as taught by Almahali as both teachings are directed towards sum of products operations in deep learning. One with ordinary skill in the art would be motivated to combine the teachings because this would determine an accuracy of the neural network and training, and correct parameters appropriately (Wang: ¶ 0071).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant claims an information processing circuit as in claim 1 comprising:
a first information processing circuit, having a fixed circuit configuration in hardware, that performs layer operations in deep learning;
a second information processing circuit that performs the layer operations in deep learning on input data by means of a programmable accelerator; and
an integration circuit integrates a calculation result of the first information processing circuit with a calculation result of the second information processing circuit, and output an integration result,
wherein the first information processing circuit includes:
a parameter value output circuit in which parameters of deep learning are circuited; and
a sum-of-product circuit that performs a sum-of-product operation using the input data and the parameters.
Wherein claim 13 dependent on claim 1 further comprises:
the first information processing circuit is an inference unit with fixed operators corresponding to layers in deep earning and with fixed parameters,
the parameters of deep learning are fixedly configured in the first information processing circuit by the parameter value output circuit
the first information processing circuit includes a plurality of sum-of-product circuits each specializing in a corresponding layer operation, and
the second information processing circuit comprises an operator and an external memory configured to hold parameters to be used for the layer operations.
The specific reason for indication of allowable subject matter is the inclusion of a plurality of sum-of-product circuits in the first information processing circuit, each of the circuits specializing in a corresponding layer operation as well as the second information processing circuit comprising an operator with an external memory for holding of parameters. Almahali discloses the information processing circuit as in claim 1, but is silent as to the highlighted limitations. Similarly, Huang and Wang are silent as to the above highlighted limitations of claim 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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