The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Applicant’s amendments and remarks filed 2/9/26 are acknowledged. Claims 1 and 17 have been amended. Claims 1 – 27 are pending.
Response to Amendments / Arguments
Applicant's arguments regarding the amended claims versus the previously-raised rejections under 35 USC 103(a) have been fully considered but they are not persuasive. Furthermore, the arguments are moot in view of the new grounds of rejections, as necessitated by Applicant’s amendments. The new limitations in independent claims 1 and 17 define that a wafer with a single-piece semiconductor substrate has a diameter in the range from 50 mm to 600 mm. Accordingly, the Examiner applies a reference by Celler (US 2010/0295083 A1) lists the diameters of standard/commercial-grade silicon wafers.
Amended claims 1 and 17:
Applicant continues to assert that a reduced level of roughness of a planarization dielectric coat adjacent to a 2D material somehow improves modulation/detection efficiency of the 2D material interfacing such dielectric coat. In particular, Applicant alleges that “The invention is based on the insight that surface roughness impacts electro-optical efficiency. Contrary to the examiner's allegation, the present invention is not about avoiding optical loss in waveguides, but about optimizing modulation/detection efficiency, in other words, how much electrical signal is obtained from an optical input and how much optical signal for an electrical input” (para. bridging pp. 14 – 15 of the Remarks) and that “the present invention recited in claims 1 and 17 is not about optical losses. Rather, it enables the electro-optical device(s) (modulator(s)/detector(s)), having an improved modulation/detection efficiency. The invention is based on the insight that roughness can cause electronic degradation of the active element(s) with the above materials” (1st complete para. on p. 16).
The Examiner notes that Applicant’s assertions are inaccurate and not persuasive on multiple levels, both legal and technical, for at least the following reasons:
(i) As an aside, it is noted that Applicant does not properly define modulation efficiency. It is not “how much optical signal for an electrical input”, but rather how much modulated signal is produced for a given/fixed electrical input.
(ii) More importantly, Applicant does not cite any particular passage/drawing of the disclosure that supports the assertion that “The invention is based on the insight that surface roughness impacts electro-optical efficiency”, let alone the assertion that “The invention is based on the insight that roughness can cause electronic degradation of the active element(s) with the above materials”. The instant application mentions surface roughness only at para. 0037, 0041 – 0043, 0052, 0066, 0076, 0193, 0197, and 0256 – 0258 and none of them expressly states that “surface roughness impacts electro-optical efficiency”, let alone any quantification/examples of “the electro-optical device(s) (modulator(s)/detector(s)), having an improved modulation/detection efficiency” due to roughness under 2.0 nm RMS. In fact, the instant specification does not even mention any efficiency, modulation or detection. Hence, Applicant’s arguments are moot to begin with, because the claims do not recite the alleged effect of “improved modulation/detection efficiency”. Furthermore, any attempt to amend the claims and/or the specification at this point would cause the issue of new matter and/or rejections under 35 USC 112.
(iii) The instant specification only mentions a relationship between surface roughness of a layer interfacing a 2D material (graphene) and stress/strain in the latter and cites a prior-art NPL reference by Banszerus (para. 0042). The NPL reference details a relationship between surface roughness and stress/strain and exemplifies/quantities that a surface roughness of 0.2 – 1.0 nm can minimize strain/stress (Fig. 5; Table 1 and related text). However, the NPL reference does not describe any connection (let alone an explicit dependence/quantification) between surface roughness and the applicant-alleged “improved modulation/detection efficiency” to render the recited range meaningful/critical in that regard. The reference may however be applied, as prior art, if needed to cover any (new) limitations defining strain/stress caused by surface roughness.
(iv) While the instant specification does not mention any efficiency (modulation or detection), the instant specification does refer to a (well-known) relationship between surface roughness and optical loss (e.g., “To achieve low losses due to scattering, a low sidewall roughness is advantageous” at para. 0042; also para. 0076).
(v) Finaly, even if we assumed, arguendo, that reduced surface roughness of a planarization layer/coat leads to improved modulation/detection efficiency of a 2D material in contact with it, the Zou – Lipson combination considers a range of surface roughness that at least overlaps with the recited range, so that an electro-optic modulator and a photodetector of the Zou – Lipson combination (both graphene-based, as taught by Zou) would also have improved modulation efficiency and detection efficiency, respectively. It is noted that finding a new benefit of a known product does not carry patentable weight.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 27 are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al (CN 105842782 A) in view of Lipson et al (US 2014/0264400 A1), and further in view of Celler (US 2010/0295083 A1), as evidenced by “Graphene as a two-directional material”, by Katsnelson, Encyclopedia Britannica article (hereinafter Katsnelson).
Regarding claims 1 and 17, Zou discloses (Figs. 2, 4, and 5; Abstract; para. 0026 - 0037) a semiconductor device (optoelectronic board) and a corresponding method of manufacturing thereof, the semiconductor device comprising:
a wafer with a single-piece semiconductor substrate 101 (silicon substrate 101; para. 0028), and
at least one integrated electronic component 103 (e.g., transistors; para. 0029) extending in and/or on the semiconductor (silicon) substrate 101 (as seen in Fig. 2), the wafer having a front-end-of-line structure 102 and a back-end-of-line structure 202 lying there above (Fig. 2; para. 0031), the front-end-of-line 102 comprising the integrated electronic component or at least one of the integrated electronic components 103, and
a photonic platform (within 202) fabricated on a (planarized) side of the wafer facing (upward) away from the front-end-of-line structure (para. 0031),
wherein the photonic platform comprises at least one waveguide 204 and at least one electro-optical device, in particular, at least one photodetector (Abstract) and/or at least one electro-optical modulator (a photodetector 402 and/or a modulator 401; para. 0036),
wherein the electro-optical device (a photodetector 402 and/or a modulator 401; para. 0036) is connected (by electrically conductive metal vias 105) to the integrated electronic components 103 (transistors, drivers, amplifiers, etc) of the wafer (para. 0030),
wherein the at least one electro-optical device comprises at least one active element, the at least one active element comprising graphene, which is a 2D material (as evidenced by Katsnelson),
wherein the photonic platform (within 202) comprises a planarization coat 107 of a dielectric material (silicon dioxide SiO2) and at least one further planarization coat, and
wherein the planarization coat 107 and the at least one further planarization coat is on a (upper) side thereof facing away from the wafer 101.
Indeed, Zou teaches that the planarization coat 107 can be a multi-layer coat formed by deposition at least one coating material (e.g., silicon oxide; para. 0030) on the (upper) side of the wafer facing away from the front-end-of-line 101 and subsequent processing, the latter including planarization, deposition of a further planarization coat, and further planarization of the deposited material on its upper side facing away from the wafer by means of chemical-mechanical polishing (“The specific steps are as follows: continue to grow the insulating material 107 with a certain thickness on the interconnection layer 104, and perform a planarization treatment to ensure that the optical waveguide 204 produced subsequently has a relatively flat lower surface; grow the optical waveguide material on the surface of the insulating maternal 107, and Perform photolithography and etching to form the required optical waveguide 204 ; grow the insulating material 107 with a certain thickness again, and perform planarization treatment again to form a relatively flat upper surface of the optical waveguide 204” at para. 0031, emphasis added).
Further, Zou intends to produce low-loss optical waveguides (para. 0015 and 0033, claim 7), which are defined by planarized surfaces, and suggests the use of a low-loss optical material(s) for such planarized surfaces, as one factor determining the total waveguide loss, but Zou does not mention the surface roughness of the planarized surfaces another (well-known) factor contributing to the total waveguide loss. However, Lipson discloses (Figs. 1A, 2A – 2H, and 6 – 11; Abstract; para. 0027 – 0029, 0035 – 0039, and 0046 – 0061) a semiconductor device (optoelectronic board) and a corresponding method of manufacturing thereof, the semiconductor device comprising (see annotated Fig. 6 below):
a wafer with a single-piece semiconductor (silicon) substrate (“Silicon” in Fig. 6; 2nd and 3rd para. of Section IV), and
at least one integrated electronic component (e.g., transistors) extending in and/or on the semiconductor (silicon) substrate, the wafer having a front-end-of-line structure (identified as “CMOS” in Fig. 6) and a back-end-of-line structure (identified as “Deposited Photonics” in Fig. 6) lying there above, the front-end-of-line comprising the integrated electronic component or at least one of the integrated electronic components (“The CMOS microelectronic layer includes the Front End Of Line (FEOL) having the transistors and other active devices fabricated on the silicon substrate at the bottom, and the Back End Of Line (BEOL) having multiple layers of metal (as many as 10 or more in modern logic process) and interlayer dielectric for connecting the frontend devices together to form a circuit ... In FIG. 6, the BEOL is connected to multiple photonic layers” at para. 0046, emphasis added), and
a photonic platform (within the “Deposited Photonics”) fabricated on a side (either the bottom or top side of the “Passivation” layer in Fig. 1) of the wafer facing (upward) away from the front-end-of-line structure (“CMOS”, as seen in Fig. 1), which photonic platform (“Deposited Photonics”) comprises at least one waveguide (a pair of lower SiN waveguides and one upper waveguide in Fig. 6) and at least one electro-optical device (a photodetector and/or an electro-optical modulator), wherein the electro-optical device (a photodetector and/or a modulator) or at least one of the electro-optical devices of the photonic platform (within the “Deposited Photonics”) is connected (by electrically conductive metal vias, as shown in Fig. 6) to the integrated electronic component (transistors, drivers, amplifiers, etc) or at least one of the integrated electronic components of the wafer (“In the upper deposited photonics layer in the example in FIG. 6, two layers of Silicon Nitride (SiN (waveguides are marked as lower optical waveguide and upper optical waveguide. One layer of a Excimer Laser Anneal (ELA) polysilicon is shown to form the active photonic device that is electrically coupled to a CMOS transistor circuit in the CMOS layer. In the illustrated examples in FIGS. 6-9, the active photonic device is shown to be an optical ring resonator configured to provide a desired function (e.g., a modulator or detector). In implementations, such an active photonic device can be implemented in various configurations in connection with the underlying CMOS transistor circuit” at para. 0047, emphasis added).
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Annotated Fig. 6 of Lipson.
Lipson discloses (Figs. 2E – 2H) a deposition-planarization-deposition processing sequence that is similar in Zou and produces a planarization coat 222,230,222 as a multi-layer coat formed by deposition at least one coating material (PECVD oxide coating 230 in Fig. 2G) on an (upper) side (of lower planarized coat 222) facing away from of the (silicon) wafer 201, chemical-mechanical planarization (CMP) processing to provide a flattened/planarized surface, deposition of subsequent layers (PECVD silicon nitride 232 in Fig. 2G and upper flattened/planarized layer 222 (further planarization coat) in Fig. 2H), and their planarization (see annotated Figs. 2G and 2H below).
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Annotated Figs. 2G and 2H of Lipson.
Lipson recognizes that the roughness of such CMP-processed/planarized surfaces contributes to total optical waveguide loss and quantifies that such surfaces are to have low RMS roughness, e.g., below 3 nm RMS roughness (“The top part of the sacrificial layer 220 can be processed, e.g., removed and polished, to produce a flat top surface for forming the optical layers. For example, a chemical mechanical polishing (CMP) process can be performed to polish the deposited surface of the layer 220 down to a desired thickness and roughness (e.g., below 3 nm RMS roughness)” at para. 0038).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the planarized surfaces of the planarization coat and the further planarization coat, as taught by both Zou and Lipson, can each have roughness below 3 nm RMS, as quantified/exemplified by Lipson, in order to reduce optical scattering loss on them.
The Zou – Lipson combination considers a range of surface roughness values that at least overlaps with the recited range and, hence, a prima facie case of obviousness exists (MPEP 2144.05). It is also noted that (i) the upper range limit depends on a particular application (e.g., an maximum acceptable level of optical waveguide loss, an operational wavelength (scattering loss strongly depends on it), etc); that (ii) the instant application does not provide any criticality for the exact value of the recited upper range limits; that (iii) it has been held that discovering the optimum or workable ranges of prior art involves only routine skill in the art (In re Aller, 105 USPQ 233); and that (iv) it has been held that "A recognition in the prior art that a property is affected by the variable is sufficient to find the variable result-effective." In re Applied Materials', Inc., 692 F.3d 1289, 1297 (Fed. Cir. 2012). It is well settled that it would have been obvious for an artisan with ordinary skill to develop workable or even optimum ranges for result-effective parameters. In re Boesch, 617 F.2d 272, 276 (CCPA 1980); see also In re Woodruff, 919 F.2d 1575, 1577-78 (Fed. Cir. 1990). In this regard, the Zou – Lipson combination certainly considers surface roughness a result-effective parameter (which determines optical propagation loss).
Further, both Zou (claim 4) and Lipson (Fig. 6; para. 0036 and 0038) each teach that the underlying substrate can be a silicon wafer. While the Zou – Lipson combination does not cite typical diameters of standard/commercial-grade silicon wafers, Celler discloses (Fig. 4I; para. 0009 – 0020 and 0085) an optical waveguide device with hybrid integration, wherein the optical waveguide device comprises optical waveguides, modulators, and/or photodetectors that are formed in layers deposited over a silicon wafer 28. Celler states a (well-known) fact that standard/commercial-grade silicon wafers have industry-standardized diameters of 200 mm or 300 mm (para. 0052). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the silicon wafer in the device of the Zou – Lipson combination can be an industry-standardized silicon wafer with a diameter of 200 mm or 300 mm, in order to take advantage of the mature technology of manufacturing silicon wafers and their high quality at relatively low cost.
The Zou – Lipson – Celler combination considers a range of wafer diameters that at least overlaps with the recited range and, hence, a prima facie case of obviousness exists (MPEP 2144.05). It is also noted that (i) the range limits depend on a particular application (e.g., a particular semiconductor material of the wafer that sets the upper size of dies subsequently singulated from it, etc); that (ii) the instant application does not provide any criticality for the exact values of the recited range limits; and that (iii) it has been held that discovering the optimum or workable ranges of prior art involves only routine skill in the art (In re Aller, 105 USPQ 233).
In light of the foregoing analysis, the Zou – Lipson – Celler combination teaches expressly or renders obvious all of the recited limitations.
To sum up the applied prior art, Zou discloses a semiconductor device comprising graphene-based electro-optic waveguide devices and planarized coats/layers. Lipson quantifies a level of surface roughness of planarized coats/layers needed for reducing optical loss in optical waveguides. Celler cites diameters of industry-standardized silicon wafers
Regarding claims 2 and 18, Zou teaches that the back-end-of-line structure 102 of the wafer and the photonic platform 202 comprise interconnection elements (electrically conductive metal vias 105) through which the integrated electronic components 103 (transistors, resistors, etc) of the wafer is connected to the electro-optical device (a photodetector and/or a modulator) of the photonic platform (para. 0030).
Lipson also teaches (annotated Fig. 6 provided above for claims 1 and 17) that the back-end-of-line structure (identified as “CMOS” in Fig. 6) of the wafer and the photonic platform (within the “Deposited Photonics”) comprise interconnection elements (electrically conductive metal vias, identified by yellow color in Fig. 1) through which the integrated electronic component (transistors, drivers, amplifiers, etc) or at least one of the integrated electronic components of the wafer is connected to the electro-optical device (a photodetector and/or a modulator) or at least one of the electro-optical devices of the photonic platform (para. 0046 and 0047).
Regarding claims 3 and 19, Zou teaches that the photonic platform 202 comprises material 107 deposited on the side of the wafer facing (upward) away from the front-end-of-line 102, as seen in Fig. 2 (para. 0031).
Lipson also teaches (annotated Fig. 6 provided above for claim 1) that the photonic platform (within the “Deposited Photonics”) comprises material (“Passivation” layer in Fig. 6 and/or the layer disposed directly over it) deposited on the side of the wafer facing (upward) away from the front-end-of-line (“CMOS” in Fig. 6).
Regarding claims 4 and 20, Zou teaches that the photonic platform 202 comprises a planarization coat (lower portion of 107) of a dielectric material (e.g., silicon oxide; para. 0030 and 0031) fabricated in particular on the side of the wafer facing (upward) away from the front-end-of-line 101, and preferably the waveguide 204 is fabricated on the (upper) side (11) of the planarization coat facing (upward) away from the wafer (“The specific steps are as follows: continue to grow the insulating material 107 with a certain thickness on the interconnection layer 104, and perform a planarization treatment to ensure that the optical waveguide 204 produced subsequently has a relatively flat lower surface; grow the optical waveguide material on the surface of the insulating maternal 107” at para. 0031, emphasis added).
Lipson also teaches (annotated Figs. 2G and 2H provided above for claim 1) the planarization coat 230 (lower cladding) is fabricated in particular on the (upper) side of the (silicon) wafer 201 facing away from the front-end-of-line, and the (SiN) waveguide or at least one of the waveguides is fabricated (from the PECVD silicon nitride layer 232) on the (upper) side of the planarization coat 230 facing away from the wafer 201.
Regarding claims 5, 7, 21, and 22, Zou teaches that the planarization coat 107 is a coat formed by deposition at least one coating material (e.g., silicon oxide; para. 0030) on the side of the wafer facing away from the front-end-of-line 101 and preferably subsequent processing (planarization, deposition of the further planarization coat, and further planarization) of the deposited material on its upper side facing away from the wafer by means of chemical-mechanical polishing (“The specific steps are as follows: continue to grow the insulating material 107 with a certain thickness on the interconnection layer 104, and perform a planarization treatment to ensure that the optical waveguide 204 produced subsequently has a relatively flat lower surface; grow the optical waveguide material on the surface of the insulating maternal 107, and Perform photolithography and etching to form the required optical waveguide 204 ; grow the insulating material 107 with a certain thickness again, and perform planarization treatment again to form a relatively flat upper surface of the optical waveguide 204” at para. 0031, emphasis added). Lipson details that the planarization coat(s) (230 and upper 222 in Fig. 2H) can be deposited by plasma-enhanced chemical vapor deposition (PECVD, as indicated in Figs. 2G and 2H; para. 0038 and 0047) and be planarized using chemical-mechanical polishing (para. 0038).
Finally, the Zou – Lipson – Celler combination recognizes that the roughness of such CMP-processed/planarized surfaces contributes to total optical loss and the Zou – Lipson – Celler combination quantifies that such surfaces are to have low RMS roughness, e.g., below 3 nm RMS roughness (“The top part of the sacrificial layer 220 can be processed, e.g., removed and polished, to produce a flat top surface for forming the optical layers. For example, a chemical mechanical polishing (CMP) process can be performed to polish the deposited surface of the layer 220 down to a desired thickness and roughness (e.g., below 3 nm RMS roughness)” at para. 0038).
The Zou – Lipson – Celler combination considers a range of surface roughness values that at least overlaps with the recited range and, hence, a prima facie case of obviousness exists (MPEP 2144.05). It is also noted that (i) the upper range limit depends on a particular application (e.g., an maximum acceptable level of optical waveguide loss, an operational wavelength (scattering loss strongly depends on it), etc); that (ii) the instant application does not provide any criticality for the exact value of the recited upper range limits; that (iii) it has been held that discovering the optimum or workable ranges of prior art involves only routine skill in the art (In re Aller, 105 USPQ 233); and that (iv) it has been held that "A recognition in the prior art that a property is affected by the variable is sufficient to find the variable result-effective." In re Applied Materials', Inc., 692 F.3d 1289, 1297 (Fed. Cir. 2012). It is well settled that it would have been obvious for an artisan with ordinary skill to develop workable or even optimum ranges for result-effective parameters. In re Boesch, 617 F.2d 272, 276 (CCPA 1980); see also In re Woodruff, 919 F.2d 1575, 1577-78 (Fed. Cir. 1990). In this regard, the Zou – Lipson – Celler combination certainly considers surface roughness a result-effective parameter (which determines optical propagation loss).
Regarding claims 6 and 23, Zou teaches that the photonic platform 202 comprises at least one further planarization coat (a middle portion of 107), the further planarization coat or at least one of the further planarization coats preferably being made of the same material (e.g., silicon oxide; para. 0030 and 0031) as the planarization coat (a lower portion of 107) (“The specific steps are as follows: continue to grow the insulating material 107 with a certain thickness on the interconnection layer 104, and perform a planarization treatment to ensure that the optical waveguide 204 produced subsequently has a relatively flat lower surface; grow the optical waveguide material on the surface of the insulating maternal 107, and Perform photolithography and etching to form the required optical waveguide 204 ; grow the insulating material 107 with a certain thickness again, and perform planarization treatment again to form a relatively flat upper surface of the optical waveguide 204” at para. 0031, emphasis added).
Lipson also teaches (annotated Fig. 2H provided above for claim 1) the further planarization coat (layer embedding the waveguide cores 234 on the sides) or at least one of the further planarization coats (upper 222) preferably being is made of the same material as the planarization coat 230 (silicon oxide; para. 0038).
Regarding claims 8 and 9, Lipson describes (annotated Fig. 6 provided above for claim 1) that the at least one waveguide comprises or consists of silicon nitride, wherein the photonic platform (within the “Deposited Photonics”) comprises a plurality of waveguides (at last two lower waveguide and one upper waveguide), preferably at least two waveguides extending at least in sections one above the other, as seen in Fig. 6 (“a layer of 400 nm of low stress PECVD Silicon Nitride can be used as the optical waveguide layer 232” at para. 0038; “In the upper deposited photonics layer in the example in FIG. 6, two layers of Silicon Nitride (SiN (waveguides are marked as lower optical waveguide and upper optical waveguide” at para. 0047).
Regarding claims 10 and 25, Zou discloses that the photonic platform can comprise at least one coupling device (e.g., a grating coupler; para. 0036 and 0037) associated with at least one of the waveguides 204, at least one coupling device (grating) preferably serving to couple electromagnetic radiation into the at least one associated waveguide 204, and/or to couple electromagnetic radiation out of the at least one associated waveguide 204.
Lipson also teaches (annotated Fig. 6 provided above for claim 1; also Fig. 5A; para. 0044) that the photonic platform comprises at least one coupling device (evanescent couplers between the SiN waveguides and the electro-optical device) associated with at least one of the (SiN) waveguides, the at least one coupling device (evanescent coupler) preferably serving to couple electromagnetic radiation into the at least one associated waveguide, and/or to couple electromagnetic radiation out of the at least one associated waveguide (as shown in Fig. 6 by the dashed arrows).
Regarding claim 11, Zou discloses that the electro-optical device or at least one of the electro-optical devices comprises at least one active element (a photodetector 402 and/or a modulator 401) comprising or consisting of at least one material (graphene; para. 0036), which (in a photodetector) absorbs electromagnetic radiation of at least one wavelength and generates an electrical photo signal as a result of the absorption and/or whose refractive index changes as a function of a voltage (in an electro-optic modulator) and/or the presence of a charge and/or an electric field (para. 0036 and 0037).
Lipson also teaches (annotated Fig. 6 provided above for claim 1) that the electro-optical device or at least one of the electro-optical devices comprises at least one active element (a photodetector in Fig. 7 and/or a modulator in Fig. 8) comprising or consisting of at least one material (silicon and germanium; para. 0042), which (in a photodetector) absorbs electromagnetic radiation of at least one wavelength and generates an electrical photo signal as a result of the absorption (para. 0048) and/or whose refractive index changes as a function of a voltage (in an electro-optic modulator; para. 0049) and/or the presence of a charge and/or an electric field (Fig. 4; para. 0041).
Regarding claim 12, Zou discloses that the electro-optical device can be provided by a (elector-optic) modulator 401 comprising an active element having or consisting of at least one material, whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, in particular graphene (para. 0032, 0036, and 0037) which is a 2D material.
Lipson also teaches (Fig. 4; para. 0041 – 0043) the electro-optical device or at least one of the electro-optical devices is provided by a (electro-optic) modulator comprising an active element having or consisting of at least one material, whose refractive index changes as a function of a voltage and/or the presence of charge and/or an electric field, in particular silicon, wherein the active element (modulator) and the electrode are preferably spaced apart from one another and/or are arranged offset from one another in such a way that they lie one above the other in sections (as seen in Fig. 4, the metal electrodes are spaced apart from the optical ring resonator).
Regarding claim 13, Zou discloses that the electro-optical device is given by a photodetector 402 comprising one, preferably exactly one active element 203 consisting of or comprising at least one material (graphene) which absorbs electromagnetic radiation of at least one wavelength and generates an electrical photo-signal as a result of the absorption, in particular graphene (para. 0032, 0036, and 0037).
Regarding claim 14, the Examiner took official notice in the Office Action of 1/3/25 that plasmonic waveguides are well known in the art of optical waveguides and are commonly formed of a metal (Au, Ag, Al, etc) and an interfacing a dielectric material(s). Since Applicant has not traversed this official notice per see (Applicant traversed only the official notice taken for claim 5 regarding surface roughness), the fact of common knowledge has become applicant admitted prior art. Such type of optical waveguide would be an obvious choice to a person of ordinary skill in the art of optical waveguides (which is noted as being high) and provide the benefits of small transverse size and sharp bends. Lipson cites (para. 0044) a well-known use of tapered waveguide portions/transitions for improved optical coupling to/in an active element (an optical modulator in Fig. 5A).
Regarding claims 15 and 16, Lipson cites (para. 0044) a well-known use of tapered waveguide portions/transitions for improved optical coupling to/in an active element (an optical modulator in Fig. 5A).
Furthermore, the Examiner took official notice in the Office Action of 1/3/25 that tapered optical waveguide interconnections/couplers were well known in the art of optical waveguides. Since Applicant has not traversed this official notice per see (Applicant traversed only the official notice taken for claim 5 regarding surface roughness), the fact of common knowledge has become applicant admitted prior art. Such type of tapered optical coupler would be an obvious choice to a person of ordinary skill in the art of optical waveguides (which is noted as being high) and provide the benefits of a mode-size transformer that reduces optical coupling loss between two or more optical elements with different sizes of their optical modes.
Regarding claim 24, Zou discloses that the fabrication of the at least one waveguide 204 includes applying a waveguide material in particular to the (upper) side of the planarization coat (lower portion of 107) facing (upward) away from the wafer, preferably depositing it thereon, and then preferably carrying out a structuring of the applied waveguide material in particular by means of lithography and/or reactive ion etching (“The specific steps are as follows: continue to grow the insulating material 107 with a certain thickness on the interconnection layer 104, and perform a planarization treatment to ensure that the optical waveguide 204 produced subsequently has a relatively flat lower surface; grow the optical waveguide material on the surface of the insulating maternal 107, and Perform photolithography and etching to form the required optical waveguide 204” at para. 0031, emphasis added).
Lipson also teaches (para. 0036 and 0038) such (well-known) processes as photolithography and reactive ion etching (RIE).
Regarding claims 26 and 27, Lipson mentions such (well-known) fact that individual chips/devices are produced from wafers by their singulation/fragmentation (e.g., by dicing; “… achieve efficient side coupling while being compatible with both flipchip packaging and mass manufacturing in just a single dielectric etch process followed by dicing” at para. 0056).
Furthermore, the Examiner took official notice in the Office Action of 1/3/25 that singulation/fragmentation (by dicing) of wafers into individual chips/devices was a technique that was well known in the art of optical waveguides. Since Applicant has not traversed this official notice per see (Applicant traversed only the official notice taken for claim 5 regarding surface roughness), the fact of common knowledge has become applicant admitted prior art. Such technique would be an obvious choice to a person of ordinary skill in the art of optical waveguides (which is noted as being high) in order to produce the final product (i.e., individual chips/devices) from a processed wafer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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