DETAILED ACTION
1. Claims 1-27 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sumbul et al (hereafter Sumbul)(US Pub. 2020/0026498).
5. As to claim 1, Sumbul discloses an integrated in-memory computing (IMC) architecture configurable to support scalable execution and dataflow of an application mapped thereto (fig. 1 compute in memory system), comprising:
a plurality of configurable Compute-In-Memory Units (CIMUs) forming an array of CIMUs (fig. 1 and [0025]-[0028], CIM system with array of units performing computations); and
a configurable on-chip network for communicating input data to the array of CIMUs, communicating computed data between CIMUs, and communicating output data from the array of CIMUs ([0038] upstream and downstream communication, input and output buffers used for the communication).
6. As to claim 21, Sumbul discloses an integrated in-memory computing (IMC) architecture configurable to support scalable execution and dataflow of a neural network (NN) mapped thereto ([0003]-[0004]), comprising:
a plurality of configurable Compute-In-Memory Units (CIMUs) forming an array of CIMUs logically configured as elements within layers of the NN mapped thereto, wherein each CIMU provides computed data output representing a respective portion of a vector within a dataflow associated with the mapped NN, and wherein parallel output computed data of CIMUs executing at a given layer form a feature-map pixel (fig. 1 and [0025]-[0028], CIM system with array of units performing computations and [0102] the CIM circuitry of either CIM 530 or CIM 540, or both, can include one or more levels of a neural network. In one example, after configuration of the CIM circuitry, the instruction pipeline applies input values to the configured neural network for processing. The CIM circuitry generates a resultant to write back to register space or system memory and the CIM circuitry can indicate completion of the processing to the executing thread that invoked the CIM circuitry);
a configurable on-chip network for communicating input data to the array of CIMUs, communicating computed data between CIMUs, and communicating output data from the array of CIMUs, the on-chip network including an on-chip operand loading network to communicate operands between CIMUs via respective interfaces therebetween ([0038] upstream and downstream communication, input and output buffers used for the communication).
7. As to claim 25, Sumbul discloses a computer implemented method of mapping an application to configurable in- memory computing (IMC) hardware of an integrated IMC architecture, the IMC hardware comprising a plurality of configurable Compute-In-Memory Units (CIMUs) forming an array of CIMUs ((fig. 1 and [0025]-[0028]), and a configurable on-chip network for communicating input data to the array of CIMUs, communicating computed data between CIMUs, and communicating output data from the array of CIMUs ([0038] upstream and downstream communication, input and output buffers used for the communication), the method comprising:
allocating IMC hardware according to application computations, using parallelism and pipelining of IMC hardware, to generate an IMC hardware allocation configured to provide high throughput application computation ([0072] and [0076] parallel units);
defining placement of allocated IMC hardware to locations in the array of CIMUs in a manner tending to minimize a distance between IMC hardware generating output data and IMC hardware processing the generated output data; and configuring the on-chip network to route the data between IMC hardware (figs 1 and 3, dynamically configurable core).
8. As to claim 2, Sumbul discloses wherein: each CIMU comprises an input buffer for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMU to generate thereby computed data comprising an output vector (fig. 1, input buffer 124 and [0019] array configured for matrix vector multiplication).
9. As to claim 3, Sumbul discloses wherein each CIMU is associated with a shortcut buffer, for receiving computational data from the on-chip network, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs is maintained ([0042] MAC array 134 can be utilized every clock cycle for as long as there is input from the input pipeline. Input signals are buffered in IN Buff 124, and output signals are buffered in OUT Buff 126, which enables the array of CNM 120 to work in a pipelined fashion with a one clock cycle operational delay in between neighbor CNM cores in a 1D systolic array.).
10. As to claim 4, Sumbul discloses wherein each CIMU includes parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers ([0072] and [0076] parallel units).
11. As to claim 5, Sumbul discloses wherein at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs in the array of CIMUs is configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching ([0053], [0060], and [0068]).
12. As to claims 6 and 8, Sumbul discloses wherein the temporal delay imparted by a shortcut buffer of a CIMU comprises at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU, a control signal received from a dataflow controller, a control signal received from another CIMU, and a control signal generated by the CIMU in response to the occurrence of an event within the CIMU ([0055]-[0056] control signals).
13. As to claim 7, Sumbul discloses wherein at least some of the input buffers may be configured to impart a temporal delay to computational data received from the on-chip network or from a shortcut buffer ([0042]).
14. As to claim 8, Sumbul discloses wherein the temporal delay imparted by an input buffer of a CIMU comprises at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU, a control signal received from a dataflow controller, a control signal received from another CIMU, and a control signal generated by the CIMU in response to the occurrence of an event within the CIMU.
15. As to claim 9, Sumbul discloses wherein at least a subset of the CIMUs are associated with on-chip network portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC (fig. 1).
16. As to claim 10, Sumbul discloses wherein the application mapped onto the IMC comprises a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs executing at a next layer, said parallel output computed data forming respective NN feature-map pixels ([0102] neural network).
17. As to claims 11 and 12, Sumbul discloses wherein the input buffer is configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step; and wherein the NN comprises a convolution neural network (CNN), and the input buffer is used to buffer a number of rows of an input feature map corresponding to a size of the CNN kernel ([0066]-[0068]).
18. As to claim 13, Sumbul discloses wherein each CIMU comprises an in- memory computing (IMC) bank configured to perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BPBS) computing process in which single bit computations are performed using an iterative barrel shifting with column weighting process, followed by a results accumulation process ([0040]-[0042]).
19. As to claim 14, Sumbul discloses wherein each CIMU comprises an in- memory computing (IMC) bank configured to perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BPBS) computing process in which single bit computations are performed using an iterative column merging with column weighting process, followed by a results accumulation process ([0083]-[0085]).
20. As to claim 15, Sumbul discloses wherein each CIMU comprises an in- memory computing (IMC) bank configured to perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BPBS) computing process in which elements of the IMC bank are allocated using a BPBS unrolling process ([0048]-[0051]).
21. As to claim 16, Sumbul discloses wherein IMC bank elements are further configured to perform MVM using a duplication and shifting process ([0048]-[0051]).
22. As to claim 17, Sumbul discloses wherein each CIMU is associated with a respective near-memory, programmable single-instruction multiple-data (SIMD) digital engine, the SIMD digital engine suitable for use in combining or temporally aligning input buffer data, shortcut buffer data, and/or output feature vector data for inclusion within a feature vector map ([0044]).
23. As to claims 18 and 19, Sumbul discloses wherein at least a portion of the CIMUs include respective lookup tables for mapping inputs to outputs in accordance with a plurality of non-linear functions, wherein non-linear function output data is provided to the SIMD digital engine associated with the respective CIMU; and wherein at least a portion of the CIMUs are associated with a parallel lookup table for mapping inputs to outputs in accordance with a plurality of non-linear functions, wherein non-linear function output data is provided to the SIMD digital engine associated with the respective CIMU. ([0082]-[0084]).
24. As to claims 20 and 22, Sumbul discloses wherein each input comprises a multi-bit input, and wherein each multibit input value is represented by a respective voltage level ([0019]-[0021]).
26. As to claims 23 and 24, Sumbul discloses wherein a multi-level driver communicates an output signal from a selected one of a plurality of voltage sources, the voltage source being selected by decoding multiple bits of an input-vector element; and wherein each input comprises a multi-bit input, and wherein each multibit input value is represented by a respective voltage level ([0019]-[0021]).
27. As to claims 26 and 27, Sumbul discloses wherein the application mapped onto the IMC comprises a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs executing at a next layer, said parallel output computed data forming respective NN feature-map pixels and wherein computation pipelining is supported by allocating a larger number of configured CIMUs executing at the given layer than at the next layer to compensate for a larger computation time at the given layer than at the next layer ([0102]).
Conclusion
28. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 2020/0210369 – related to a method of processing in memory (PIM) using a memory device, and a memory device performing the processing in memory.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151