DETAILED ACTION
1. Claims 1-27 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. Applicant’s arguments with respect to the claim(s) have been considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1, 2, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (hereafter Chen)(US Pub 2019/0065151) in view of Sumbul et al (hereafter Sumbul)(US Pub. 2020/0026498).
Sumbul was cited in the office action dated 01/13/2026.
6. As to claim 1, Chen discloses an integrated in-memory computing (IMC) architecture ([0001] compute in memory) configurable to support scalable execution and dataflow of an application mapped thereto ([003] data moved through neural network), comprising:
a plurality of configurable Compute-In-Memory Units (CIMUs) forming an array of CIMUs ([0018]-[0019] CIM for reducing energy and increase memory bandwidth. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device. This reads on array of CIMUs as currently recited).
7. While Chen teaches the plurality of Compute-In-memory units as above, Chen does not explicitly teach a configurable on-chip network for communicating input data to the array of CIMUs, communicating computed data between CIMUs, and communicating output data from the array of CIMUs.
However, Sumbul teaches a configurable on-chip network for communicating input data to the array of CIMUs, communicating computed data between CIMUs, and communicating output data from the array of CIMUs ([0032] and [0038] Controller 114 can be or include one or more control block for data communication and access to memories, as well as various arithmetic operations needed to implement the deep neural network. While this, in Sumbul, may be related to compute near memory and not explicitly compute in memory, Sumbul teaches an on-chip network for communicating input data to the array and output data from the array. Furthermore, the instant claim does not further detail the configurable on chip network beyond the limitation as currently recited. Thus, the combination of Chen and Sumbul teach the claimed limitation as recited.
8. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to modify the Compute in memory teachings of Chen, with the communication as in Sumbul, for the benefit of efficiently moving data around as needed. This would also further have been obvious limitation in view of Chen, as communicating data to and from an array is something that is needed in all instances.
9. As to claim 2, the combination of Chen and Sumbul discloses wherein: each CIMU comprises an input buffer for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMU to generate thereby computed data comprising an output vector ([Chen, [0024]-[0027]).
10. As to claim 20, the combination of Chen and Sumbul discloses wherein each input comprises a multi-bit input, and wherein each multibit input value is represented by a respective voltage level (Chen [0048]).
Allowable Subject Matter
11. Claims 21-27 allowed.
Claims 3-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art of record US Pub. 20190065151 and US Pub. 20200026498 teach the limitations as in claim 1 above.
However, the prior art of record does not teach or suggest for example, at least wherein each CIMU is associated with a shortcut buffer, for receiving computational data from the on-chip network, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs is maintained, as in claim 3;
a plurality of configurable Compute-In-Memory Units (CIMUs) forming an array of CIMUs logically configured as elements within layers of the NN mapped thereto, wherein each CIMU provides computed data output representing a respective portion of a vector within a dataflow associated with the mapped NN, and wherein parallel output computed data of CIMUs executing at a given layer form a feature-map pixel, as in claim 21;
allocating IMC hardware according to application computations, using parallelism and pipelining of IMC hardware, to generate an IMC hardware allocation configured to provide high throughput application computation; defining placement of allocated IMC hardware to locations in the array of CIMUs in a manner tending to minimize a distance between IMC hardware generating output data and IMC hardware processing the generated output data; as in claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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