DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 7-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, claim 19 continues to be rejected under 35 USC 112(b) as claim 19 requires that a semiconductor layer of the separation structure is grown in a direction parallel to the surface of the substrate and, as claim 19 depends from claim 17, requires that the semiconductor stack is formed after forming the separation section. However, the Applicant only has support for growing the semiconductor layer of the separation section in a direction parallel to the top surface of the substrate in embodiments where the semiconductor stack is formed first and then the semiconductor layer of the separation section is grown. Therefore, the same issue as identified in the previous rejection of claim 19 under 35 USC 112(b) exists where claim 19 seems to be drawn to an embodiment where the semiconductor stack is grown before the separation section is formed. Appropriate correction is required to clarify the language and have claim 19 be directed to an embodiment consistent with that of claim 17.
Regarding claim 1, claim 11 recites “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with the substrate ”. However, it is unclear in what way the topmost surface of the semiconductor stacks is at a higher position in a direction parallel with the substrate as it is unclear to which feature of the substrate the parallel refers. While the substrate surface may extend in a left/right direction across the page, the substrate has a thickness in and up/down direction across the page. Thus, it is unclear in what direction the semiconductor stack is at a higher position than the separation section. Appropriate correction is required to clarify the language. However, for purposes of compact prosecution, the Examiner interprets the language to be “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with a thickness of the substrate.” The Examiner’s interpretation is based on Fig. 4 of the Applicant’s disclosure which seems to be the only drawing directed to an embodiment where the topmost surface of the semiconductor stack is higher than a topmost surface of the separation section.
Claims 2, 3, 7-16 are also rejected under 35 USC 112(b) as they depend from and include all of the limitations of rejected claim 1.
Regarding claim 17, claim 17 recites “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with the substrate ”. However, it is unclear in what way the topmost surface of the semiconductor stacks is at a higher position in a direction parallel with the substrate as it is unclear to which feature of the substrate the parallel refers. While the substrate surface may extend in a left/right direction across the page, the substrate has a thickness in and up/down direction across the page. Thus, it is unclear in what direction the semiconductor stack is at a higher position than the separation section. Appropriate correction is required to clarify the language. However, for purposes of compact prosecution, the Examiner interprets the language to be “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with a thickness of the substrate.” The Examiner’s interpretation is based on Fig. 4 of the Applicant’s disclosure which seems to be the only drawing directed to an embodiment where the topmost surface of the semiconductor stack is higher than a topmost surface of the separation section.
Claims 18 and 19 are also rejected under 35 USC 112(b) as they depend from and include all of the limitations of rejected claim 17.
Regarding claim 20, claim 20 recites “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with the substrate ”. However, it is unclear in what way the topmost surface of the semiconductor stacks is at a higher position in a direction parallel with the substrate as it is unclear to which feature of the substrate the parallel refers. While the substrate surface may extend in a left/right direction across the page, the substrate has a thickness in and up/down direction across the page. Thus, it is unclear in what direction the semiconductor stack is at a higher position than the separation section. Appropriate correction is required to clarify the language. It is recommended that the Applicant clarify the language by stating the direction in terms of the top surface of the substrate and that the stacking direction in the instant case would be perpendicular to the top surface of the substrate. However, for purposes of compact prosecution, the Examiner interprets the language to be “wherein a topmost surface of each of the semiconductor stacks is at a position higher than a topmost surface of the separation section in a direction parallel with a thickness of the substrate.” The Examiner’s interpretation is based on Fig. 4 of the Applicant’s disclosure which seems to be the only drawing directed to an embodiment where the topmost surface of the semiconductor stack is higher than a topmost surface of the separation section.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7, 8, 15 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Templier et al. (US 2021/0020688) hereinafter “Templier”.
Regarding claim 1, Fig. 2B of Templier teaches a light emitting device, comprising: a substrate (Combination of Items 250, 251 and 201) having a first surface (Top surface of Item 201) and a second surface (Bottom surface of Item 250) opposed to each other; semiconductor stacks (Item 103) provided on the first surface of the substrate (Top surface of Item 201) and each including a first conductivity type layer (Item 109), an active layer (Item 107), and a second conductivity type layer (Item 105) that are stacked in order from a side of the first surface, the semiconductor stacks (Item 103) including multiple light emitting regions configured to emit light; and a separation section (Item 115) provided between each of the semiconductor stacks (Item 103), wherein a topmost surface of each of the semiconductor stacks (Item 103) is at a position higher than a topmost surface of the separation structure (Item 115) in a direction parallel with a thickness of the substrate (Combination of Items 250, 251 and 201).
Regarding claim 3, Fig. 2B of Templier further teaches where the second conductivity type layer (Item 105) extends onto a portion of the topmost surface of the separation section (Item 115).
Regarding claim 7, Fig. 4F of Templier further teaches where the separation section (Item 405) includes an insulator including a dielectric material (Paragraph 0074).
Regarding claim 8, Fig. 4F of Templier further teaches wherein the dielectric material comprises an oxide material (Paragraph 0074 SiO2).
Regarding claim 15, Fig. 2B of Templier further teaches where the multiple light emitting regions emit light from a side of the substrate (Item 250).
Regarding claim 16, Fig. 2B of Templier further teaches where the substrate (Combination of Items 250, 251 and 201) has multiple openings (Where there are openings in the dielectric layer of Item 201 and those openings are filled with conductive material) at respective positions directly opposed to the multiple light emitting regions.
Alternatively, Claims 1-3, 7, 8 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lau et al. (US 2020/0184884) hereinafter “Lau”.
Regarding claim 1, Fig. 10I of Lau teaches a light emitting device (Paragraph 0002), comprising: a substrate (Item 1080) having a first surface and a second surface opposed to each other; semiconductor stacks (Combination of p-GaN, EBL, MQW and n-GaN) provided on the first surface of the substrate and each including a first conductivity type layer (Item p-GaN), an active layer (Item MQW), and a second conductivity type layer (Item n-GaN) that are stacked in order from a side of the first surface, the semiconductor stacks including multiple light emitting regions configured to emit light; and a separation section (Item 1060) provided between each of the semiconductor stacks, wherein the topmost surface of each of the semiconductor stacks (Top surface of Item n-GaN) is at a position higher than a topmost surface of the separation section (Item 1060) in a direction parallel with a thickness of the substrate (Item 1080).
Examiner’s Note: The Examiner notes that the separation section being provided between each of the semiconductor stacks does not require that the entirety of each of the semiconductor stacks are separated from each other by the separation section.
Examiner’s Note 2: Further, there is no requirement that each of the stacks are entirely physically separated from each other. Each stack can include n-GaN layer even when the n-GaN layer is common to all of the stacks.
Regarding claim 2, Fig. 10I of Lau further teaches where multiple light emitting regions are to be driven independently of each other (Paragraph 0153).
Regarding claim 3, Fig. 10I of Lau further teaches where the second conductivity type layer (Item n-GaN) extends onto a portion of the topmost surface of the separation section (Item 1060).
Regarding claim 7, Fig. 10I of Lau further teaches where the separation section (Item 1060) includes an insulator including a dielectric material (Paragraph 0148).
Regarding claim 8, Fig. 10I of Lau further teaches wherein the dielectric material comprises an oxide material (Paragraph 0148 SiO2).
Regarding claim 15, Fig. 10I of Lau further teaches where the multiple light emitting regions emit light from a side of the substrate (Item 1080).
Alternatively, Claims 1 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 2020/0403116) hereinafter “Li”.
Regarding claim 1, Fig. 2K of Li teaches a light emitting device, comprising: a substrate (Item 50) having a first surface (Top surface) and a second surface (Bottom surface) opposed to each other; semiconductor stacks (Item 210) provided on the first surface of the substrate (Item 50) and each including a first conductivity type layer (Item 211), an active layer (Item 212), and a second conductivity type layer (Item 213) that are stacked in order from a side of the first surface, the semiconductor stacks including multiple light emitting regions configured to emit light; and a separation section (Combination of Items 42 and 100; where the combination of Items 42 and 100 are between respective light emitting structures and therefore separate the light emitting structures from each other; See also Examiner’s Note below) provided between each of the semiconductor stacks (Item 210), wherein the topmost surface of each of the semiconductor stacks (Top surface of Item 213) is at a position higher than a topmost surface of the separation section (Combination of Items 42 and 100) in a direction parallel with a thickness of the substrate (Item 50).
Examiner’s Note: The Examiner notes that the claim language does not require any specific structure or orientation of a structure to be the separation section except that the separation section is provided between each of the semiconductor stacks and has a topmost surface lower than a topmost surface of the semiconductor stack.
Regarding claim 17, Figs. 2A-2K of Li teaches a method of manufacturing a light emitting device, comprising; after forming a separation section (Item 42) on a first surface (Top surface) of a substrate (Item 50) having the first surface and a second surface (Bottom surface) opposed to each other, forming semiconductor stacks (Item 210) with the separation section interposed therebetween, the semiconductor stacks each including a first conductivity type layer (Item 211), an active layer (Item 212), and a second conductivity type layer (Item 213) that are stacked in order from a side of the first surface (Top surface of Item 50), the semiconductor stacks including multiple light emitting regions configured to emit light, wherein a topmost surface of each of the semiconductor stacks (Item 210) is at a position higher than a topmost surface of the separation section (Item 42) in a direction parallel with the thickness of the substrate (Item 50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Bierhuizen et al. (US 2011/0260178) hereinafter “Bierhuizen”.
Regarding claim 9, Templier teaches all of the elements of the claimed invention as stated above except where the separation stacks includes a semiconductor material that configures the semiconductor stacks.
Bierhuzien teaches where a semiconductor material is used as an isolation means between light emitting segments (Paragraph 0025).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the separation stacks include a semiconductor material that configures the semiconductor stacks because a semiconductor material is known to form an insulating region between light emitting segments (Bierhuizen Paragraph 0025) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Bierhuizen et al. (US 2011/0260178) hereinafter “Bierhuizen” and in further view of Oraw (US 2016/0218245) hereinafter “Oraw”.
Regarding claim 10, the combination of Templier and Bierhuizen teaches all of the elements of the claimed invention as stated above except where the separation section includes an undoped layer including the semiconductor material that configures the semiconductor stacks.
Oraw teaches where an undoped semiconductor material is known to be an insulating semiconductor material (Paragraph 0016 where undoped GaN is used as an insulating semiconductor material).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the separation section include an undoped layer including the semiconductor material that configures the semiconductor stacks because an undoped semiconductor material is known to act as an insulating material (Oraw Paragraph 0016) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Sato (US 2016/0155782) hereinafter “Sato”.
Regarding claim 11, Templier teaches all of the elements of the claimed invention as stated above except where the separation section has a stacked structure including a first separation layer, including a dielectric material and a second separation layer including a semiconductor material that configures the semiconductor stacks.
Fig. 4 of Sato teaches where a separation section (Combination of Items 27a-c and 28) includes a stacked structure including a first separation layer (Item 28), including a dielectric material (Paragraph 0029) and a second separation layer (Combination of Items 27a-c) including a semiconductor material (Paragraph 0032) that configures the semiconductor stacks.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the separation section has a stacked structure including a first separation layer, including a dielectric material and a second separation layer including a semiconductor material that configures the semiconductor stacks because this allows for separation between semiconductor stacks (Paragraph 0032) while also incorporating a photodiode in the device, where the photodiode prevents light leakage between adjacent pixels (Sato Paragraph 0034).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Cha et al. (US 2022/0190204) hereinafter “Cha”.
Regarding claim 12, Templier teaches all of the elements of the claimed invention as stated above except a first electrically conductive film on the topmost surface of each of the semiconductor stacks.
Fig. 2 of Cha teaches where electrically conductive films (Items 16 and 17, respectively) are present on a lowermost surface of a semiconductor light emitting stack (Combination of Items 11, 12 and 13) and a topmost surface of the semiconductor light emitting stack.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first electrically conductive film on the topmost surface of each of the semiconductor stacks as taught by Cha because having the first electrically conductive film on the topmost surface of each of the semiconductor stacks instead of a side surface reduces the foot print (width) of the light emitting element by forming a single stack of layers (Cha Paragraph 0043).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Chu (US 2016/0020353) hereinafter “Chu”.
Regarding Claim 12, Templier teaches all of the elements of the claimed invention as stated above except a first electrically conductive film on the topmost surface of each of the semiconductor stacks.
Fig. 10 of Chu teaches where an electrically conductive film is present on a topmost surface of semiconductor stacks.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an electrically conductive film on the topmost surface of each of the semiconductor stacks because this allows for the second electrode to make better electrical contact with the second conductivity type layer as more surface area of the second electrode will make physical contact with the second conductivity type layer (Chu Paragraph 0108)
Regarding claim 13, Templier further teaches where the separation section (Item 115) has a groove extending from the top surface in a direction toward the first surface of the substrate (Combination of Items 250, 251 and 201), and the groove is filled with the first electrically conductive film (Item 113).
Regarding claim 14, Templier further teaches where the first electrically conductive film (Item 113) has a light reflecting property (Paragraph 0077 where the metal is copper or titanium).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2020/0403116) hereinafter “Li” in view of Robin et al. (US 2020/0357848) hereinafter “Robin”.
Regarding claim 18, the combination of Li and Robin teaches all of the elements of the claimed invention as stated above.
Templier does not teach where after forming the separation section entirely on the first surface, forming multiple openings that penetrate the separation section, and growing the first conductivity type layer, the active layer and the second conductivity type layer in order on the first surface exposed in each of the openings.
Robin teaches after forming the separation section (Item 30) entirely on the first surface, forming multiple openings (Items 31) that penetrate the separation section (Item 30), and growing the first conductivity type layer, the active layer and the second conductivity type layer (Item 221; Paragraph 0062) in order on the first surface exposed in each of the openings.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have, after forming the separation section entirely on the first surface, forming multiple openings that penetrate the separation section, and growing the first conductivity type layer, the active layer and the second conductivity type layer in order on the first surface exposed in each of the openings because this allows the separation layer to serve as a mask to denote where a semiconductor stack is grown on a substrate (Robin Paragraph 0109).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Templier et al. (US 2021/0020688) hereinafter “Templier” in view of Chen et al. (US 2019/0305073) hereinafter “Chen”.
Regarding claim 20, Fig. 2B of Templier teaches an image display apparatus (Paragraph 0002) comprising a light emitting device (Item 200), the light emitting device includes: a substrate (Combination of Items 250, 251 and 201) having a first surface (Top surface of Item 201) and a second surface (Bottom surface of Item 250) opposed to each other; semiconductor stacks (Item 103) provided on the first surface of the substrate (Top surface of Item 201) and each including a first conductivity type layer (Item 109), an active layer (Item 107), and a second conductivity type layer (Item 105) that are stacked in order from a side of the first surface, the semiconductor stacks (Item 103) including multiple light emitting regions configured to emit light; and a separation section (Item 115) provided between each of the semiconductor stacks (Item 103), wherein a topmost surface of each of the semiconductor stacks (Item 103) is at a position higher than a topmost surface of the separation structure (Item 115) in a direction parallel with a thickness of the substrate (Combination of Items 250, 251 and 201).
Templier does not teach where the image display device comprises multiple light emitting devices.
Fig. 1 of Chen teaches an image display device (Paragraph 0045) where the image display device comprises multiple light emitting devices (Items 1 and 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the image display device of Templier comprise multiple light emitting devices because this allows for use in large sized display applications (Chen Paragraph 0004).
Response to Arguments
Applicant's arguments filed 09/16/2025 with regard to the rejection of claim 19 under 35 USC 112(b) have been fully considered but they are not persuasive.
Specifically, claim 19 continues to be rejected under 35 USC 112(b) as claim 19 requires that a semiconductor layer of the separation structure is grown in a direction parallel to the surface of the substrate and, as claim 19 depends from claim 17, requires that the semiconductor stack is formed after forming the separation section. However, the Applicant only has support for growing the semiconductor layer of the separation section in a direction parallel to the top surface of the substrate in embodiments where the semiconductor stack is formed first and then the semiconductor layer of the separation section is grown. Therefore, the same issue as identified in the previous rejection of claim 19 under 35 USC 112(b) exists where claim 19 seems to be drawn to an embodiment where the semiconductor stack is grown before the separation section is formed. Appropriate correction is required to clarify the language and have claim 19 be directed to an embodiment consistent with that of claim 17 .
Applicant’s arguments, see Applicant’s REMARKSs, filed 09/16/2025, with respect to the rejection(s) of claim(s) 1, 17 and 20 under 35 USC 102(a) and 35 USC 103(a), respectively have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different embodiment of Templier (Fig. 2B) and a different orientation of Fig. 10I of Lau.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891