DETAILED ACTION
The Office Action is sent in response to Applicant’s Communication received on 08/08/2022 for application number 17/798,155. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/declaration, Claims, Preliminary Amendments, Certified Copy of Foreign Priority Application, M903, and WIPO with Written opinion.
Examiner notes: claims 1-14 have been canceled, and claims 15-27 are newly added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following limitations:
wherein at least one arithmetic module of the arithmetic modules that is provided to calculate at least one individual product of two binary digits including a logical AND gate, and/or logical XOR gate, and/or a multiplexer.
Wherein all combinations of a logical AND gate, and/or logical XOR gate, and/or a multiplexer must be shown. For one example: a logical AND gate, and logical XOR gate, and a multiplexer to calculate at least one individual product of two binary digits.
wherein the configuration of the arithmetic unit is retrieved based on the input data from a further artificial neural network.
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “1” has been used to designate both arithmetic unit and input data to the ANN on at least figure 6.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under the Alice Framework Step 1, Claims 15-19 recites an arithmetic unit and, therefore, is a machine. Claim 20 recites a control device and, therefore, is a machine. Claims 21-22 recites a method and, therefore, is a process. Claims 23-25 recites a method and, therefore, is a process. Claim 26 recites a non-transitory machine readable data carrier and, therefore, is an article of manufacture. Claim 27 recites a computer and, therefore, is a machine.
Under the Alice Framework Step 2A prong 1, claim 15 recites
An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers, comprising:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers,
the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums,
at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
The above underlined limitations are related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas (see specification pages 10-11, and 13-14). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 15 recites the following additional elements: “a plurality of arithmetic modules”, “an adder”, and “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”. However, the additional elements of “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 15 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claims 16-19 recite further steps and details to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas and falls within the “mathematical Concepts” and/or “mental Processes” grouping of abstract ideas.
Claim 16, is directed to circuits for the arithmetic modules to compute the product. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a logical AND gate, and/or logical XOR gate, and/or a multiplexer”. However, the additional elements of “a logical AND gate, and/or logical XOR gate, and/or a multiplexer” are recited at a high-level of generality (i.e., as a generic computer component for computing logic for the product) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a logical AND gate, and/or logical XOR gate, and/or a multiplexer” are recited at a high-level of generality (i.e., as a generic computer component for computing logic for the product) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 17, is directed to implementing full adders. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “full adder”. However, the additional elements of “full adder” are recited at a high-level of generality (i.e., as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements “full adder” are recited at a high-level of generality (i.e., as a generic computer component for adding) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 18, is directed to merely applying the arithmetic modules to a work cycle. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “wherein at least one arithmetic module of the arithmetic modules and/or its spatial situation inside the arithmetic unit, is thermally configured for a lower work cycle than is the case for at least one other of the arithmetic modules”. However, the additional elements of “one arithmetic module… is thermally configured for a lower work cycle” are recited at a high-level of generality (i.e., as a generic computer component for computing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one arithmetic module… is thermally configured for a lower work cycle” are recited at a high-level of generality (i.e., as a generic computer component for computing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 19, is directed to merely considering the arithmetic modules size and distances. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “a lower work cycle by scaling down its constructive size and/or by reducing a distance between the at least one arithmetic module and other components of the arithmetic unit”. However, the additional elements of “a lower work cycle by scaling down its constructive size and/or by reducing a distance between the at least one arithmetic module and other components of the arithmetic unit.” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, the claim does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “a lower work cycle by scaling down its constructive size and/or by reducing a distance between the at least one arithmetic module and other components of the arithmetic unit.” are merely adding insignificant extra-solution activities. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, which discloses turning off parts of the chips that are not used for increased cooling [p. 42] and lessening distances improves performance [p.537-538]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claim 20 recites
A control device for a vehicle, comprising:
a first interface capable of being connected to at least one sensor borne by the vehicle;
a second interface capable of being connected to at least one actuator of the vehicle;
an artificial neural network (ANN) that is involved in processing of measurement data of the sensor to form control signals for the actuator, at least one arithmetic unit being provided for calculation of a sum of inputs of at least one neuron in the ANN, the inputs being weighted with weights of the neuron, the arithmetic unit including:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers,
the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums,
at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
The above underlined limitations are related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas (see specification pages 10-11, and 13-14). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 20 recites the following additional elements: “a first interface capable of being connected to at least one sensor borne by the vehicle”, “a second interface capable of being connected to at least one actuator of the vehicle”, “an artificial neural network (ANN)”, “arithmetic unit “, “a plurality of arithmetic modules”, “an adder”, and “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”. However, the additional elements of “a first interface capable of being connected to at least one sensor borne by the vehicle”, “a second interface capable of being connected to at least one actuator of the vehicle”, “an artificial neural network (ANN)”, “arithmetic unit “, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for obtaining sensor data; as a generic computer component for control; as a generic computer component for using a neural network to implement the math; and as a generic computer component for doing the arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 20 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a first interface capable of being connected to at least one sensor borne by the vehicle”, “a second interface capable of being connected to at least one actuator of the vehicle”, “an artificial neural network (ANN)”, “arithmetic unit “, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for obtaining sensor data; as a generic computer component for control; as a generic computer component for using a neural network to implement the math; and as a generic computer component for doing the arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claim 21 recites
A method for producing and/or configuring an arithmetic unit for calculation of a sum of inputs of at least one neuron in an artificial neural network (ANN), the inputs being weighted with weights of the neuron, the arithmetic unit including:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers,
the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums,
at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
providing a candidate configuration of the arithmetic unit that determines which arithmetic modules are absent or are completely deactivated or partially deactivated;
training the ANN bases on training data, the arithmetic unit, or a simulational representation of the arithmetic unit, behaving in a manner corresponding to the candidate configuration;
ascertaining success of the training based on test data or validation data;
optimizing parameters that characterize the candidate configuration with respect to at least one specified optimization goal, with a boundary condition that the success of the training fulfills a further specified condition.
The above underlined limitations are related to optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas (see at least specification pages 10-11, and 13-17). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 15 recites the following additional elements: “ANN”, “a plurality of arithmetic modules”, “an adder”, and “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”. However, the additional elements of “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” and “providing a candidate configuration of the arithmetic unit that determines which arithmetic modules are absent or are completely deactivated or partially deactivated” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 15 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea The additional elements of at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit” and “providing a candidate configuration of the arithmetic unit that determines which arithmetic modules are absent or are completely deactivated or partially deactivated” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claim 22 recite further steps and details to the optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas In particular claims 22 do not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, claim 23 recites
A method for operating an artificial neural network (ANN) that is implemented with at least one arithmetic unit including:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers,
the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums,
at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
wherein the method comprises the following steps:
based on specific input data that are provided for processing by the ANN, ascertaining a configuration of the arithmetic unit that determines which of the arithmetic modules of the arithmetic unit are to be deactivated for the running time;
completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration;
supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated.
The above underlined limitations are related to optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas (see at least specification pages 10-11, and 13-17). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 23 recites the following additional elements: “ANN”, “a plurality of arithmetic modules”, “an adder”, and “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”. However, the additional elements of “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”, “completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration”, and “supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 23 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea The additional elements of “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”, “completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration”, and “supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, Claim 24 recite further steps and details to the optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas. Wherein claim 24 computes the resilience. In particular claims 2 do not include additional elements that would require further analysis under Step 2A prong 2 and Step 2B. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 1, Claim 25 recite further steps and details to the optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas. Wherein claim 25 receives the input data from another ANN. Accordingly, the claims recites an abstract idea.
Under the Alice Framework Step 2A prong 2, the claim recites the following additional elements: “wherein the configuration of the arithmetic unit is retrieved based on the input data from a further artificial neural network.”. However, the additional elements of “wherein the configuration of the arithmetic unit is retrieved based on the input data from a further artificial neural network.” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 15 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the elements of “wherein the configuration of the arithmetic unit is retrieved based on the input data from a further artificial neural network.” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under the Alice Framework Step 2A prong 1, claim 26 recites
A non-transitory machine-readable data carrier on which is stored a computer program for operating an artificial neural network (ANN) that is implemented with at least one arithmetic unit including:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers,
the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums,
at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
wherein the method comprises the following steps:
based on specific input data that are provided for processing by the ANN, ascertaining a configuration of the arithmetic unit that determines which of the arithmetic modules of the arithmetic unit are to be deactivated for the running time;
completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration;
supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated.
The above underlined limitations are related to optimizing parameters related to computing products and sums which amount to mathematical operations and relationships which falls under “mathematical concepts” of abstract ideas (see at least specification pages 10-11, and 13-17). Accordingly, the claim recites an abstract idea.
Under the Alice Framework Step 2A prong 2, claim 26 recites the following additional elements: “a computer program”, “ANN”, “a plurality of arithmetic modules”, “an adder”, and “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”. However, the additional elements of “a computer program“, “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for storing instructions; as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea. The additional elements of “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”, “completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration”, and “supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated” are merely adding insignificant extra-solution activities. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under the Alice Framework Step 2B, claim 23 does not include additional elements that individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a computer program“, “ANN”, “a plurality of arithmetic modules” and “an adder” are recited at a high-level of generality (i.e., as a generic computer component for storing instructions; as a generic neural network for computing the math; and as a generic computer component for doing arithmetic) such that they amount to no more than mere instructions using a generic computer component or merely as tools to implement the abstract idea The additional elements of “at least one arithmetic module… being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit”, “completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration”, and “supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated” are merely adding insignificant extra-solution activities. See MPEP 2106.05(d)(II) which states that the courts have recognized computer functions such as “Storing and retrieving information in memory” as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See Patterson et al., Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, (2013), hereinafter Patterson 2013, Chapter 1 which discloses turning off parts of the chips that are not used [p. 42]. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Claim 27 is directed to claim 23. A mere change in statutory class is obvious. As such claim 27 is rejected for the reasons given above
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15, 18, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moons et al. (NPL: "DVAS: Dynamic Voltage Accuracy Scaling for Increased Energy-Efficiency in Approximate Computing"), hereinafter Moons.
Regarding claim 15, Moon discloses:
An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers, comprising ["We show DVAS is an efficient method for scalable approximate computing..." Sec.I]:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit ["Reducing the bit width reduces activity quadratically in multipliers (see figure 3), and linearly in adder structures" Sec,II.B; Figure 3, shows the multiplier architecture that generates products and/or sum and shows the crtical path; "it is of course important to signal-gate the unused inputs to prevent unwanted signal propagation" Sec.II.B; "In the second case (blue), only the two MSB’s of each word are used. All other inputs are signal gated. The number of active gates is now reduced from 20 (red) to 6 (blue) and the critical path length is shorter, allowing voltage scaling" Sec.II.C; “we have implemented a DVAS-capable multiply-accumulate” Sec.V.A].
Regarding claim 18, Moon discloses wherein at least one arithmetic module of the arithmetic modules and/or its spatial situation inside the arithmetic unit, is thermally configured for a lower work cycle than is the case for at least one other of the arithmetic modules [“For every accuracy setting, the critical path is derived and the operational minimum voltage maintaining the nominal operational frequency is set” Sec.III; “the critical path length is shorter, allowing voltage scaling” Sec.II.C].
Regarding claim 19 Moon discloses wherein at least one arithmetic module of the arithmetic models, or its situation in the arithmetic unit, is configured for a lower work cycle by scaling down its constructive size. [“For every accuracy setting, the critical path is derived and the operational minimum voltage maintaining the nominal operational frequency is set” Sec.III; “the critical path length is shorter, allowing voltage scaling” Sec.II.C].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Moons, and in view of Alkurwy (NPL: " Design of a high-performance multiplier based on multiplexer").
Regarding claim 16, Moons disclose the invention substantially as claimed. See the discussion of claim 15 above. However, Moons does not explicitly disclose wherein at least one arithmetic module of the arithmetic modules that is provided to calculate at least one individual product of two binary digits including a logical AND gate, and/or logical XOR gate, and/or a multiplexer.
In the analogous art of multiplier implementations, Alkurwy discloses multipliers using a AND gates or using a multiplexer to compute the individual products of two binary digits [Figs.1-3]
It would have been obvious to one of ordinary skill in the art, having the teachings of Moons and Alkurwy before him before the effective filing date of the claimed invention to implement the components of the multiplier array disclosed by Moons, using the conventional or the multiplexer equivalent taught by Alkurwy, in order to use commonly known multiplier or for improved operations using the mux [Alkurwy: Sec.1, and 4];
Regarding claim 17, Moons and Alkurwy disclose the invention substantially as claimed. See the discussion of claim 16 above.
Moons discloses wherein the adder includes a plurality of full adders as arithmetic modules [“Reducing the bit width reduces activity quadratically in multipliers (see figure 3), and linearly in adder structures“ Sec.II.B; “a DVAS-capable multiply-accumulate (MAC) unit in 40nm CMOS This MAC exists out of an 8-bit two stage pipelined DVAS multiplier with two or four voltage-accuracy scaling modes and a 16-bit adder.”Sec.V.A].
Alkurwy also discloses the adder includes a plurality of full adders as arithmetic modules [Fig.1]
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sharan et al. (US 2021/0133583 A1), hereinafter Sharan, and in view of Venkataramani et al. (NPL: "AxNN: Energy-Efficient Neuromorphic Systems using Approximate Computing"), hereinafter Venkataramani, and further in view of Moons.
Regarding claim 20, Sharan discloses:
A control device for a vehicle, comprising:
a first interface capable of being connected to at least one sensor borne by the vehicle; a second interface capable of being connected to at least one actuator of the vehicle; ["each of any number of system(s) on chip(s) (“SoC(s)”) 1204, each of controller(s) 1236, and/or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1200), and may be connected to a common bus, such CAN bus." par.137; "SoCs 1204 may include, without limitation,...1212, accelerator(s) ... and/or other components and features not illustrated. In at least one embodiment, SoC(s) 1204 may be used to control vehicle 1200 in a variety of platforms and systems." par. 139]
an artificial neural network (ANN) that is involved in processing of measurement data of the sensor to form control signals for the actuator ["accelerator(s) 1214 (e.g., hardware acceleration cluster) may include a deep learning accelerator(s) (“DLA”)...a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones 1296; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and/or a CNN for security and/or safety related events." par.149]
However, Sharan does not explicitly disclose an artificial neural network (ANN) that is involved in processing of measurement data of the sensor to form control signals for the actuator, at least one arithmetic unit being provided for calculation of a sum of inputs of at least one neuron in the ANN, the inputs being weighted with weights of the neuron, the arithmetic unit including: a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
In the analogous art of Neural network approximate computing, Venkataramani teaches an artificial neural network (ANN) that is involved in processing of measurement data, at least one arithmetic unit being provided for calculation of a sum of inputs of at least one neuron in the ANN, the inputs being weighted with weights of the neuron [“we propose a method to transform any given NN into an Approximate Neural Network (AxNN).” Abs; “In fully-accurate NNs, the output error originates from untrained or partially trained network parameters. However, in the case of AxNNs, we intentionally supplement this error with a secondary source, viz. approximate neurons… we propose to retrain the AxNN parameters with approximations in-place” Sec.4.1.3; Figure 3].
And scaling the hardware by optimizing the precision of the input and weights [“In this work, we utilize precision scaling, a popular technique in which the precisions (bit-widths) of the input operands and the neuron weights are modulated based on their degree of resilience.” Sec.4.1.2]
It would have been obvious to one of ordinary skill in the art, having the teachings of Sharan and Venkataramani before him before the effective filing date of the claimed invention to incorporate the approximation training method as taught by Venkataramani into the device disclosed by Sharan, to implement a neural network that improves energy efficiency while maintaining acceptable output quality [Venkataramani: Sec.3/4]
However, Sharan and Venkataramani, does not explicitly disclose: the arithmetic unit including: a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
In the analogous art of hardware approximate computing implementations, Moons teaches:
An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers, comprising ["We show DVAS is an efficient method for scalable approximate computing..." Sec.I]:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit ["Reducing the bit width reduces activity quadratically in multipliers (see figure 3), and linearly in adder structures" Sec,II.B; Figure 3, shows the multiplier architecture that generates products and/or sum and shows the crtical path; "it is of course important to signal-gate the unused inputs to prevent unwanted signal propagation" Sec.II.B; "In the second case (blue), only the two MSB’s of each word are used. All other inputs are signal gated. The number of active gates is now reduced from 20 (red) to 6 (blue) and the critical path length is shorter, allowing voltage scaling" Sec.II.C; “we have implemented a DVAS-capable multiply-accumulate” Sec.V.A].
It would have been obvious to one of ordinary skill in the art, having the teachings of Sharan, Venkataramani, and Moons before him before the effective filing date of the claimed invention to modify the arithmetic unit disclosed by the combination of Sharan and Venkataramani to use the arithmetic unit taught by Moon, to utilize the same type of hardware for minimizing bit-width for further improvements to energy consumption for multiply-accumulate operations [Moon: Sec.II-III].
Claims 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Venkataramani, and in view of Moons.
Regarding claim 21, Venkataramani discloses:
A method for producing and/or configuring an arithmetic unit for calculation of a sum of inputs of at least one neuron in an artificial neural network (ANN), the inputs being weighted with weights of the neuron, the arithmetic unit including [“we propose a method to transform any given NN into an Approximate Neural Network (AxNN).” Abs; “In fully-accurate NNs, the output error originates from untrained or partially trained network parameters. However, in the case of AxNNs, we intentionally supplement this error with a secondary source, viz. approximate neurons… we propose to retrain the AxNN parameters with approximations in-place” Sec.4.1.3; Figure 3].:
wherein the method comprises the following steps:
providing a candidate configuration of the arithmetic unit that determines which arithmetic modules are absent or are completely deactivated or partially deactivated ["an iterative approximate-and-retrain loop to enhance the benefits of approximate computing" Sec.1; "in the case of AxNNs, we intentionally supplement this error with a secondary source, viz. approximate neurons" Sec.4.1.3];
training the ANN bases on training data, the arithmetic unit, or a simulational representation of the arithmetic unit, behaving in a manner corresponding to the candidate configuration [“we propose to retrain the AxNN parameters with approximations in-place.” Sec.4.1.3];
ascertaining success of the training based on test data or validation data [“After retraining, if the AxNN meets the specified quality constraint, then lines 4-14 are repeated and the network is further approximated. If not, the last valid AxNN is produced as the output.” Sec.4.2];
optimizing parameters that characterize the candidate configuration with respect to at least one specified optimization goal, with a boundary condition that the success of the training fulfills a further specified condition [“the training phase, the parameters of the NN (weights of each neuron) are identified based on training dataset…” Sec.3; the retaining process… suitably adjusts the AxNN parameters, thereby alleviating the impact of approximation-induced errors.” Sec.4.1].
However, Venkataramani, does not explicitly disclose: the arithmetic unit including: a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
In the analogous art of hardware approximate computing implementations, Moons teaches:
An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers, comprising ["We show DVAS is an efficient method for scalable approximate computing..." Sec.I]:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit ["Reducing the bit width reduces activity quadratically in multipliers (see figure 3), and linearly in adder structures" Sec,II.B; Figure 3, shows the multiplier architecture that generates products and/or sum and shows the crtical path; "it is of course important to signal-gate the unused inputs to prevent unwanted signal propagation" Sec.II.B; "In the second case (blue), only the two MSB’s of each word are used. All other inputs are signal gated. The number of active gates is now reduced from 20 (red) to 6 (blue) and the critical path length is shorter, allowing voltage scaling" Sec.II.C; “we have implemented a DVAS-capable multiply-accumulate” Sec.V.A].
It would have been obvious to one of ordinary skill in the art, having the teachings of Venkataramani and Moon before him before the effective filing date of the claimed invention to modify the arithmetic unit disclosed by the combination of Venkataramani to use the arithmetic unit taught by Moon, to utilize the same type of hardware for minimizing bit-width for further improvements to energy consumption for multiply-accumulate operations [Moon: Sec.II-III].
Regarding claim 22, Venkataramani and Moon disclose the invention substantially as claimed. See the discussion of claim 21 above.
Venkataramani discloses wherein the specified optimization goal includes:
a minimal energy consumption of the arithmetic unit["in this work, we identify a new dimension to optimize neuromorphic systems. We leverage their intrinsic resilience and employ approximate computing to construct NN implementations that are significantly more efficient” Sec.2; “the parameter update process is formulated as a gradient descent optimization problem as shown in Equation 1” Sec. 3; See sec.4.2 for design methodology related to energy]
Moon also discloses a minimal number of arithmetic modules present or activated in the arithmetic unit, [“For every accuracy setting, the critical path is derived and the operational minimum voltage maintaining the nominal operational frequency is set” Sec.III]
Regarding claim 23, Venkataramani discloses:\
A method for operating an artificial neural network (ANN) that is implemented with at least one arithmetic unit [“we propose a method to transform any given NN into an Approximate Neural Network (AxNN).” Abs; “In fully-accurate NNs, the output error originates from untrained or partially trained network parameters. However, in the case of AxNNs, we intentionally supplement this error with a secondary source, viz. approximate neurons… we propose to retrain the AxNN parameters with approximations in-place” Sec.4.1.3; Figure 3].:
wherein the method comprises the following steps:
based on specific input data that are provided for processing by the ANN, ascertaining a configuration of the arithmetic unit that determines which of the arithmetic modules of the arithmetic unit are to be deactivated for the running time; completely or partially deactivating selected arithmetic modules of the arithmetic unit corresponding to the ascertained configuration; supplying the input data to the ANN for the processing with the selected arithmetic modules completely or partially deactivated. [“the training phase, the parameters of the NN (weights of each neuron) are identified based on training dataset…” Sec.3; “the retaining process… suitably adjusts the AxNN parameters, thereby alleviating the impact of approximation-induced errors.” Sec.4.1; "Once the NN is trained, it enters the testing or evaluation phase" Sec.3 "the neurons were approximated by scaling the precision of their input operands..." Sec.7.5; “In this work, we utilize precision scaling, a popular technique in which the precisions (bit-widths) of the input operands and the neuron weights are modulated based on their degree of resilience” Sec.4.1.2];
However, Venkataramani, does not explicitly disclose: the arithmetic unit including: a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of this individual product or this individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit.
In the analogous art of hardware approximate computing implementations, Moons teaches:
An arithmetic unit for calculating an approximate value for a product or a sum of two inputted numbers, comprising ["We show DVAS is an efficient method for scalable approximate computing..." Sec.I]:
a plurality of arithmetic modules, at least one of the arithmetic modules being provided to calculate individual products or individual sums of digits of the inputted numbers, the plurality of arithmetic modules being connected in an adder that is configured to calculate digits of the product or of the sum, from the individual products or from the individual sums, at least one arithmetic module that is required for the calculation of at least one individual product or individual sum, and/or is required for the propagation of the individual product or the individual sum onto the product or the sum, being absent in the arithmetic unit or being connected there in such a way that it is capable of being selectively deactivated, completely or partially, for a running time of the arithmetic unit ["Reducing the bit width reduces activity quadratically in multipliers (see figure 3), and linearly in adder structures" Sec,II.B; Figure 3, shows the multiplier architecture that generates products and/or sum and shows the crtical path; "it is of course important to signal-gate the unused inputs to prevent unwanted signal propagation" Sec.II.B; "In the second case (blue), only the two MSB’s of each word are used. All other inputs are signal gated. The number of active gates is now reduced from 20 (red) to 6 (blue) and the critical path length is shorter, allowing voltage scaling" Sec.II.C; “we have implemented a DVAS-capable multiply-accumulate” Sec.V.A].
It would have been obvious to one of ordinary skill in the art, having the teachings of Venkataramani and Moons before him before the effective filing date of the claimed invention to modify the arithmetic unit disclosed by the combination of Venkataramani to use the arithmetic unit taught by Moon, to utilize the same type of hardware for minimizing bit-width for further improvements to energy consumption for multiply-accumulate operations [Moon: Sec.II-III].
Regarding claim 24, Venkataramani and Moon disclose the invention substantially as claimed. See the discussion of claim 23 above.
Venkataramani discloses wherein a measure of the resilience of the ANN to changes in the input data are ascertained based on the input data, and the configuration of the arithmetic unit is ascertained based on the measure of the resilience [“We leverage the intrinsic resilience and employ approximate computing to construct NN implementations that are significantly more efficient” Sec.2].
Regarding claim 25, Venkataramani and Moon disclose the invention substantially as claimed. See the discussion of claim 23 above.
Venkataramani discloses wherein the configuration of the arithmetic unit is retrieved based on the input data from a further artificial neural network. [“After retraining, if the AxNN meets the specified quality constraint, then lines 4-14 are repeated and the network is further approximated. If not, the last valid AxNN is produced as the output” Sec.4.2]
Regarding claim 26, Venkataramani discloses:
A non-transitory machine-readable data carrier on which is stored a computer program for operating an artificial neural network (ANN) [“Approximate neurons are inaccurate but cost-effective hardware or software implementations of the original neuron functionality and are the primary source of the energy efficiency in AxNNs.” Sec.4.1.2; “We now evaluate the benefits of AxNNs on commodity platforms by designing approximate software implementations of NNs.” Sec.7.5]
The remaining limitations of the claim is directed to claim 23, a mere change in statutory class is obvious. The combination of Venkataramani and Moons in claim 23 discloses the remaining limitations
Regarding claim 27, Venkataramani discloses:
A computer configured to operate an artificial neural network (ANN) [“Approximate neurons are inaccurate but cost-effective hardware or software implementations of the original neuron functionality and are the primary source of the energy efficiency in AxNNs.” Sec.4.1.2; “We now evaluate the benefits of AxNNs on commodity platforms by designing approximate software implementations of NNs.” Sec.7.5]
The remaining limitations of the claim is directed to claim 23, a mere change in statutory class is obvious. The combination of Venkataramani and Moons in claim 23 discloses the remaining limitations
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Antony et al. “Design of High Speed Vedic Multiplier using Multiplexer based Adder.” Discloses another variant of using muxes. See Sec.IV
Wilson “Design Recipes for FPGAs Using Verilog and VHDL”, discloses XOR for sign bits. See fig.26.1.
Baugh et al. “A Two’s Complement Parallel Array Multiplication Algorithm” discloses using AND gates for partial products. See p.1045.
Sharma et al. “Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks” discloses bit fusion, of number of components to be optimized. See Fig.2;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenny K. Bui whose telephone number is (571)270-0604. The examiner can normally be reached 8:00 am to 3:00 pm on Monday, 8:00 am to 4:00 pm on Tuesday to Friday ET.
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/KENNY K. BUI/Patent Examiner, Art Unit 2182
(571)270-0604
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182