DETAILED ACTION
This Office Action is in response to the Applicant’s Remarks filed on 01/27/2026.
Currently, claims 1-10 and 12-13 are pending in the application. Currently, claims 1-5 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/27/2026 has been entered.
Response to Amendments
Applicant' s arguments with respect to claim(s) 6-9 (see pages 8-10 of Applicant’s Remarks filed 01/27/2026) have been considered and are persuasive (see allowable subject matter below). Applicant' s arguments with respect to claim(s) 10, 12, and 13 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 12-13 are rejected under 35 U.S.C. 103 as being obvious over YU et al. (US Pub. No. 2020/0118908) in view of LIU (US Pub. No. 2021/0134748) in view of ZHANG et al. (US Pub. No. 2020/0411479) and further in view of WU et al. (US Pub. No. 2020/0058617).
Regarding independent claim 10, Yu teaches a method for manufacturing a bonding structure (Figs. 32-39), comprising:
providing a bottom wafer (Fig. 32, L1 + M1 + L2, ¶ [0054]), wherein a first hybrid bonding structure (Fig. 33, 24A + 26A, ¶ [0055]) is formed on the bottom wafer, the hybrid bonding structure comprises a first dielectric bonding layer (Fig. 33, 26A, ¶ [0055]) and a first metal bonding pad (Fig. 33, 24A, ¶ [0055]) in the dielectric bonding layer.
providing one or more to-be-bonded wafers (Figs. 33 & 36, layer of M2 + L3 + M3 and layer of M4 + L4, ¶¶ [0055] & [0057]), a second hybrid bonding structure (Fig. 36, 24B + 26B, ¶ [0055]) comprising a second dielectric bonding layer (Fig. 36, 26B, ¶ [0055]) and a second metal bonding pad (Fig. 36, 24B, ¶ [0055]) in the second dielectric bonding layer is formed on each of the one or more to-be-bonded wafers;
bonding the one or more to-be-bonded wafers sequentially on the bottom wafer via the hybrid bonding structure and the second hybrid bonding structure to form a wafer stack (Fig. 36) comprising an array of chip stacks (the Examiner notes that Yu Figs. 32-38 only teaches the creation of a singular chip stack. ¶ [0015] teaches that the completed package 100 can be referred to as an integrated Chip. Yu Fig. 39, ¶ [0059] teaches that a plurality of identical packages 100 are formed through a singulation process after the processing steps of Figs. 32-38.) and electrical vertical interconnections (Figs. 35 & 38, layers connected to 30 + 41, ¶¶ [0019] & [0057]) in each of the chip stacks, wherein the chip stacks comprises the chips in the bottom wafer and the other chips in the one or more to-be-bonded wafers, each of the chip stack comprises a plurality of layers of chips;
wherein for each of the one or more to-be-bonded wafers, the method further comprises: forming one or more through silicon vias (Figs. 35 & 38, 30 + 41, ¶¶ [0019] & [0057]) on said to-be-bonded wafer after said to-be-bonded wafer is bonded in the bonding;
wherein when a quantity of the to-be-bonded wafer is more than one, for each of the one or more to-be-bonded wafers except a topmost one, after forming the one or more through silicon vias, the method further comprises:
forming a rewiring layer (Fig. 38, 76 + 80, ¶¶ [0050]-[0051]) electrically connected to the one or more through silicon vias on said to-be-bonded wafer after said to-be-bonded wafer is bonded in the bonding; and
forming a third hybrid bonding structure (Fig. 37, 24C + 26C, ¶ [0026], the Examiner notes that 26C is unlabeled in Fig. 38 (see Fig. 7)) on the one rewiring layer, where the third hybrid bonding structure comprises a third dielectric bonding layer (Figs. 7 & 37, 26C, ¶ [0026]) and a third metal bonding pad (Fig. 37, 24C, ¶ [0026]) in the third dielectric bonding layer, and one of the one or more through silicon vias in said to-be-bonded wafer is electrically connected to the third metal bonding pad via the rewiring layer; and
wherein the one or more to-be-bonded wafers comprises a first to-be-bonded wafer (Fig. 38, layer of M4 + L4) and a second to-be-bonded wafer (Fig. 30, layer of M2 + L3 + M3 and 78, ¶ [0024]) that are directly bonded, and the first to-be-bonded wafer is located at a side of the second to-be-bonded wafer away from the bottom wafer (Fig. 38); and wherein for at least one of the chip stacks, the plurality of layers comprises a first layer (Fig. 37, layer of 24C) in the first to-be-bonded wafer and a second layer (Fig. 37, layer of 76) in the second to-be-bonded wafer.
However, Yu does not explicitly teach that at least one of the interconnection layers in the first layer is electrically isolated from the rewiring layer of the second to-be-bonded wafer by the third dielectric bonding layer of the second to-be-bonded wafer, and the at least one of the interconnection layers in the first layer is aligned with the rewiring layer of the second to-be-bonded wafer along a direction perpendicular to a surface of the bottom wafer.
However, Liu is a pertinent art that teaches that at least one of the interconnection layers in the first layer (Fig. 2A, 236, ¶ [0044]) is electrically isolated from the rewiring layer (Fig. 2A, 232, ¶ [0042]) of the second to-be-bonded wafer (Fig. 2A, 2nd Semiconductor Structure, ¶ [0042]) by the third dielectric bonding layer (Fig. 2A, 220, ¶ [0044]) of the second to-be-bonded wafer, and the at least one of the interconnection layers in the first layer is aligned (Fig. 2A) with the rewiring layer of the second to-be-bonded wafer along a direction perpendicular to a surface of the bottom wafer (Fig. 2A, 202, ¶ [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s semiconductor structure to further include aligned layers that are electrically isolated from each other according to the teaching of Liu (Fig. 2A) in order to facilitate higher alignment precision (Liu ¶ [0031]).
However, as it is not pertinent to the particulars of their invention, Yu modified by Liu does not explicitly teach providing a bottom wafer in which chips are arranged in an array; providing one or more to-be-bonded wafers, wherein other chips are arranged in an array in each of the one or more to-be-bonded wafers; and forming a wafer stack comprising an array of chip stacks and an interconnection layer in the bottom wafer is electrically connected to the metal bonding pad; and a second interconnection layer in each of the one or more to-be-bonded wafer is electrically connected to the second metal bonding pad; and each layer of the plurality of layers comprises an interconnection layer; wherein the electrical vertical interconnections comprise: a thorough vertical interconnection that is electrically connected to the interconnection layer in each layer of the plurality of layers, a partial vertical interconnection that is electrically connected to the interconnection layer in each layer of a part of the plurality of layers, wherein the part of the plurality of layers comprises two or more layers, and a single vertical interconnection that is electrically connected to the interconnection layer in a single layer of the plurality of layers (the Examiner notes that Yu teaches a method for packaging pre-cut semiconductor die in multi-layered semiconductor structures and does not explicitly teach the stacking of wafers before further processing and dicing. ).
However, stacking wafers before dicing is known in the art. Zhang is one such reference that teaches providing a bottom wafer (Fig. 20, bottom 200, ¶ [0200]) in which chips (Fig. 20, quadrants of 200 separated by 269, ¶ [0061]) are arranged in an array; providing one or more to-be-bonded wafers (Fig. 20, additional wafers 200 stacked above bottom 200), wherein other chips are arranged in an array in each of the one or more to-be-bonded wafers; and forming a wafer stack (Fig. 20, 260, ¶ [0061]) comprising an array of chip stacks (Fig. 20, stack of quadrants of 200 separated by 269 that include multiple dies 202, ¶ [0061]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s method for manufacturing to further comprise in the context of stacked wafers as shown by Zhang (Fig. 20) in order to reduce manufacturing time (Yu modified by Zhang would require one less singulation step).
However, Yu modified by Liu modified by Zhang does not explicitly teach a second interconnection layer in each of the one or more to-be-bonded wafer is electrically connected to the second metal bonding pad; and each layer of the plurality of layers comprises an interconnection layer; wherein the electrical vertical interconnections comprise: a thorough vertical interconnection that is electrically connected to the interconnection layer in each layer of the plurality of layers, a partial vertical interconnection that is electrically connected to the interconnection layer in each layer of a part of the plurality of layers, wherein the part of the plurality of layers comprises two or more layers, and a single vertical interconnection that is electrically connected to the interconnection layer in a single layer of the plurality of layers.
However, Wu is a pertinent art that teaches a second interconnection layer (Fig. 5, 336/236, ¶ [0015]) in each of the one or more to-be-bonded wafer (Fig. 5, 10 + 20 + 30 + 40, ¶ [0012]) is electrically connected to the second metal bonding pad (Fig. 5, 224/324, ¶ [0017], corresponding to Yu’s metal pads 24A/24B); and
each layer of the plurality of layers comprises an interconnection layer (Yu modified by Wu’s bonding metal lines 236 and 336 would be connected to Yu’s metal pads in the manner shown in Wu Fig. 5 and would thus fulfill this limitation); wherein the electrical vertical interconnections comprise:
a thorough vertical interconnection that is electrically connected to the interconnection layer in each layer of the plurality of layers (Yu modified by Wu’s Interconnect A (see annotated Figure below)),
a partial vertical interconnection that is electrically connected to the interconnection layer in each layer of a part of the plurality of layers, wherein the part of the plurality of layers comprises two or more layers (Yu modified by Wu’s Interconnect B (see annotated Figure below)), and
a single vertical interconnection that is electrically connected to the interconnection layer in a single layer of the plurality of layers (Yu modified by Wu’s Interconnect C (see annotated Figure below)).
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Annotated Yu Fig. 38
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s method for manufacturing to further comprise bonding metal lines connected to Yu’s metal pads according to the teaching of Wu (Fig. 5) in order to provide additional routing flexibility (Wu ¶ [0017]).
Regarding claim 12, Yu modified by Liu modified by Zhang modified by Wu teaches the method according to claim 11, and Yu teaches forming a pad (Fig. 39, 40, ¶ [0052]) on the rewiring layer (Fig. 30, 76 + 80, ¶¶ [0050]-[0051]) of the topmost one (Yu Fig. 36, layer of M4 + L4, ¶¶ [0055] & [0057]) of the one or more to-be- bonded wafers.
Regarding claim 13, Yu modified by Liu modified by Zhang modified by Wu teaches the method according to claim 10, and Zhang teaches dicing the wafer stack (Fig. 20, 260, ¶ [0061]) to separate the chip stacks (¶ [0061] teaches cutting the wafer stack along lines 269).
Allowable Subject Matter
Claims 6-9 are allowed.
The following is an examiner's statement of reasons for allowance:
Regarding independent claim 6, none of the prior art of record teaches or suggests, alone or in combination, the plurality of layers comprises a third layer in the first to-be- bonded wafer and a fourth layer in the second to-be-bonded wafer, the interconnection layer of the third layer is aligned with the interconnection layer of the fourth layer along the direction perpendicular to the surface of the bottom wafer, and the interconnection layer of the third layer is electrically isolated from the interconnection layer of the fourth layer, in combination with the remaining limitations of independent claim 6.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813