DETAILED ACTION
This Office Actions is in response to communication (Amendment) filed on 09/24/2025.
Claims 1 – 20 are pending. Claims 10 – 20 are non-elected. Claim 1 is in independent form. Claim 1 is amended. This action is Final.
Claims 10 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/23/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the applicant’s remarks and arguments filed on 09/24/2025.
Claim 1 was amended. Claims 1 – 20 remain pending in the application. Claims 10 – 20 are withdrawn from further consideration. Claims 1 – 9 are being considered on the merits.
Response to Arguments
The applicant’s remarks and/or arguments, filed on 09/24/2025 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Response to Specification and Abstract objection
Applicant’s argument filed on 09/24/2025 regarding the Specification and Abstract objection have been fully considered and they are persuasive. The Specification and Abstract objection have been withdrawn.
Response to Drawing objection
Applicant’s argument filed on 09/24/2025 regarding the Drawing objection has been fully considered and they are persuasive. The Drawing objection has been withdrawn.
Response to 103 Remarks
Applicant’s argument filed on 09/24/2025 regarding 35 U.S.C § 103 rejections have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In addition, regarding the remark that “Further, Applicant disagrees that Ravid discloses Applicant's claimed stand-alone accelerator protocol (SAP) module configured to communicate with a remote computing system agent over a network fabric and initialize local hosting of an application kernel because Ravid's single reference to a protocol in the accelerator allows the analysis module to communicate with the accelerator without affecting the suspect computer (Ravid, 6:51-54). Nowhere does Ravid disclose or suggest that Ravid's protocol is configured to "initialize local hosting of an application kernel" as Applicant has claimed.” The examiner fully considers, but respectfully disagrees, and would like to point out that the examiner only relies on Ravid for the teaching of “a stand-alone accelerator protocol (SAP) module”, as explained in the rejection below. The examiner did not rely on Ravid for teaching the others limitation of the claim 1.
Regarding the remark that “Applicant's boot loader, on the contrary, "initializes a SAP module" that is "configured to communicate with a remote computing agent" and "initialize local hosting of an application kernel." Applicant's SAP module implements an Open Systems Interconnect model for connection to a remote computing agenda (U.S. Published Patent Application # 2023/0081394, paragraph 85). Chapman's communications are clearly initialized, and indeed are operational, when the application programs are invoked because Chapman's data are already transferred between the host computer and the accelerator when the application kernel programs are invoked.” The examiner fully considers, but respectfully disagrees, and would like to point out that the examiner only relies on Chapman for the teaching of “initialize local hosting of an application kernel”, as explained in the rejection below. With the current claim language, under BRI in light of the Specification, the limitation “initialize local hosting of an application kernel” is reasonable taught by Chapman, as Chapman disclose “the accelerator device 320 comprises the application kernels 321”, which means the kernel is located within the accelerator, and at [0073] disclose the accelerator invokes/initialize the application kernel.
Thus, based on all of the above explanation, the examiner finds these arguments
unpersuasive and maintains that the rejection under 35 U.S.C. § 103 is proper.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over Santan et al. US Pat. No. US 10031760 B1 (hereafter Santan), Ravid US Pat. No. US 8793795 B1, Chapman et al. US Pub. No. US 20130179485 A1 (hereafter Chapman), in further view of Vaibhav NPL Understanding What is a Flash Bootloader and the Nuances of an Automotive ECU Re-programming
Regarding claim 1, Santan teaches the invention substantially as claimed A non-transitory computer-readable medium having stored thereon software instructions that, when executed by a processor, cause the processor to (Col 4, lines 10 – 16: “In still another aspect, the inventive arrangements may be implemented as a computer program product having a non-transitory computer-readable storage medium storing program code that, when executed, causes a processor to perform and/or initiate the operations described within this disclosure.”)
establish a software-defined board support package (SW-BSP) on a reconfigurable hardware accelerator (Col 1, lines 64 – 67 and Col 2 lines 1 – 3: “A method of managing an accelerator includes, responsive to determining a first container including a first configuration file and a second configuration file, caching, using a host processor, the second configuration file within a local memory of the host processor. The method includes providing, using the host processor, the first configuration file to a device of the accelerator.” and Col 3, lines 40 – 44: “an accelerator may include a programmable integrated circuit (IC). The programmable IC implements specialized circuitry by loading a type of configuration file called a configuration bitstream.” and col 9, lines 6 – 13.) The citation discloses the programmable integrated circuit (IC)/ reconfigurable hardware accelerator could be configure by loading a configuration file to a device of the accelerator/SW-BSP, called configuration bitstream.
the SW-BSP comprising: a stand-alone accelerator protocol (SAP) module configured to communicate with a remote computing system agent over a network fabric. (FIG. 2, FIG. 4, Col 12, lines 4 – 14, Col 20 lines 44 – 54: “Referring to FIGS. 7 and 8, the methods described herein may be used to remotely and automatically update configuration files of devices throughout a computing environment such as a data center. A system administrator, for example, may create a container or containers for accelerators with updated configuration files and store the containers within the host system(s) in designated locations. The next reboot of the host system and/or the accelerator(s) will cause the container(s) with the update configuration files to be used in booting the accelerator(s) and devices thereon throughout the data center.”) and Col 25, lines 44 – 59 and col 12, lines 43 – 53: “programmable IC 220 to establish communication with processor 105 via bus 115, e.g., network adapter 404 coupled to CAP 406.”) The citation discloses at FIG. 2, FIG.4 and Col 12, lines 4 – 14 that the Programmable IC 220 of accelerator 150 communicate with the host system. At Col 20, lines 44 – 54 discloses the current method can perform remotely, such as a data center, which the container(s) with the update configuration files to be used in booting the accelerator(s) and devices thereon throughout the data center. At col 25, lines 44 – 59 that the computer readable program instructions could be execute entirely on the remote computer or server. Col 12, lines 43 – 53 discloses the programmable IC 220 to establish communication with processor 105 via bus 115/network fabric.
However, the teaching of Santan teaches the accelerator module, but does not clearly indicate that the accelerator module is a stand-alone. The stand-alone accelerator protocol (SAP) module will be discussed below.
and a boot loader configured to initialize the SAP module on connection of the reconfigurable hardware accelerator to the network fabric. (FIG. 1, 7, 9, Col 3, lines 21 – 23 and lines 36 – 39: “This disclosure relates to using accelerators and, more particularly, to boot and configuration management of accelerators using configuration files...... Boot and configuration management is an important technological aspect of using accelerators and ensuring that the accelerators operate efficiently and correctly.” and Col 21, lines 8 – 29: “Flash memory 225 may store a boot loader 910, a configuration bitstream 915, and one or more containers 210. In one arrangement, responsive to powering on programmable IC 220, PCAP 906 may read flash memory 225 and provide boot loader 910 to processor 105. Processor 105, for example, is a hardwired processor. Processor 105 may execute boot loader 910 to begin operation.” In one arrangement, configuration bitstream 915, when loaded into programmable IC 220, may implement network adapter 404 using programmable circuitry of programmable IC 220. Network adapter 404 may be coupled to processor 105. In one aspect, network adapter 404 may be used to allow programmable IC 220, using processor 105, to communicate with one or more other systems.”) and Col 22, lines 5 – 11: “For example, processor 105 may execute an operating system and the accelerator driver upon executing boot loader 910. The accelerator driver locates container 410 at a predetermined location within flash memory 225 or within another data storage device coupled to programmable IC 220, i.e., via network adapter 404.” And Col 23, lines 13 – 14: “boot loader 910 may be loaded subsequent to loading configuration bitstream 915.”) The citation discloses at FIG. 9 a system that includes network having an architecture that including a boot loader. At Col 21, lines 8 – 29 and Col 22 lines 5 – 11 discloses Processor 105 may execute boot loader 910 to begin operation, and load the configuration bitstream 915 into programmable IC 220, may implement network adapter 404 using programmable circuitry of programmable IC, which allow programmable IC 220, using processor 105, to communicate with one or more other systems.
Santan teaches the accelerator module, but does not clearly indicate that the accelerator module is a stand-alone accelerator protocol (SAP) module, and Santan does not clearly indicate the initialize local hosting of an application kernel.
However, Ravid teaches a stand-alone accelerator protocol (SAP) module (e.g. FIG. 5, Fig. 6, and Col 7, lines 63 – 67, and col 8, lines 1 – 18, and Col 9, lines 58 – 65: “The present invention is additionally defined as a device, comprising: using an analyzing pre-processing unit as a stand alone accelerator, not connected to a subject computer, but only connected to an analyzing unit; all functionality of the analyzing pre-processing unit is available as a hardware accelerator to the analyzing unit; and the data to be analyzed is either already inside the analyzing unit or the suspect computer is connected directly to the analyzing unit.” and Col 6, lines 51 – 59: “In addition, a protocol in the computer forensic accelerator engine 20 may be provided to allow the analysis device 22 to communicate with the computer forensic accelerator engine 20 without affecting the suspect drive. The computer forensic accelerator engine 20 is provided with the ability to communicate with the analysis device 22 to receive various instructions including parameters (such as a list of website names) from the analysis device 22 prior to and during data acquisition and analysis”) The citation discloses at FIG. 5, Fig. 6, and Col 7, lines 63 – 67, and col 8, lines 1 – 18, and Col 9, lines 58 – 65 the Analysis and Processing Device (APD) as a stand-alone accelerator for performing the analyzing data from the suspect computer and send the analyzed data to the Analysis Unit. At Col 6, lines 51 – 59 discloses the protocol for the computer forensic accelerator engine 20 is provided with the ability to communicate with the analysis device 22
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the stand-alone accelerator protocol (SAP) module, as taught in Ravid’s invention into Santan’s invention because adding the SAP module to the current system would bring important improvements in flexibility, compatibility, reduce setup time, and make it easier to use the reconfigurable hardware accelerator, since the SAP module is stand-alone, it can handle communication and configuration with the computing system on its own, without depending on other components of the system.
However, Chapman teaches and initialize local hosting of an application kernel; (e.g. FIG. 3, [0045]: “The accelerator device 320 comprises the application kernels 321, buffer objects 322, the runtime environment 323, the proxy facilities 324 to the host 310, and the socket interface 325.” and [0073]: “Alternatively according to the present invention provided as the pseudo code 1220, the application data are transferred with the optimal chunk size and the accelerator device invokes the application kernel programs to start the operation on the data upon receiving each chunk if the computation is associative.”) The citation discloses at FIG. 3 and [0045] that the application kernel is located inside/local to the accelerator, and at [0073] disclose the accelerator invokes/initialize the application kernel.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the initialize local hosting of an application kernel, as taught in Chapman’s invention into Santan’s invention because by start and run the application kernel locally, the accelerator can begin processing the computational tasks quickly, and improve in performance, independence, and responsiveness of the accelerator.
Santan teaches the boot loader, but fails to teach that the boot loader executing on the reconfigurable hardware accelerator before connection of the reconfigurable hardware accelerator to the network fabric
However, Vaibhav teaches executing on the reconfigurable hardware accelerator before connection of the reconfigurable hardware accelerator to the network fabric (e.g. section: “How Bootloader Software Makes Re-programming of an Automotive ECU, an Efficient Process”) The citation discloses the idea of operating an electronic control unit (ECU) which is tasked with a specific application. ECU includes bootloader software responsible for ECU software update. At every boot-up, the bootloader software checks if the updated version of ECU software is available ("Primary Bootloader: Microcontroller Unit Setup. After the microcontroller is reset, the control first comes to Primary Bootloader. This is the part of the Bootloader software that initializes and sets up the MCU resources."), then checking firmware update via communication medium (Secondary bootloader: microcontroller reprogramming), and perform remote ECU update via ethernet as medium for communication (DoIP "Diagnostics over Internet Protocol". thus, Vaibhav suggests the idea of an internal, or built-in boot loader responsible to load programming data of an electronic control unit at every boot-up, prior to connects or communicate with client/service via a communication medium such as ethernet or internet.
It would have been obvious to one of ordinary skills in the art before executing on the reconfigurable hardware accelerator before connection of the reconfigurable hardware accelerator to the network fabric, as taught in Vaibhav’s invention into Santan’s invention because new features would improves security and reliability by ensuring the system is properly prepared before any external communication begins, which allows the accelerator to verify and set up critical components in advance and reducing startup errors, and helping the accelerator connect to the network in a controlled and trusted state.
Regarding claim 3, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 1, and Santan further teaches wherein the SW-BSP further comprises an application module locally hosting the application kernel. (FIG. 2, and Col 5, lines 43 – 50: “Accelerator driver 205 may be executed by processor 105 to communicate with accelerator 150. In one aspect, accelerator driver 205 is implemented as a kernel mode device driver. The term “kernel mode” refers to a computing environment that includes high level privileges. A kernel mode device driver is made for, and executed using, the kernel mode of an operating system. Kernel mode device drivers generally execute at the same high level of privilege.”) The citation discloses the accelerator driver is implemented as a kernel mode device driver, which responsible for configurating the accelerator.
Regarding claim 4, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 3, and Chapman further teaches wherein the application module further loads the application kernel from a plurality of stored application kernels. (Chapman - FIG. 3, and [0045]) The citation discloses the accelerator device 320 comprises multiple application kernels 321.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Santan Ravid, Vaibhav, and Chapman, in further view of Loafman et al. US Pub. No. US 8671414 B1 (hereafter Loafman)
Regarding claim 2, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 1, and Ravid further teach wherein the SAP module ....... without being provisioned by a central processing unit (CPU). (e.g. FIG. 5, Fig. 6, and Col 7, lines 63 – 67, and col 8, lines 1 – 18, and Col 9, lines 58 – 65: “The present invention is additionally defined as a device, comprising: using an analyzing pre-processing unit as a stand alone accelerator, not connected to a subject computer, but only connected to an analyzing unit; all functionality of the analyzing pre-processing unit is available as a hardware accelerator to the analyzing unit; and the data to be analyzed is either already inside the analyzing unit or the suspect computer is connected directly to the analyzing unit.” and Col 6, lines 51 – 59: “In addition, a protocol in the computer forensic accelerator engine 20 may be provided to allow the analysis device 22 to communicate with the computer forensic accelerator engine 20 without affecting the suspect drive. The computer forensic accelerator engine 20 is provided with the ability to communicate with the analysis device 22 to receive various instructions including parameters (such as a list of website names) from the analysis device 22 prior to and during data acquisition and analysis”) The citation discloses at FIG. 5, Fig. 6, and Col 7, lines 63 – 67, and col 8, lines 1 – 18, and Col 9, lines 58 – 65 the Analysis and Processing Device (APD) as a stand alone accelerator for performing the analyzing data from the suspect computer and send the analyzed data to the Analysis Unit. Since Analysis and Processing Device (APD) as a stand alone accelerator, the accelerator can operate without the provision of the CPU. At Col 6, lines 51 – 59 discloses the protocol for the computer forensic accelerator engine 20 is provided with the ability to communicate with the analysis device 22
Santan, in view of Ravid, Vaibhav, and Chapman disclose the Analysis and Processing Device (APD) as a stand alone accelerator can communicate with the analysis device 22, but fails to teach implements an Open Systems Interconnect (OSI) model for connection to the remote computing system agent
However, Loafman teaches wherein the SAP module implements an Open Systems Interconnect (OSI) model for connection to the remote computing system agent (FIG. 4A, 4B, and Col 9, lines 24 – 32: “In FIGS. 4A and 4B, moving from the start block, process 400 advances to block 402 where a first guest application running in a Virtual Machine on a node requests access to a second guest application running in its own Virtual Machine. The first guest application that is running as process within it's VM initiates a request to access a second application through standard network communication protocol. In at least a portion of the various embodiments, the request begins at the Application Layer of the OSI communication Stack.”) and lines 39 – 44: “At block 404, the request is passed to the application (top) layer of a seven layer communication protocol stack such as the Open Sources Interconnection (OSI) reference model.”) The citation discloses the concept of the first guest application running in a Virtual Machine on a node requests access to a second guest application running in its own Virtual Machine using the Open Sources Interconnection (OSI) reference model.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the SAP module implements an Open Systems Interconnect (OSI) model for connection to the remote computing system agent, as taught in Loafman’s invention into Santan, Ravid, Vaibhav, and Chapman’s invention because the OSI model is a widely accepted framework that breaks down communication into separate layers and each layer has specific functions and responsibilities, and the model provides a clear structure for data to be sent, received, and managed. As a result, the model improves compatibility with different network system, and this makes the system easier to integrate and troubleshoot, and more reliable and flexible operation.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Santan, Ravid, Vaibhav, and Chapman, in further view of Sastry et al. US Pub. No. US 20200371759 A1 (hereafter Sastry)
Regarding claim 5, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 3, but fails to teach wherein the application module further provides a high-level synthesis (HSL) interface for the application kernel.
However, Sastry teaches wherein the application module further provides a high-level synthesis (HSL) interface for the application kernel. (abstract: “For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device” and FIG. 33 and [0294]: “The example software architecture 3300 of FIG. 33 may be used in cases where the application, e.g., the data flow graph, specifies one or more High-Level Synthesis (HLS) kernels for implementation in the PL 214”) The citation discloses the High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the application module further provides a high-level synthesis (HSL) interface for the application kernel, as taught in Sastry’s invention into Santan, Ravid, Vaibhav, and Chapman’s invention because the HSL interface would benefit in improving development speed, productivity, flexibility, and make the system easier to maintain, since the HSL interface allow the software developers implement higher level programming language (such as C/C++) rather than low level hardware description languages.
Claims 6, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Santan, Ravid, Vaibhav, and Chapman, in further view of Loafman et al. US Pat. No. US 8671414 B1 (hereafter Loafman)
Regarding claim 6, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 1, but fails to teach wherein the SW-BSP further comprises a board support module providing a physical layer connection to the network fabric.
However, Loafman teaches wherein the SW-BSP further comprises a board support module providing a physical layer connection to the network fabric. (FIG. 3, FIG 4A, 4B, Col 3, lines 13 – 20: “distributed data storage clusters may be built with one or more data storage nodes and one or more compute accelerator nodes. A data storage cluster can be interconnected by a high-bandwidth, low latency network backplane. Typically, compute processes accessing the distributed data storage cluster communicate through a high-latency, relatively low-bandwidth front side network connection, such as Ethernet, and the like.” and Col 9 lines 65 – 67 - Col 10 lines 1 – 12: “If at block 406 it is determined whether the first application is targeting access to a second application running on a different physical machine/node, or the target is not recognized as running on a co-resident VM, then the process moves to block 408 and employs the presentation layer offered by the network communication protocol running on the VM for the first guest application. Next, the process moves down through the other blocks for the communication protocol layers for the VM for the first guest application, e.g., 410 (Session layer), 412 (Transport layer), 414 (Network Layer), 416 (Data Link Layer), and 418 (Physical Layer). At block 428, the request for access is received from block 418 at the lowest level of the communication stack, such as, the Physical Layer, that corresponds to the VM for the second guest application.”) The citation discloses the physical layer 418 is one of the layers offered by the network communication protocol running on the VM for the first guest application.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the SW-BSP further comprises a board support module providing a physical layer connection to the network fabric, as taught in Loafman’s invention into Santan, Ravid, Vaibhav, and Chapman’s invention because it would add important improvements by ensuring stable hardware communication, since this module handles the data transfer needed to physically connect the reconfigurable hardware accelerator to the network. Therefore, it is easier to deploy the system across different hardware setups and enhance performance.
Regarding claim 7, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 6, and Santan further teaches wherein the board support module further implements memory, power, and kernel control for the SW-BSP. (Santan - FIG. 2, col 5, lines 43 – 46: “Accelerator driver 205 may be executed by processor 105 to communicate with accelerator 150. In one aspect, accelerator driver 205 is implemented as a kernel mode device driver.” and Col 13, lines 7 – 9: “accelerator driver 205 loads configuration bitstream 412 into configuration memory of programmable IC 220” and Col 12, lines 24 – 43: “In implementing the Tandem boot process, upon powering on, programmable IC 220 automatically accesses flash memory 225 (not shown) to obtain and load the first partial configuration bitstream (e.g., a first stage boot configuration bitstream). The hardwired circuitry of programmable IC 220, e.g., a configuration controller, is configured to access flash memory 225 and load the first partial configuration bitstream into configuration memory responsive to power on thereby implementing region 402 using programmable circuitry of programmable IC 220. While not shown, one skilled in the art will appreciate that the configuration controller stores the first partial configuration bitstream into appropriate configuration memory cells of programmable IC 220. The configuration controller is distinct from other processors that execute user program code. The configuration controller does not execute user program code, but rather is reserved exclusively for processing configuration bitstreams to implement circuit designs within programmable IC 220.” and Col 26, lines 58 – 64: “A method of managing an accelerator may include, responsive to determining a first container including a first configuration file and a second configuration file, caching, using a host processor, the second configuration file within a local memory of the host processor and providing, using the host processor, the first configuration file to a device of the accelerator.”) The citation discloses the accelerator driver 205 is implemented as the kernel device driver for the programmable IC 220 or the device of the accelerator. At Col 12, lines 24 – 43 discloses the configuration controller that controls the configuration memory and power of the programmable IC 220.
Regarding claim 8, Santan, in view of Ravid, Vaibhav, and Chapman, discloses the non-transitory computer-readable medium of claim 6, and Santan further teaches wherein the board support module further provides partial reconfiguration logic to dynamically reconfigure the reconfigurable hardware accelerator during runtime (Col 13, lines 15 – 25: “In general, partial reconfiguration is a process where a region of a programmable IC, e.g., partial reconfiguration region 420, may be dynamically reconfigured by loading different partial configuration bitstreams during operation of programmable IC 220. Each of the partial configuration bitstreams, for example, may specify different circuitry and/or a different system than previously implemented in the region. The region may undergo modification through partial reconfiguration while other regions, i.e., region 402, of programmable IC 220 continue to operate without interruption.” and Col 14, lines 40 – 53: “Accordingly, accelerator driver 205 locates the particular container needed to implement the specialized circuitry (i.e., circuit 522) for the task within partial reconfiguration region 420. In this case, accelerator driver 205 locates container 502. Accelerator driver 205 prepares programmable IC 220 for dynamic partial reconfiguration by sending clearing configuration bitstream 414 from local memory 120 to programmable IC 220 via network adapter 404. Clearing configuration bitstream 414 clears partial reconfiguration region 420 (e.g., clearing circuit 422). Accelerator driver 205 further reads configuration bitstream 504 from container 502 and sends configuration bitstream 504 to programmable IC 220 via network adapter 404 thereby implementing circuit 522 within partial reconfiguration region 420”) The citation discloses the partial reconfiguration loading different partial configuration bitstreams during operation of programmable IC 220, while the programmable IC 220 continue to operate without interruption.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Santan Ravid, Vaibhav, Chapman, and Loafman, in further view of Seshadri et al. US Pat. No. US 10776142 B1 (hereafter Seshadri)
Regarding claim 9, Santan, in view of Ravid, Vaibhav, Chapman, and Loafman, discloses the non-transitory computer-readable medium of claim 6, but fails to teaches wherein the board support module further receives and forwards SAP packets to the SAP module.
However, Seshadri teaches wherein the board support module further receives and forwards SAP packets to the SAP module. Col 23, lines 1 – 23: “FIG. 7 illustrates an example of a computing device 700. Functionality and/or several components of the computing device 700 may be used without limitation with other embodiments disclosed elsewhere in this disclosure, without limitations. A computing device 700 may facilitate processing of packets and/or forwarding of packets from the computing device 700 to another device. As referred to herein, a “packet” or “network packet” may refer to a variable or fixed unit of data. In some instances, a packet may include a packet header and a packet payload. The packet header may include information associated with the packet, such as the source, destination, quality of service parameters, length, protocol, routing labels, error correction information, etc. In certain implementations, one packet header may indicate information associated with a series of packets, such as a burst transaction. In some implementations, the computing device 700 may be the recipient and/or generator of packets. In some implementations, the computing device 700 may modify the contents of the packet before forwarding the packet to another device. The computing device 700 may be a peripheral device coupled to another computing device, a switch, a router or any other suitable device enabled for receiving and forwarding packets.”) The citation discloses the computing device 700 capable of receiving and forwarding packets to another device.
The teaching of Seshadri does not clearly indicate the packets are the SAP packets and the receiving device/module is the SAP module. The SAP module is taught by Ravid at FIG. 5, Fig. 6, and Col 7, lines 63 – 67, and col 8, lines 1 – 18, and Col 9, lines 58 – 65, as explain in the rejection of claim 1.
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to add the wherein the board support module further receives and forwards SAP packets to the SAP module, as taught in Seshadri’s invention into Santan, Ravid, Vaibhav, Chapman, and Loafman’s invention because this method enable the board support module acts as a bridge between the physical network and the SAP module for receiving and forwarding SAP packets. Therefore, this method improves the flow of communication between the hardware accelerator and the computing system, reduce delays, simplify data handling, and make the overall computing system design more efficient and easier to manage and control.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20150229310 A1: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The FPGA unit also includes a controller configured to establish a first communication channel between the first interface unit and a processing module. The controller may establish the first communication channel between the first interface unit and a first external module/device, such as a sensor, an actuator, a controller for such a device, etc., so that the user design can access the external module/device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN M NGUYEN whose telephone number is (703)756-1599. The examiner can normally be reached Monday-Friday: 9:30am - 5:30PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN M NGUYEN/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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