DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2016/0111600) in view of Cho (US 2015/0011031).
Regarding claim 1, Chae discloses in figure 16 an optoelectronic semiconductor device comprising:
a carrier (101) [0180] comprising a patterned surface (top of 101 may comprise patterned substrate PSS [0180]);
a semiconductor layer sequence (111, 112, 113) [0181] arranged on the carrier (101), the semiconductor layer sequence (111, 112, 113) comprising:
a first semiconductor layer (113) having a first surface (4A – see modified figure 16 below);
a second semiconductor layer (111) having a first surface (6A – see modified figure 16 below);
a first main surface (3A - see modified figure 16 below-) and a second main surface (3B- see modified figure 16 below) opposite the first main surface (3A), wherein the first surfaces (4A, 6A) of the first (113) and second (111) semiconductor layers are at least partly arranged at the first main surface (3A – see modified figure 16 below), and wherein the second main surface (3B) faces the patterned surface (top of 101) of the carrier (101);
at least one side face (3C – see modified figure 16 below) connecting the first (3A) and second main surfaces (3B);
a directionally reflective layer (132, figure 18) [0191]; and
a planarization layer (131, 150) [0194] [0195] arranged between the patterned surface (top of 101) and the directionally reflective layer (132), wherein the patterned surface (top of 101) is arranged on a side of the carrier (101) facing the semiconductor layer sequence (111, 112, 113), wherein the carrier (101) comprises structural elements at the patterned surface (top of 101) [0180].
Chae does not disclose, in a first region of the carrier, the planarization layer is arranged in the interspaces and in a vertical direction extends at least to upper ends of the structural elements.
However, Cho discloses an analogous device, in figure 8, in a first region (at least a portion of figure 8) of the carrier (10), the planarization layer (50) is arranged in the interspaces (between 40s) and in a vertical direction (upwards as shown in figure 8) extends at least to upper ends of the structural elements (40).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the device of Chae to include the planarization layer filling the interspaces of the patterned substrate in order to protect the LED in light of the disclosure of Cho.
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Top: fig. 1A of instant application designating various surfaces
Bottom: annotated fig. 16 labeling corresponding surfaces of Chae as described above
Regarding claim 3, Chae discloses, in the first region (region to the right of the right semiconductor stack of 112/113), the planarization layer (131/150) comprises a surface (top surface of 131) facing the directionally reflective layer (132); wherein the surface (top surface of 131) has a planar (see figure 18 for zoomed in view) [0178] or concavely curved shape.
Regarding claim 4, Chae discloses, in the first region (region to the right of the right stack of 112/113), the carrier (101) is laterally projecting beyond the second semiconductor layer (111).
Regarding claim 5, Chae discloses parts of the semiconductor layer sequence (111, 112, 113) are arranged in the interspaces of the structural elements (patterned substrate protrusions on top of 101) in a second region (region below semiconductor 112, 113 stack) of the carrier (101).
Although not clearly shown by Chae, in forming a semiconductor layer (111) on top of a patterned substrate, the layer will be arranged in the interspaces of the structural elements as shown by Cho in figure 8.
Regarding claim 6, Chae discloses the optoelectronic semiconductor device according to claim 1, wherein the planarization layer (131/150) comprises at least one of SiO2 and spin-on glass [0189].
Regarding claim 7, Chae discloses the optoelectronic semiconductor device according to claim 1, wherein the planarization layer (131/150) is arranged on the at least one side face of the semiconductor layer sequence (111, 112, 113).
Regarding claim 8, Chae discloses the optoelectronic semiconductor device according to claim 1, wherein the planarization layer (131/150) at least partly covers the at least one side face of the semiconductor layer sequence (111, 112, 113).
Regarding claim 9, Chae discloses the optoelectronic semiconductor device according to claim 1, wherein the planarization layer (131/150) at least partly covers the first main surface (3A) of the semiconductor layer sequence (111, 112, 113). Regarding claim 10, Chae discloses the optoelectronic semiconductor device according to claim 1, further comprising an omnidirectionally reflective layer (140) [0198] arranged on a side of the directionally reflective layer (132) facing away from the carrier (101).
Regarding claim 12, Chae discloses the optoelectronic semiconductor device according to claim 1, wherein the second semiconductor layer laterally (111) projects beyond the first semiconductor layer (113).
Regarding claim 13, Chae discloses the optoelectronic semiconductor device according to claim 1, further comprising a dielectric layer (lower layer of 131 stack of multiple layers) [0189] arranged between the planarization layer (131/150) and at least one of the semiconductor layer sequence (111, 112, 113) and the carrier (101).
Regarding claim 14, Chae discloses a method for producing an optoelectronic semiconductor device in figure 16; wherein the method comprises:
providing a carrier (101) [0180] comprising a patterned surface (top of 101 may comprise patterned substrate PSS [0180]);
providing a semiconductor layer sequence (111, 112, 113) [0181] comprising:
a first semiconductor layer (113) having a first surface (4A – see modified fig. 16 below);
a second semiconductor layer (111) having a first surface (6A);
a first main surface (3A) and a second main surface (3B) opposite the first main surface (3A), wherein the first surfaces (4A, 6A) of the first (113) and second (111) semiconductor layers are at least partly arranged at the first main surface (3A), and wherein the second main surface (3B) faces the patterned surface (top of 101) of the carrier (101) [0180];
at least one side face (3C) connecting the first (3A) and second (3B) main surfaces, applying a planarization layer (131/150) [0194] [0195] on the patterned surface (top of 101) [0180]; and
applying a directionally reflective layer (132) [0191] on the planarization layer (131/150) (see annotated fig. 16 above), wherein the carrier (101) comprises structural elements at the patterned surface (top of 101) [0180].
Chae does not disclose, in a first region of the carrier, the planarization layer is arranged in the interspaces and in a vertical direction extends at least to upper ends of the structural elements.
However, Cho discloses an analogous method, in figure 8, in a first region (at least a portion of figure 8) of the carrier (10), the planarization layer (50) is arranged in the interspaces (between 40s) and in a vertical direction (upwards as shown in figure 8) extends at least to upper ends of the structural elements (40).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the method of Chae to include the planarization layer filling the interspaces of the patterned substrate in order to protect the LED in light of the disclosure of Cho.
Regarding claim 16, Chae discloses the method according to claim 14, wherein the planarization layer (131/150) is formed by Plasma-Enhanced Chemical Vapor Deposition [0200].
Claims 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chae in view of Cho, in further view of Wegleiter (US 6531405).
Regarding claim 11, Chae in view of Cho does not disclose wherein the semiconductor layer sequence (111, 112, 113) is patterned at the at least one side face such that it comprises structural elements.
However, Wegleiter discloses an optoelectronic semiconductor device in figure 3c wherein the semiconductor layer sequence (2, 3, 4) (Col. 6, lines 59-65) is patterned at the at least one side face such that it comprises structural elements (Col. 6, line 66 – Col. 7, line 6).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the device of Chae in view of Cho to include patterning at least one side of the semiconductor layer sequence in order to increase the proportion of the radiation generated that impinges on the surface of the semiconductor layer at an angle smaller than the critical angle of total reflection in light of the disclosure of Wegleiter (Col. 2, lines 38-44).
Regarding claim 17, Chae in view of Cho does not disclose wherein the semiconductor layer sequence (111, 112, 113) is patterned at the at least one side surface by wet chemical etching such that it comprises structural elements.
However, Wegleiter discloses wherein the semiconductor layer sequence (2, 3, 4) (Col. 6, lines 59-65) is patterned at the at least one side surface by wet chemical etching (Col. 3, lines 40-55) such that it comprises structural elements (Col. 6, line 66 – Col. 7, line 6).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Chae in view of Cho to include patterning at least one side of the semiconductor layer sequence by wet etching in order to increase the proportion of the radiation generated that impinges on the surface of the semiconductor layer at an angle smaller than the critical angle of total reflection in light of the disclosure of Wegleiter (Col. 2, lines 38-44).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chae in view of Cho and Chin (JP H08-241891).
Regarding claim 15, Chae in view of Cho does not disclose wherein the method is further comprising applying in a first region of the carrier a volume of spin-on glass on the patterned surface (top surface of 101) and rotating the carrier (101) such that the spin-on glass covers the at least one side face to form the planarization layer (131/150).
However, Chin discloses in figure 2 a method comprising applying in a first region of the carrier (10) [0017] a volume of spin-on glass (24) [0022] on the surface and rotating [0022] the carrier (10) such that the spin-on glass covers the at least one side face (side of the mesa comprising 11, 12, and 13) [0017] to form the planarization layer (24).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Chae in view of Cho to include forming the planarization layer using spin-on glass and rotating the carrier in order to uniformly spread the glass across the carrier in light of the disclosure of Chin [0022].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yun (US 2018/0106941), Kwon (US 2017/0338438), Kim (US 2016/0211307), Nishimura (US 2018/0294428), Sato (US 2017/0170248), and Lien (US 2014/0132569) discloses light emitting devices with planarization layer arranged in interspaces and in a vertical direction extends to upper ends of structural elements.
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/BUMSUK WON/Supervisory Patent Examiner, Art Unit 2872