Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12,14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn (USPN 2006/0001789).
With regard to claim 1,
Ahn discloses an array substrate, having a device region (withing 90) and a sealant region (corresponding to 90) enclosing the device region, wherein the array substrate comprises: a substrate (80); an array driving layer (23/25) disposed on the substrate, wherein the array substrate comprises at least one of conductive layers (23/25) and at least one insulation layer (82/86) located on a side of at least one of the conductive layers away from the substrate, and the at least one of the conductive layers comprises a conductive pattern located in the sealant region (see fig. 17); and wherein the insulation layer is only located in the device region correspondingly; or the insulation layer is correspondingly located in the device region and the sealant region, and a number of layers of the insulation layer located in the sealant region is less than a number of layers of the insulation layer located in the device region (see fig. 18A/18E).
With regard to claim 2,
Ahn discloses the array substrate as claimed in claim 1, wherein a surface area of the array driving layer (23/25) is greater than a projection area of an orthogonal projection of the array driving layer on the substrate in the sealant region (see fig. 18E).
With regard to claim 3,
Ahn discloses the array substrate as claimed in claim 2, wherein in the sealant region, the at least one insulation layer (82/86) is disposed on a side of the conductive pattern away from the substrate (see fig. 18A), the insulation layer comprises a first coverage layer (82) corresponding to the conductive pattern, a surface area of the first coverage layer is greater than a projection area of an orthogonal projection of the first coverage layer on the substrate (see fig. 18F).
With regard to claim 4,5,
Ahn discloses the array substrate as claimed in claims 2,3 wherein in the sealant region, at least one of the conductive layers (25) is disposed on the side of the conductive pattern away from the substrate (See fig. 18F), at least one of the conductive layers comprises a second coverage layer (25) corresponding to the conductive pattern, and a surface area of the second coverage layer is greater than a projection area of an orthogonal projection of the second coverage layer on the substrate (See fig. 18F).
With regard to claim 6,
Ahn discloses the array substrate as claimed in claim 1, wherein in the sealant region, a distance of a boundary of the insulation layer to the device region is less than a distance of a boundary on a side of the sealant region away from the device region to the device region, and an orthogonal projection of the insulation layer on the substrate covers an orthogonal projection of the conductive pattern on the substrate; or in the sealant region, at least one of the conductive layers is disposed on a side of the conductive pattern away from the substrate, a distance of a boundary of at least one of the conductive layers to the device region is less than the distance of the boundary on the side of the sealant region away from the device region to the device region, and the orthogonal projection of the insulation layer on the substrate covers the orthogonal projection of the conductive pattern on the substrate (See fig. 17).
With regard to claim 7,
Ahn discloses the array substrate as claimed in claim 1, wherein the conductive pattern comprises a bottom surface facing toward the substrate and a lateral surface connected to the bottom surface, an included angle formed between the lateral surface and the bottom surface ranges from 60°-90° (see fig. 18F).
With regard to claim 8,
Ahn discloses a liquid crystal display panel (See paragraph 3), comprising the array substrate as claimed in claim 1, and comprising an opposite substrate (100) disposed opposite to the array substrate, a liquid crystal layer (see paragraph 19) located between the array substrate and the opposite substrate, and a sealant (90) for bonding the array substrate and the opposite substrate; wherein the sealant is bonded to a part of the array substrate corresponding to the sealant region (see fig. 9B).
With regard to claim 9,
Ahn discloses the liquid crystal display panel as claimed in claim 8, wherein a contact area between the array substrate and the sealant is greater than a projection area of an orthogonal projection of the sealant on the array substrate (See fig. 9B).
With regard to claim 10,
Ahn discloses the liquid crystal display panel as claimed in claim 9, wherein in the sealant region, the at least one insulation layer (82/86) is disposed on a side of the conductive pattern away from the substrate (See fig. 18F), the insulation layer comprises a first coverage layer (82) corresponding to the conductive pattern, a surface area of the first coverage layer is greater than a projection area of an orthogonal projection of the first coverage layer on the substrate (See fig. 18F).
With regard to claim 11,
Ahn discloses the liquid crystal display panel as claimed in claim 10, wherein in the sealant region, at least one of the conductive layers (25) is disposed on the side of the conductive pattern away from the substrate, at least one of the conductive layers comprises a second coverage layer (86) corresponding to the conductive pattern, and a surface area of the second coverage layer is greater than a projection area of an orthogonal projection of the second coverage layer on the substrate (See fig. 18F).
With regard to claim 12,
Ahn discloses the liquid crystal display panel as claimed in claim 9, wherein a part of the sealant (90) away from the device region contact to the substrate (80) along at least one of the conductive layers and the lateral surface of the insulation layer; or the part of the sealant away from the device region contact to the substrate along at least one of the conductive layers or the lateral surface of the insulation layer (see fig. 18F).
With regard to claim 14,
Ahn discloses the liquid crystal display panel as claimed in claim 8, wherein the conductive pattern (23/25) comprises a bottom surface facing toward the substrate and a lateral surface connected to the bottom surface, an included angle formed between the lateral surface and the bottom surface ranges from 60°-90° (See fig. 18F).
With regard to claim 15,
Ahn disclose an array substrate, having a device region (Within 80) and a sealant region (corresponding to 90) enclosing the device region, wherein the array substrate comprises: a substrate (80); an array driving layer (23/25) disposed on the substrate, wherein the array substrate extends from the device region to the sealant region (See fig. 18A), the array substrate comprises at least one of conductive layers (23/25) and at least one insulation layer (82/86) located on a side of at least one of the conductive layers away from the substrate, and at least one of the conductive layers comprises a conductive pattern located in the sealant region (See fig. 17); and wherein the insulation layer is only located in the device region correspondingly; or the insulation layer is correspondingly located in the device region and the sealant region, and a number of layers of the insulation layer located in the sealant region is less than a number of layers of the insulation layer located in the device region (see figs 18A/18E).
With regard to claim 16,
Ahn discloses the array substrate as claimed in claim 15, wherein a surface area of the array driving layer (23/25) is greater than a projection area of an orthogonal projection of the array driving layer on the substrate in the sealant region (see fig. 18F).
With regard to claim 17,
Ahn discloses the array substrate as claimed in claim 16, wherein in the sealant region, the at least one insulation layer (82/86) is disposed on a side of the conductive pattern (23/25) away from the substrate, the insulation layer comprises a first coverage layer (82) corresponding to the conductive pattern, a surface area of the first coverage layer is greater than a projection area of an orthogonal projection of the first coverage layer on the substrate (See fig 18F).
With regard to claim 18,
Ahn discloses the array substrate as claimed in claim 16, wherein in the sealant region, at least one of the conductive layers (25) is disposed on the side of the conductive pattern away from the substrate, at least one of the conductive layers comprises a second coverage layer (25) corresponding to the conductive pattern, and a surface area of the second coverage layer is greater than a projection area of an orthogonal projection of the second coverage layer on the substrate (See fig 18F).
With regard to claim 19,
Ahn discloses the array substrate as claimed in claim 15, wherein in the sealant region, a distance of a boundary of the insulation layer to the device region is less than a distance of a boundary on a side of the sealant region away from the device region to the device region, and an orthogonal projection of the insulation layer on the substrate covers an orthogonal projection of the conductive pattern on the substrate; or in the sealant region, at least one of the conductive layers is disposed on a side of the conductive pattern away from the substrate, a distance of a boundary of at least one of the conductive layers to the device region is less than the distance of the boundary on the side of the sealant region away from the device region to the device region, and the orthogonal projection of the insulation layer on the substrate covers the orthogonal projection of the conductive pattern on the substrate (see fig, 17).
With regard to claim 20,
Ahn discloses the array substrate as claimed in claim 15, wherein the conductive pattern comprises a bottom surface facing toward the substrate and a lateral surface connected to the bottom surface, an included angle formed between the lateral surface and the bottom surface ranges from 60°-90° (See fig. 18F).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn (USPN 2006/0001789 in view of Cheng et al. (USPN 2012/0327355).
With regard to claim 13,
Ahn discloses the liquid crystal display panel as claimed in claim 9. While Ahn does not disclose a display wherein an orthogonal projection of the insulation layer on the substrate is within the device region, and the sealant directly contacts to at least one of the conductive layers, Cheng et al. do disclose such a configuration ( insulation layer PV2 in device region, sealant 140 contacts conductive layer 112/114). It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate this concept of Cheng et al. into the panel of Ahn in order to try to improve connection of the sealant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. USPN 2009/0242885, 2003/0103181, 2021/0325717.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher Raabe whose telephone number is (571)272-8434. The examiner can normally be reached M-F 0530-1430.
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/CHRISTOPHER M RAABE/Primary Examiner, Art Unit 2875
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