DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Amendment filed on May 5, 2026. Claims 1, 4-6, 8-9, and 12 are amended. Claim 10 is cancelled. Claims 16-21 are new. Claims 1-9 and 11-21 are pending in the case. Claims 1, 8, and 12 are the independent claims.
This action is final.
Applicant’s Response
In the Amendment filed on May 5, 2026, Applicant amended the claims and provided arguments in response to the rejections of the claims under 35 USC 101, 102, and 103.
Response to Argument/Amendment
Applicant’s amendments to the claims in response to the rejections of the claims under 35 USC 101, 102, and 103 are acknowledged, and have been fully considered. Each of Applicant’s corresponding arguments are persuasive, and the rejections are withdrawn. However, new grounds of rejection are provided below.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8, 9, 11, 16-18, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sridharan et al. (US 20180322387 A1), further in view of Zhang et al. (US 20220035762 A1).
With respect to claim 1, Sridharan teaches a device, comprising: a processing resource including a processor; and memory resource storing instructions that, when executed by the processing resource, cause the processing resource to implement a neural network representing at least a portion of a knowledge base (e.g. paragraph 0176, knowledge instilled within neural network during initial training; paragraphs 0349-0350, described embodiments implemented by microchips/integrated circuits, software stored by a memory device and executed by a microprocessor, etc.; media having stored thereon instructions that, when executed by computer, carrying out described operations);
wherein a logical node of the neural network is connected to a plurality of child nodes via a logical edge (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0179, Fig. 12, describing model parallelism implementation 1202 in which the neural network is split such that each layer is assigned to a respective computational node; Figs. 16A-C, showing nodes 1610/1620; paragraph 0227, Fig. 17A, nodes of a multi-node compute system; paragraph 0233, Fig. 19B, multi-node system 1920 including producer node 1930 and consumer node 1940; i.e. as can be seen in Figs. 10 and 12, where a layer containing at least a single neural network node is assigned/implemented on a single physical computational node, the computational node to which the layer (and therefore the constituent node) is assigned can be considered to be a physical device implementing the layer/node, forming a logical node of the neural network and is connected to a plurality of child nodes via a logical edge) and is to:
receive a first node instruction (e.g. paragraph 0143, data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other node);
generate an output change value based on the received first node instruction (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950); and
transmit the output change value and the first node instruction to the logical edge (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950); and
wherein the logical edge of the neural network (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0209, Fig. 15B, describing MLSL architecture 1511 as including machine learning specific abstractions including layer-to-layer communication abstractions for implementing communication patterns for layers/parallelisms, where communications for (i.e. between) layers are enabled via communication modules 1517, messaging library 1519, and high performance communications fabric 1521, and also enable intelligent messaging scheduling across neural network layers; paragraph 0210, communication module 1517 includes logic to drive underlying messaging library 1519 enabling transmitting data between various compute nodes; logic to optimize network bandwidth and enable low latency communications, specified processor resources tasked with managing distributed communication; compute/communication resources; paragraph 0211, communication module 1517 enabling communication between processing nodes; paragraph 0212, messaging library 1519 using communication routines to transmit data over high performance communications fabric 1521; Figs. 16A-C, showing links/connections between nodes 1610/1620; paragraph 0222, Fig. 16C, receive buffer receiving set of weight deltas generated by nodes; summation unit 1636 (shown in Fig. 16 as being positioned between, for purposes of receiving weight delta, etc., nodes 1631) may be a separate control node which transmits new/updated set of weights to each node; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0227, Fig. 17A, interconnects provided via links 816, 1716, 1708; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0233, Fig. 19B, showing shared memory 1950 on communication path between nodes 1930 and 1940, which may be as distributed and shared virtual address space mapped across multiple nodes; i.e. the combined hardware and software functionalities providing communication capabilities between nodes (both nodes of the neural network and their corresponding compute nodes), including the shared memory implementation, communications fabric, and associated processing resources (such as summation units shared by nodes, etc.) and library routines for implementing communications, collectively provide the logical edges between the nodes; compare with specification of the instant application at paragraph 0012, indicating that “a logical node, logical edge, and/or logical device can include a logical partition of memory resources and/or processing resources….the processing resource can be a virtual processing resource….”) is to:
receive the output change value and the first node instruction from the logical node (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function based on coefficients/weights associated with edges connecting layers (and therefore nodes); paragraph 0222, Fig. 16C, receive buffer of summation unit 1636 receiving set of weight deltas generated by nodes; paragraph 0233, tensor data written to memory 1950 (i.e. by a producer node));
generate second node instructions based on the output change value and the first node instruction (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)); and
transmit the second node instructions (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)).
Sridharan does not explicitly disclose wherein the logical edge of the neural network is to identify, based on the first node instruction, a subset of child nodes of the plurality of child nodes, or that the second node instructions are transmitted to the subset of child nodes. However, Zhang teaches wherein the logical edge of the neural network is to identify, based on the first node instruction, a subset of child nodes of the plurality of child nodes, or that the second node instructions are transmitted to the subset of child nodes (e.g. paragraphs 0186-0187, receiving data operation signal with type flag bit; determining operation according to type flag; paragraphs 0189-0190, data operation signal includes data reception flag bit; determining target machine learning unit that receives the input data according to value of the data reception flag bit; paragraph 0438, computation instruction including operation fields and an opcode; computation instruction including neural network operation instruction; paragraph 0450, primary processing circuit determining input neuron is broadcast data, the weight is distribution data, and partitioning distribution data into plurality of data blocks, and send data blocks and operation instruction to secondary processing circuits; paragraphs 0577-0581, describing neural network implementation in which neurons and weights of the neural network are partitioned and distributed to respective secondary processing circuits of the device; paragraph 0603, opcode of data operation signal used to indicate an operation type of the data operation signal, which includes a first-type flag bit; operation field used to store required data information of the data operation signal during execution, which includes second-type flag bit; data receiving flag indicates device or processing circuit such as machine learning device/MLU, operation unit, primary processing circuit, secondary processing circuit, etc.; paragraph 0604, determining specific type of data operation signal according to flag bits, locating a corresponding operation, and determining a target device for sending operated data according to the data reception flag bit; see similar descriptions with respect to paragraphs 0649-0651 and Table 5; paragraph 0614, primary processing circuit is configured to distribute input data (neuron and weight data) to plurality of secondary processing circuits; device assigning each of the machine learning units to respectively process neurons in each machine learning unit and output corresponding output data; paragraph 0659, data operation signal includes data reception flag bit used to indicate target machine learning unit that can receive input data; paragraph 0660, according to flagging of data reception flag bit, the target machine learning unit is determined; when receiving data, each machine learning unit in the machine learning device is determined according to the data reception flag bit in the data operation signal; paragraph 0722-0723, machine learning device including plurality of machine learning units; dividing and assigning subsets of neurons for each layer (such as 25 out of 100) to each machine learning unit; each machine learning unit obtaining input neuron data and weight data corresponding to assigned neurons, performing operation to obtain output neuron data, and transferring the output data; next machine learning unit using output neuron data of all neurons of a layer as input to next layer for computation; i.e. the nodes/neurons of the neural network may be divided and implemented on respective devices/units/circuits, analogous to logical/child nodes, and at a given logical node at a given layer/level (analogous to a logical parent node) the flag values of the operation code may be utilized to determine which of the different devices (implementing a given set of nodes/child nodes) the data and operation are to be distributed to, analogous to identifying, based on a node instruction, a subset of child nodes and transmitting second node instructions to those child nodes (e.g. identifying based on corresponding flags in the operation code, devices to receive the instruction, where the devices implement subsets of neurons/nodes of the neural network, such that the identifying of a receiving/target device effectively identifies the neurons/nodes implemented by that device); see also Figs. 18 and 21, showing relationships of processing circuits within computation devices such as the machine learning units, where instructions are distributed by a primary processing circuit to secondary/child processing circuits via branch processing circuits as described in paragraph 0450).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device. One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
With respect to claim 8, Sridharan teaches a non-transitory machine readable medium storing instructions executable by a processing resource to:
transmit a first node instruction to a logical node device of a neural network, wherein the first node instruction includes a node operation code, wherein the neural network represents at least a portion of a knowledge base, and wherein the logical node device is connected to a plurality of child nodes via a logical edge device (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0176, knowledge instilled within neural network during initial training; paragraph 0179, Fig. 12, describing model parallelism implementation 1202 in which the neural network is split such that each layer is assigned to a respective computational node; Figs. 16A-C, showing nodes 1610/1620; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other node; paragraph 0227, Fig. 17A, nodes of a multi-node compute system; paragraph 0228, node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; paragraph 0233, Fig. 19B, multi-node system 1920 including producer node 1930 and consumer node 1940; i.e. the message includes a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address; see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a command operation code/opcode 3104; as can be seen in Figs. 10 and 12, where a layer containing at least a single neural network node is assigned/implemented on a single physical computational node, the computational node to which the layer (and therefore the constituent node) is assigned can be considered to be a physical device implementing the layer/node, forming a logical node of the neural network and is connected to a plurality of child nodes via a logical edge);
generate, by the logical node device, an output change value based on the first node instruction (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950);
transmit, by the logical node device, the output change value and the first node instruction to the logical edge device of the neural network (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950);
receive, at the logical edge device, the output change value and the first node instruction from the logical node device (e.g. paragraph 0143, data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other node);
generate, by the logical edge device, second node instructions based on the output change value and the first node instruction (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)); and
transmit, by the logical edge device, the second node instructions to one of the logical node device or an external device (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)).
Sridharan does not explicitly disclose identify, based on the node operation code, a subset of child nodes of the plurality of child nodes, or that the second node instructions are transmitted to the subset of child nodes. However, Zhang teaches identify, based on the node operation code, a subset of child nodes of the plurality of child nodes, or that the second node instructions are transmitted to the subset of child nodes (e.g. paragraphs 0186-0187, receiving data operation signal with type flag bit; determining operation according to type flag; paragraphs 0189-0190, data operation signal includes data reception flag bit; determining target machine learning unit that receives the input data according to value of the data reception flag bit; paragraph 0438, computation instruction including operation fields and an opcode; computation instruction including neural network operation instruction; paragraph 0450, primary processing circuit determining input neuron is broadcast data, the weight is distribution data, and partitioning distribution data into plurality of data blocks, and send data blocks and operation instruction to secondary processing circuits; paragraphs 0577-0581, describing neural network implementation in which neurons and weights of the neural network are partitioned and distributed to respective secondary processing circuits of the device; paragraph 0603, opcode of data operation signal used to indicate an operation type of the data operation signal, which includes a first-type flag bit; operation field used to store required data information of the data operation signal during execution, which includes second-type flag bit; data receiving flag indicates device or processing circuit such as machine learning device/MLU, operation unit, primary processing circuit, secondary processing circuit, etc.; paragraph 0604, determining specific type of data operation signal according to flag bits, locating a corresponding operation, and determining a target device for sending operated data according to the data reception flag bit; see similar descriptions with respect to paragraphs 0649-0651 and Table 5; paragraph 0614, primary processing circuit is configured to distribute input data (neuron and weight data) to plurality of secondary processing circuits; device assigning each of the machine learning units to respectively process neurons in each machine learning unit and output corresponding output data; paragraph 0659, data operation signal includes data reception flag bit used to indicate target machine learning unit that can receive input data; paragraph 0660, according to flagging of data reception flag bit, the target machine learning unit is determined; when receiving data, each machine learning unit in the machine learning device is determined according to the data reception flag bit in the data operation signal; paragraph 0722-0723, machine learning device including plurality of machine learning units; dividing and assigning subsets of neurons for each layer (such as 25 out of 100) to each machine learning unit; each machine learning unit obtaining input neuron data and weight data corresponding to assigned neurons, performing operation to obtain output neuron data, and transferring the output data; next machine learning unit using output neuron data of all neurons of a layer as input to next layer for computation; i.e. the nodes/neurons of the neural network may be divided and implemented on respective devices/units/circuits, analogous to logical/child nodes, and at a given logical node at a given layer/level (analogous to a logical parent node) the flag values of the operation code may be utilized to determine which of the different devices (implementing a given set of nodes/child nodes) the data and operation are to be distributed to, analogous to identifying, based on a node instruction, a subset of child nodes and transmitting second node instructions to those child nodes (e.g. identifying based on corresponding flags in the operation code, devices to receive the instruction, where the devices implement subsets of neurons/nodes of the neural network, such that the identifying of a receiving/target device effectively identifies the neurons/nodes implemented by that device); see also Figs. 18 and 21, showing relationships of processing circuits within computation devices such as the machine learning units, where instructions are distributed by a primary processing circuit to secondary/child processing circuits via branch processing circuits as described in paragraph 0450).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device. One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
With respect to claim 2, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and further teaches wherein
the logical node is a logical node device (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0179, Fig. 12, describing model parallelism implementation 1202 in which the neural network is split such that each layer is assigned to a respective computational node; Figs. 16A-C, showing nodes 1610/1620; paragraph 0227, Fig. 17A, nodes of a multi-node compute system; paragraph 0233, Fig. 19B, multi-node system 1920 including producer node 1930 and consumer node 1940; i.e. as can be seen in Figs. 10 and 12, where a layer containing at least a single neural network node is assigned/implemented on a single physical computational node, the computational node to which the layer (and therefore the constituent node) is assigned can be considered to be a physical device implementing the layer/node, forming a logical node device of the neural network) and
the logical edge is a logical edge device (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0209, Fig. 15B, describing MLSL architecture 1511 as including machine learning specific abstractions including layer-to-layer communication abstractions for implementing communication patterns for layers/parallelisms, where communications for (i.e. between) layers are enabled via communication modules 1517, messaging library 1519, and high performance communications fabric 1521, and also enable intelligent messaging scheduling across neural network layers; paragraph 0210, communication module 1517 includes logic to drive underlying messaging library 1519 enabling transmitting data between various compute nodes; logic to optimize network bandwidth and enable low latency communications, specified processor resources tasked with managing distributed communication; compute/communication resources; paragraph 0211, communication module 1517 enabling communication between processing nodes; paragraph 0212, messaging library 1519 using communication routines to transmit data over high performance communications fabric 1521; Figs. 16A-C, showing links/connections between nodes 1610/1620; paragraph 0222, Fig. 16C, receive buffer receiving set of weight deltas generated by nodes; summation unit 1636 (shown in Fig. 16 as being positioned between, for purposes of receiving weight delta, etc., nodes 1631) may be a separate control node which transmits new/updated set of weights to each node; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0227, Fig. 17A, interconnects provided via links 816, 1716, 1708; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0233, Fig. 19B, showing shared memory 1950 on communication path between nodes 1930 and 1940, which may be as distributed and shared virtual address space mapped across multiple nodes; i.e. the combined hardware and software functionalities providing communication capabilities between nodes (both nodes of the neural network and their corresponding compute nodes), including the shared memory implementation, communications fabric, and associated processing resources (such as summation units shared by nodes, etc.) and library routines for implementing communications, collectively provide at least one logical edge device between the nodes).
With respect to claim 3, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the logical node is to determine the logical edge is affected by the output change value (e.g. paragraph 0222, indicating that summation unit positioned between nodes may be implemented as a separate node such as a control node; paragraph 0228, associating memory address with each node with virtual address space; writing/exchanging data within virtual address space based on corresponding messages; determining, based on write address of message, that message is destined for a given node; fabric interface, based on destination address, determining message is intended for given node; paragraph 0233, Fig. 19B, showing shared memory 1950, which may be a distributed and shared virtual address space as an edge between two nodes; i.e. based on the instruction/command/message, it may be determined that specified data is to be provided/routed to a specified node or virtual memory address space; where the specified node (such as a control node) or virtual address space is embodied as a logical edge between two nodes, this determination amounts to determining that the logical edge is to be affected by the specified data (i.e. output change value)).
With respect to claim 4, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the first node instruction and the second node instructions include a node operation code, a node input change value, and a node index (e.g. paragraph 0223, request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command).
With respect to claim 9, Sridharan in view of Zhang teaches all of the limitations of claim 8 as previously discussed, and Sridharan further teaches wherein the first node instruction includes a node index, wherein the second node instructions comprise the output change value (e.g. paragraph 0223, request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command).
With respect to claim 5, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the logical edge is to transmit the second node instructions to the logical node in response to node indices of the second node instructions being associated with the logical node (e.g. paragraph 0223, request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command).
Zhang teaches transmitting the second nodes instructions to the subset of child nodes (as previously cited).
With respect to claim 11, Sridharan in view of Zhang teaches all of the limitations of claim 8 as previously discussed, and Sridharan further teaches wherein the neural network generates a set of node instructions simultaneously (e.g. paragraph 0197, implementing model parallelism, in which different portion of the model’s (neural network’s) computations are performed simultaneous on different nodes).
With respect to claim 16, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Zhang further teaches wherein the logical edge is to identify the subset of child nodes based on a comparison between an operation code in the first node instruction and operation codes associated with the subset of child nodes (e.g. paragraph 0254, determining target machine learning unit or target operation unit from plurality of machine learning units according to types of the data operation signals; paragraph 0258-0259, determining if data operation signal is multicast type signal or broadcast type signal and whether channel of target machine learning unit specified by multicast type signal is idle, or if channels of remaining machine learning units are idle; paragraphs 0450-0457, primary processing circuit determining broadcast and distribution data and sending data blocks and operation instructions to secondary processing units; secondary processing units configured to perform operations according to the operation instruction; secondary processing circuits may include multiplication processing circuit, forwarding processing circuit, accumulation processing circuit, etc., while the operation instructions may include a computation instruction such as a matrix-mult-matrix instruction, an accumulation instruction, and activation instruction, etc.; paragraph 0600, determining specific type of the data operation signal; classification of type flag bits of the data operation signal to quickly locate the corresponding operation; paragraph 0602-0603, operation field further including indications of devices or processing circuits to receive input data, including those which can, and cannot receive data; paragraph 0604, determining specific type of data operation signal, locating corresponding operation, and determining target device for sending operated data; paragraph 0749, different types of data operations performed through different processing circuits; paragraph 0797, parsing data operation signal to determine type, according to opcode of the data operation signal, and processing the signal with the corresponding/appropriate processing circuit; see also paragraphs 0834-0840, describing different types of processing circuits to process different types of signals, use of identifiers or an arbitration circuit for determining corresponding target devices, etc.; i.e. the operation instruction and data may be sent to a corresponding unit/circuit which is configured to perform that operation instruction type).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device. One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
With respect to claim 17, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the first node instruction comprises a node index representing a connection between the logical node and at least one child node (e.g. paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit and therefore represents a connection between the sending/logical node and receiving/child node).
Zhang further teaches wherein the node index represents connections with a plurality of child nodes (e.g. paragraph 0239, data operation signal is multicast instruction which carries identifies of a plurality of target machine learning units that receive data; paragraph 0604, determining target device for sending operated data according to data reception flag bit; paragraph 0609, data returned to one or more target machine learning units according to data reception flag bit; paragraph 0612, data reception flag bit operation field flagging three MLUs as may receive data and one as cannot receive data; i.e. where, for a given sending/logical node, a data flag value indicating a plurality of units (respectively implementing subsets of neural network nodes/neurons) as being able to receive data and other units as not being able to receive data is representative of connections between the sending/logical node and receiving/child nodes (i.e. the nodes/units which are able to receive information from the sending node/unit)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device, where the flag values included in the operation code include indications of which child units/nodes are able to receive information (representative of a connection to those child units/nodes). One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
With respect to claim 18, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein a child node other than the child nodes is to retain an internal state value of the child node in response to the first node instruction (e.g. paragraph 0164, indicating that neural network nodes have respective state values; paragraph 0176, performing incremental learning allowing neural network to adapt to new data without forgetting knowledge instilled within the network during initial training; i.e. where the neural network implemented on respective computing nodes is instilled with knowledge via training, and where the nodes of the neural network each have corresponding state values, and the incremental learning of the neural network allows adaptation to new data without forgetting knowledge instilled in initial training, this is analogous to retaining the internal state associated with at least one child node and in response to the first instruction (i.e. incrementally updating to adapt to new data, where in the incremental update some child node internal states are changed, while other child node internal states are retained in order to prevent forgetting of knowledge instilled during initial training)).
Zhang further teaches remaining child nodes of the plurality of child nodes, the subset of child nodes, and internal state values of the remaining child nodes (e.g. paragraph 0450, primary processing circuit determining input neuron is broadcast data, the weight is distribution data, and partitioning distribution data into plurality of data blocks, and send data blocks and operation instruction to secondary processing circuits; paragraphs 0577-0581, describing neural network implementation in which neurons and weights of the neural network are partitioned and distributed to respective secondary processing circuits of the device; paragraph 0604, determining specific type of data operation signal according to flag bits, locating a corresponding operation, and determining a target device for sending operated data according to the data reception flag bit; paragraph 0612, data reception flag bit operation field flagging three MLUs as may receive data and one as cannot receive data; paragraph 0614, primary processing circuit is configured to distribute input data (neuron and weight data) to plurality of secondary processing circuits; device assigning each of the machine learning units to respectively process neurons in each machine learning unit and output corresponding output data; paragraph 0722-0723, machine learning device including plurality of machine learning units; dividing and assigning subsets of neurons for each layer (such as 25 out of 100) to each machine learning unit; each machine learning unit obtaining input neuron data and weight data corresponding to assigned neurons, performing operation to obtain output neuron data, and transferring the output data; next machine learning unit using output neuron data of all neurons of a layer as input to next layer for computation; i.e. there are a plurality of potential receiving/child nodes each maintaining a state of a respective neural network neuron/node, where for a given operation, data is provided to update a subset of these, where the remaining nodes not included in the subset do not receive the data and therefore retain their existing/current internal state values).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device. One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
With respect to claim 20, Sridharan in view of Zheng teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the logical node is to maintain an internal state associated with an element of the knowledge base, and update the internal state based on the first node instruction (e.g. paragraph 0164, indicating that neural network nodes have respective state values; paragraph 0176, performing incremental learning allowing neural network to adapt to new data without forgetting knowledge instilled within the network during initial training; paragraph 0200, generating updated weight data, updating weights of each layer in next forward pass; paragraph 0216, distributed training of neural network including multiple nodes; generating weight value updates; i.e. where the neural network implemented on respective computing nodes is instilled with knowledge via training, this is analogous to the neural network representing a knowledge base; where the nodes of the neural network each have corresponding state values, and the incremental learning of the neural network allows adaptation to new data without forgetting knowledge instilled in initial training, this is analogous to maintaining the internal state associated with elements of the knowledge base (i.e. the initial knowledge, encoded as state values of nodes of the neural network) and updating based on the instruction (i.e. incrementally updating to adapt to new data)).
With respect to claim 21, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the first node instruction is associated with a request to update the knowledge base (e.g. paragraph 0176, performing incremental learning allowing neural network to adapt to new data without forgetting knowledge instilled within the network during initial training; paragraph 0200, generating updated weight data, updating weights of each layer in next forward pass; paragraph 0216, distributed training of neural network including multiple nodes; generating weight value updates; i.e. where the neural network implemented on respective computing nodes is instilled with knowledge via training, this is analogous to the neural network representing a knowledge base; where this neural network is updated to adapt to new data, this is analogous to updating the knowledge base).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sridharan in view of Zhang, further in view of Malynin et al. (US 20210271965 A1).
With respect to claim 19, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein respective logical nodes of the neural network correspond to respective elements of the knowledge base (e.g. paragraph 0143, neural network nodes arranged in layers and connected via edges to nodes in adjacent layers; paragraph 0164, indicating that neural network nodes have respective state values; paragraph 0176, performing incremental learning allowing neural network to adapt to new data without forgetting knowledge instilled within the network during initial training).
Sridharan and Zhang do not explicitly disclose wherein logical edges of the neural network correspond to dependency relationships among the elements of the knowledge base. However, Malynin teaches wherein respective logical nodes of the neural network correspond to respective elements of the knowledge base, and wherein logical edges of the neural network correspond to dependency relationships among the elements of the knowledge base (e.g. paragraph 0002, graph structure representing relationships between data and operations as connections between nodes in a graph; nodes connected using directional constructs such as unidirectional arrows or connections pointing from source node to given node; paragraph 0021, transforming knowledge graph into neural network; paragraph 0038, generating calculation graph neural network from knowledge graph, the calculation graph neural network being a directed acyclic graph in which edges connecting nodes in the neural network point unidirectionally from source node to destination node).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan, Zhang, and Malynin in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning) and Zhang (directed to network on chip data processing for executing machine learning calculation), to incorporate the teachings of Malynin (directed to optimizing results of a function in a knowledge graph using neural networks) to include the capability to transform the knowledge base/graph into the neural network such that respective nodes of the neural network correspond to respective nodes/elements of the knowledge base/graph and edges of the neural network correspond to dependency relationships between the nodes/elements. One of ordinary skill would have been motivated to perform such a modification in order to optimize results generated by functions executed using a rule-baed knowledge graph as described in Malynin (abstract).
Claims 6, 7, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sridharan in view of Zhang, further in view of Bequet et al. (US 20180349508 A1).
With respect to claim 6, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the logical edge transmits a second node instruction to a device based on a node index of the second node instruction being associated with the device (e.g. paragraph 0223, request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command).
Sridharan does not explicitly disclose that the device is an external device. However, Bequet teaches that the device is an external device (e.g. paragraph 0163, node determining how data should be routed (such as which node should receive the data); paragraph 0165, grid computing system including control and worker nodes; control nodes transmitting and receiving information from one another; paragraph 0166, each worker node connected to control node, receiving and transmitting from/to the control nodes, and between each other; paragraph 0167, control node connected with external device; control node receiving data from external device; paragraph 0170, control node and external device connected; paragraph 0192, control node transmitting data with client device; query transmitted to control node; paragraph 0193, control node transmitting results of analysis; paragraph 0381, neural network defined by weights and biases applied to set of emulated neurons interconnected as nodes in a network; paragraph 0404, Fig. 24C, describing artificial neuron implementing architecture of neural network in which neurons 2577 in input layer receiving external inputs; paragraph 0406, indicating that artificial neurons 2577 incorporated into output layer provide external outputs of the neural network; i.e. nodes (implementing neurons) within the system make determinations regarding a destination for routing their output, including to another internal node, or to an external system/device).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Bequet in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Bequet (directed to automated transfer of neural network definitions among federated areas) to include the capability to transmit instructions to another device (i.e. based on an identifier, memory address, etc. of the device as taught by Sridharan), including to and from an external device (as taught by Bequet). One of ordinary skill would have been motivated to perform such a modification in order to improve accountability, reproducibility, and ease of access in use of pooled data as described in Bequet (paragraph 0079).
With respect to claim 7, Sridharan in view of Zhang teaches all of the limitations of claim 1 as previously discussed, and Sridharan further teaches wherein the logical node receives the first node instruction from a device (e.g. paragraph 0143, data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other node).
Sridharan does not explicitly disclose that the device is an external device. However, Bequet teaches that the device is an external device (e.g. paragraph 0163, node determining how data should be routed (such as which node should receive the data); paragraph 0165, grid computing system including control and worker nodes; control nodes transmitting and receiving information from one another; paragraph 0166, each worker node connected to control node, receiving and transmitting from/to the control nodes, and between each other; paragraph 0167, control node connected with external device; control node receiving data from external device; paragraph 0170, control node and external device connected; paragraph 0192, control node transmitting data with client device; query transmitted to control node; paragraph 0193, control node transmitting results of analysis; paragraph 0381, neural network defined by weights and biases applied to set of emulated neurons interconnected as nodes in a network; paragraph 0404, Fig. 24C, describing artificial neuron implementing architecture of neural network in which neurons 2577 in input layer receiving external inputs; paragraph 0406, indicating that artificial neurons 2577 incorporated into output layer provide external outputs of the neural network; i.e. nodes (implementing neurons) within the system make determinations regarding a destination for routing their output, including to another internal node, or to an external system/device).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Bequet in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Bequet (directed to automated transfer of neural network definitions among federated areas) to include the capability to transmit instructions to another device (i.e. based on an identifier, memory address, etc. of the device as taught by Sridharan), including to and from an external device (as taught by Bequet). One of ordinary skill would have been motivated to perform such a modification in order to improve accountability, reproducibility, and ease of access in use of pooled data as described in Bequet (paragraph 0079).
With respect to claim 12, Sridharan teaches a system, comprising: comprising: a processing resource including a processor; and memory resource storing instructions that, when executed by the processing resource, cause the processing resource to implement a neural network representing at least a portion of a knowledge base (e.g. paragraph 0176, knowledge instilled within neural network during initial training; paragraphs 0349-0350, described embodiments implemented by microchips/integrated circuits, software stored by a memory device and executed by a microprocessor, etc.; media having stored thereon instructions that, when executed by computer, carrying out described operations);
wherein a logical node device of the neural network is connected to a plurality of child nodes via a logical edge device (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0179, Fig. 12, describing model parallelism implementation 1202 in which the neural network is split such that each layer is assigned to a respective computational node; Figs. 16A-C, showing nodes 1610/1620; paragraph 0227, Fig. 17A, nodes of a multi-node compute system; paragraph 0233, Fig. 19B, multi-node system 1920 including producer node 1930 and consumer node 1940; i.e. as can be seen in Figs. 10 and 12, where a layer containing at least a single neural network node is assigned/implemented on a single physical computational node, the computational node to which the layer (and therefore the constituent node) is assigned can be considered to be a physical device implementing the layer/node, forming a logical node of the neural network and is connected to a plurality of child nodes via a logical edge) and is to:
receive a node instruction, wherein the node instruction includes a node operation code, a node input change value, and a node index (e.g. paragraph 0143, data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other/specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command);
generate an output change value based on the received node instruction (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950); and
transmit the output change value and the node instruction to the logical edge device (e.g. paragraph 0143, data at node propagated/fed forward to other nodes of another layer/output layer via activation function; paragraph 0200, allreduce operations performed between layers to update weights of each layer; paragraph 0217, waiting to finish receiving communication of activation data that will be used as input data for forward compute; forward compute automatically begins upon communication of completion of activation data; communicating activation data output from first node 1610 is activation data generated by first layer and used as input data for second layer/second node; paragraph 0218, describing use of backward computes, including communication of computed activation gradients, transmission of weight gradients, updated weights, etc.; paragraph 0222, each node generating weight deltas; weight deltas received in receive buffer; paragraph 0223, node sending requested block of data to other node as soon as dependencies are satisfied, such as by performing remote write; paragraph 0233, producer node produces data that will be consumed by consumer node via shared memory 1950); and
wherein the logical edge device of the neural network (e.g. paragraph 0143, describing neural networks including nodes arranged in layers via edges which are fully connected to nodes in adjacent layers, but where there are no nodes between edges within each layer; Fig. 10, illustrating an example neural network including layers 1002, 1004, 1006 each including at least one node; paragraph 0209, Fig. 15B, describing MLSL architecture 1511 as including machine learning specific abstractions including layer-to-layer communication abstractions for implementing communication patterns for layers/parallelisms, where communications for (i.e. between) layers are enabled via communication modules 1517, messaging library 1519, and high performance communications fabric 1521, and also enable intelligent messaging scheduling across neural network layers; paragraph 0210, communication module 1517 includes logic to drive underlying messaging library 1519 enabling transmitting data between various compute nodes; logic to optimize network bandwidth and enable low latency communications, specified processor resources tasked with managing distributed communication; compute/communication resources; paragraph 0211, communication module 1517 enabling communication between processing nodes; paragraph 0212, messaging library 1519 using communication routines to transmit data over high performance communications fabric 1521; Figs. 16A-C, showing links/connections between nodes 1610/1620; paragraph 0222, Fig. 16C, receive buffer receiving set of weight deltas generated by nodes; summation unit 1636 (shown in Fig. 16 as being positioned between, for purposes of receiving weight delta, etc., nodes 1631) may be a separate control node which transmits new/updated set of weights to each node; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0227, Fig. 17A, interconnects provided via links 816, 1716, 1708; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0233, Fig. 19B, showing shared memory 1950 on communication path between nodes 1930 and 1940, which may be as distributed and shared virtual address space mapped across multiple nodes; i.e. the combined hardware and software functionalities providing communication capabilities between nodes (both nodes of the neural network and their corresponding compute nodes), including the shared memory implementation, communications fabric, and associated processing resources (such as summation units shared by nodes, etc.) and library routines for implementing communications, collectively provide the logical edges between the nodes) is to:
receive the output change value and the node instruction from the logical node device (e.g. paragraph 0143, data received at nodes; paragraph 0200, Fig. 14E, describing communication operations for enabling data transfers for weight and activation data within neural network; alltoall communication operation used to transfer activation data from first layer to successive layer; alltoall operation transfers distinct data from compute nodes that generate activations to receivers; reduce scatter operation used to transfer data to final layers; paragraph 0217, first MLSL API command configuring forward compute operation for first layer at first node 1610; paragraph 0218, describing use of backward computes; paragraph 0222-0223, describing internode communication using point to point primitives, used to forward and backward propagation operations to exchange data between nodes; paragraph 0223, issuing request to node to send specific block of data to other node);
generate a sequence of node instructions based on the output change value and the node instruction (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; paragraph 0226, fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node));
transmit the sequence of node instructions to a first logical node device in response to a node index of the sequence of node instructions being associated with the first logical node device (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; routing/directing messages to corresponding destination; fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; determining, based on address, node which message is intended for;fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)); and
transmit the sequence of node instructions to a device based on a node index of the sequence of node instructions being associated with the external device (e.g. paragraph 0222, SGD 1638 of summation unit 1636 generating new set of weights, which are then transmitted to each node; paragraph 0223, block of data sent to node via transmit buffer; request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; routing/directing messages to corresponding destination; fabric interconnect logic routing data based on target memory address associated with message, write, or packet to be routed; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; determining, based on address, node which message is intended for; fabric interface determining which node message is intended for and relaying the message to the corresponding node; paragraph 0234, consumer node notified when monitored addresses written (and therefore reads the written data intended for it, resulting in transmission of the data from the memory to the consumer node)).
Sridharan does not explicitly disclose identify, based on the node operation code, a subset of child nodes of the plurality of child nodes, or wherein the sequence of node instructions correspond to the subset of child nodes. However, Zhang teaches identify, based on the node operation code, a subset of child nodes of the plurality of child nodes, wherein the sequence of node instructions correspond to the subset of child nodes (e.g. paragraphs 0186-0187, receiving data operation signal with type flag bit; determining operation according to type flag; paragraphs 0189-0190, data operation signal includes data reception flag bit; determining target machine learning unit that receives the input data according to value of the data reception flag bit; paragraph 0438, computation instruction including operation fields and an opcode; computation instruction including neural network operation instruction; paragraph 0450, primary processing circuit determining input neuron is broadcast data, the weight is distribution data, and partitioning distribution data into plurality of data blocks, and send data blocks and operation instruction to secondary processing circuits; paragraphs 0577-0581, describing neural network implementation in which neurons and weights of the neural network are partitioned and distributed to respective secondary processing circuits of the device; paragraph 0603, opcode of data operation signal used to indicate an operation type of the data operation signal, which includes a first-type flag bit; operation field used to store required data information of the data operation signal during execution, which includes second-type flag bit; data receiving flag indicates device or processing circuit such as machine learning device/MLU, operation unit, primary processing circuit, secondary processing circuit, etc.; paragraph 0604, determining specific type of data operation signal according to flag bits, locating a corresponding operation, and determining a target device for sending operated data according to the data reception flag bit; see similar descriptions with respect to paragraphs 0649-0651 and Table 5; paragraph 0614, primary processing circuit is configured to distribute input data (neuron and weight data) to plurality of secondary processing circuits; device assigning each of the machine learning units to respectively process neurons in each machine learning unit and output corresponding output data; paragraph 0659, data operation signal includes data reception flag bit used to indicate target machine learning unit that can receive input data; paragraph 0660, according to flagging of data reception flag bit, the target machine learning unit is determined; when receiving data, each machine learning unit in the machine learning device is determined according to the data reception flag bit in the data operation signal; paragraph 0722-0723, machine learning device including plurality of machine learning units; dividing and assigning subsets of neurons for each layer (such as 25 out of 100) to each machine learning unit; each machine learning unit obtaining input neuron data and weight data corresponding to assigned neurons, performing operation to obtain output neuron data, and transferring the output data; next machine learning unit using output neuron data of all neurons of a layer as input to next layer for computation; i.e. the nodes/neurons of the neural network may be divided and implemented on respective devices/units/circuits, analogous to logical/child nodes, and at a given logical node at a given layer/level (analogous to a logical parent node) the flag values of the operation code may be utilized to determine which of the different devices (implementing a given set of nodes/child nodes) the data and operation are to be distributed to, analogous to identifying, based on a node instruction, a subset of child nodes and transmitting second node instructions to those child nodes (e.g. identifying based on corresponding flags in the operation code, devices to receive the instruction, where the devices implement subsets of neurons/nodes of the neural network, such that the identifying of a receiving/target device effectively identifies the neurons/nodes implemented by that device); see also Figs. 18 and 21, showing relationships of processing circuits within computation devices such as the machine learning units, where instructions are distributed by a primary processing circuit to secondary/child processing circuits via branch processing circuits as described in paragraph 0450).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan and Zhang in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning), to incorporate the teachings of Zhang (directed to network on chip data processing for executing machine learning calculation) to include the capability to identify a subset of child/downstream nodes by identifying one or more target devices, each implementing a subset of the nodes/neurons of the neural network, according to the first node instruction, such as based on corresponding flag values included in the instruction, and to transmit second node instructions to the identified subset/implementing device. One of ordinary skill would have been motivated to perform such a modification in order to simplify data access logic, improve data access efficiency, and greatly improve access speed of the machine learning chip during data access as described in Zhang (paragraph 0604).
Sridharan does not explicitly disclose that the device is an external device. However, Bequet teaches that the device is an external device (e.g. paragraph 0163, node determining how data should be routed (such as which node should receive the data); paragraph 0165, grid computing system including control and worker nodes; control nodes transmitting and receiving information from one another; paragraph 0166, each worker node connected to control node, receiving and transmitting from/to the control nodes, and between each other; paragraph 0167, control node connected with external device; control node receiving data from external device; paragraph 0170, control node and external device connected; paragraph 0192, control node transmitting data with client device; query transmitted to control node; paragraph 0193, control node transmitting results of analysis; paragraph 0381, neural network defined by weights and biases applied to set of emulated neurons interconnected as nodes in a network; paragraph 0404, Fig. 24C, describing artificial neuron implementing architecture of neural network in which neurons 2577 in input layer receiving external inputs; paragraph 0406, indicating that artificial neurons 2577 incorporated into output layer provide external outputs of the neural network; i.e. nodes (implementing neurons) within the system make determinations regarding a destination for routing their output, including to another internal node, or to an external system/device).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan, Zhang, and Bequet in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning) and Zhang (directed to network on chip data processing for executing machine learning calculation), to incorporate the teachings of Bequet (directed to automated transfer of neural network definitions among federated areas) to include the capability to transmit instructions to another device (i.e. based on an identifier, memory address, etc. of the device as taught by Sridharan), including to and from an external device (as taught by Bequet). One of ordinary skill would have been motivated to perform such a modification in order to improve accountability, reproducibility, and ease of access in use of pooled data as described in Bequet (paragraph 0079).
With respect to claim 13, Sridharan in view of Zhang, further in view of Bequet teaches all of the limitations of claim 12 as previously discussed, and Sridharan further teaches wherein the logical node device includes a node memory map to instruct the logical node device to transmit the node instruction to the logical edge device (e.g. paragraph 0228, Fig. 17B, memory addresses within each node associated with virtual addresses within distributed virtual address space 1730; specific physical address range in each node mapped to virtual addresses associated with the node; distributed virtual address mapping exchanged between nodes such that each node is aware of the address range for each other node; paragraph 0233, Fig. 19B, shared memory 1950, shown as providing an edge between nodes 1930 and 1940, and which may be a distributed and shared virtual address space mapped across multiple nodes; i.e. where each node may include data indicating the memory mapping of nodes to the virtual address space, and where the virtual address space itself is implemented ad a logical edge between nodes, such that nodes transmit instructions, data etc. to each other via the logical edge).
With respect to claim 14, Sridharan in view of Zhang, further in view of Bequet teaches all of the limitations of claim 12 as previously discussed, and Sridharan further teaches wherein the logical edge device includes a node edge map to instruct the logical edge device to transmit the sequence of node instructions to a device (e.g. paragraph 0228, Fig. 17B, memory addresses within each node associated with virtual addresses within distributed virtual address space 1730; specific physical address range in each node mapped to virtual addresses associated with the node; distributed virtual address mapping exchanged between nodes such that each node is aware of the address range for each other node; fabric interface determining how to route/relay message based on destination address; paragraph 0233, Fig. 19B, shared memory 1950, shown as providing an edge between nodes 1930 and 1940, and which may be a distributed and shared virtual address space mapped across multiple nodes; i.e. where the virtual address space itself is implemented as a logical edge between nodes including a mapping to the respective nodes, such that the logical edge is also instructed, based on the mapping, of how/where to transmit corresponding data/instructions).
Sridharan does not explicitly disclose that the device is an external device. However, Bequet teaches that the device is an external device (e.g. paragraph 0163, node determining how data should be routed (such as which node should receive the data); paragraph 0165, grid computing system including control and worker nodes; control nodes transmitting and receiving information from one another; paragraph 0166, each worker node connected to control node, receiving and transmitting from/to the control nodes, and between each other; paragraph 0167, control node connected with external device; control node receiving data from external device; paragraph 0170, control node and external device connected; paragraph 0192, control node transmitting data with client device; query transmitted to control node; paragraph 0193, control node transmitting results of analysis; paragraph 0381, neural network defined by weights and biases applied to set of emulated neurons interconnected as nodes in a network; paragraph 0404, Fig. 24C, describing artificial neuron implementing architecture of neural network in which neurons 2577 in input layer receiving external inputs; paragraph 0406, indicating that artificial neurons 2577 incorporated into output layer provide external outputs of the neural network; i.e. nodes (implementing neurons) within the system make determinations regarding a destination for routing their output, including to another internal node, or to an external system/device).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention having the teachings of Sridharan, Zhang, and Bequet in front of him to have modified the teachings of Sridharan (directed to hardware implemented point to point communication primitives for machine learning) and Zhang (directed to network on chip data processing for executing machine learning calculation), to incorporate the teachings of Bequet (directed to automated transfer of neural network definitions among federated areas) to include the capability to transmit instructions to another device (i.e. based on an identifier, memory address, etc. of the device as taught by Sridharan), including to and from an external device (as taught by Bequet). One of ordinary skill would have been motivated to perform such a modification in order to improve accountability, reproducibility, and ease of access in use of pooled data as described in Bequet (paragraph 0079).
With respect to claim 15, Sridharan in view of Zhang, further in view of Bequet teaches all of the limitations of claim 12 as previously discussed, and Sridharan further teaches wherein the logical edge device encodes a set of partial node instructions including the node operation code and the node index (e.g. paragraph 0223, request to send specific block of data to specific node; paragraph 0226, node identifier or target memory address associated with message, write, or packet to be related; paragraph 0228, physical address ranges of nodes mapped to virtual addresses, virtual address mapping exchanged between nodes such that each node is aware of address range of other nodes; node 1 requesting data from node 3 by issuing a request for data along with providing an address within node 1’s address range; node 1 requesting synchronized write to receive buffer at node 3, requesting a read of data at address within node 3’s space; destination address; i.e. the message includes a request for specific data (analogous to a node input change value, such as weight change/update/delta data), a request for a particular operation to be performed (analogous to a node operation code, such as a request to write, or permit reading, of data at a particular address, and an identification of the related nodes (such as a node identifier, or a target memory address which is known to be associated with a particular node); see also paragraphs 0303-0304, describing instruction formats including at least an opcode 2912 defining an operation that an execution unit is to perform, along with portions related to a destination 2918, sources 2920-2924, and access/address mode 2926; see also Fig. 31A, described in paragraphs 0322-0323, showing command format 3100 including data fields identifying a target client 3102 of the command, a command operation code/opcode 3104, and relevant data for the command 3106, where the target client field (i.e. node index) is used to route command data to the appropriate unit, the opcode fields (i.e. node operation code) are used to determine the operation to perform, and the information in the data field (i.e. node input change value) is used to perform the command; it is noted that paragraph 0303 indicates that the instruction format may include a compacted instruction format 2930, which appears to be analogous to a partial set of instructions and includes opcode 2912, index 2913,destination, source, etc. information).
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain,” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting in re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (GCPA 1968)). Further, a reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill the art, including nonpreferred embodiments. Merck & Co, v. Biocraft Laboratories, 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert, denied, 493 U.S. 975 (1989). See also Upsher-Smith Labs. v. Pamlab, LLC, 412 F,3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir, 2005): Celeritas Technologies Ltd. v. Rockwell International Corp., 150 F.3d 1354, 1361, 47 USPQ2d 1516, 1522-23 (Fed. Cir. 1998).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/JEREMY L STANLEY/
Primary Examiner, Art Unit 2127
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