Prosecution Insights
Last updated: April 19, 2026
Application No. 17/800,775

CIRCUIT BOARD ASSEMBLY MANUFACTURING METHOD, CIRCUIT BOARD ASSEMBLY MANUFACTURED BY SAME, AND ELECTRIC VEHICLE INCLUDING SAME

Non-Final OA §102§103
Filed
Aug 18, 2022
Examiner
LEE, ERIC D
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Energy Solution, Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
523 granted / 644 resolved
+13.2% vs TC avg
Strong +19% interview lift
Without
With
+19.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
13 currently pending
Career history
657
Total Applications
across all art units

Statute-Specific Performance

§101
18.7%
-21.3% vs TC avg
§103
30.7%
-9.3% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 644 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6, 9-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimata et al., hereinafter Kimata, EP 1895583. Regarding Claim 1, Kimata teaches a method for manufacturing a circuit board assembly, the method comprising: preparing a mold comprising a concave portion corresponding to a shape of each of a plurality of components and a convex portion corresponding to a surface of a circuit board (Kimata Figs. 17A-17C and paragraphs [0060] and [0063], wherein die halves 80 and 81 are prepared and correspond to a mold, the die half 80 comprising concave and convex portions corresponding to components on the printed wiring board 50 and the printed wiring board itself); mounting the plurality of components on the circuit board (Kimata paragraph [0062], wherein components are mounted on the printed wiring board in advance); providing the mold at an upper side of the circuit board and preparing a protective material to be disposed on the circuit board (Kimata Figs. 17A-17C and paragraphs [0060] and [0063], wherein the die half 80 is provided above the printed wiring board and used to inject a synthetic resin coating using hot melt molding, the synthetic resin coating being a protective material); disposing the protective material on the circuit board and the components by using the mold (Kimata Figs. 17A-17C and paragraph [0064], wherein the hot melt is injected onto the components of the printed wiring board using the die halves); and curing the protective material to form a protective layer (Kimata paragraph [0065], wherein the hot melt is cooled, which is curing the hot melt to form a protective layer). Regarding Claim 2, Kimata further teaches wherein the preparing of the protective material to be disposed on the circuit board comprises disposing the protective material between the circuit board and the mold (Kimata Figs. 17A-17C and paragraph [0064], wherein the hot melt is injected onto the components of the printed wiring board using the die halves and is between the circuit board and the die halves), and the disposing of the protective material on the circuit board and the components by using the mold comprises pressing the mold to allow the protective material to be in contact with the circuit board and the components (Kimata Figs. 17A-17C and paragraph [0064], wherein the die halves press the hot melt such that the hot melt is in contact with the circuit board and its components). Regarding Claim 3, Kimata further teaches wherein the preparing of the protective material to be disposed on the circuit board comprises allowing a container, in which the protective material is stored in a melted form, to communicate with the mold (Kimata paragraph [0064], wherein the hot melt is in molten form and is inherently in a container before being injected), and the disposing of the protective material on the circuit board and the components by using the mold comprises injecting the melted protective material through the mold to allow the circuit board and the components to be in contact with the melted protective material (Kimata paragraph [0064], wherein the hot melt is injected into the die halves to contact the components of the printed wiring board). Regarding Claim 4, Kimata further teaches wherein the protective material has a width greater than that of the circuit board and a thickness greater than an interval between the concave portion and each of the components (Kimata Figs. 17A-17C, wherein the hot melt extends beyond the edges of the printed wiring board, i.e. the width is greater than that of the printed wiring board, and includes a thickness greater than an interval between a concave portion and each of the components due to the injection gate contributing to the thickness). Regarding Claim 6, Kimata further teaches wherein the mold is controlled in a range of a predetermined temperature that is greater than room temperature and less than a melting temperature of the protective material (Kimata paragraph [0065], wherein the die halves are at a temperature such that the hot melt may cool, indicating that they are at a temperature less than the melting temperature of the hot melt but also at a temperature greater than room temperature due to being in contact with the hot melt). Regarding Claim 9, Kimata further teaches wherein the concave portion has a depth greater than a height of each of the components and a width greater than that of each of the components (Kimata Figs. 17A-17C, wherein the concave portions have heights and widths greater than that of the components to allow the coating to form). Regarding Claim 10, Kimata further teaches wherein an interval between the concave portion and the convex portion corresponds to a thickness of the protective layer (Kimata Figs. 17A-17C, wherein the interval between the concave and the convex portions correspond to the thickness of the coating). Regarding Claim 11, Kimata further teaches wherein the protective material comprises a hot melt resin, a photocurable resin, a thermosetting resin, a wet resin, or a combination thereof (Kimata paragraphs [0060] and [0062], wherein the coating is a hot melt resin). Regarding Claim 12, Kimata further teaches wherein the protective layer is formed to have a same thickness on an upper portion of the circuit board and side and top surfaces of each of the components Kimata paragraph [0060], wherein the coating is formed such that the thickness is substantially uniform). Regarding Claim 13, Kimata further teaches wherein at least one region of the protective layer is formed to have a different thickness than other regions of the protective layer (Kimata Fig. 17c, wherein the thickness of the coating due to the gate is thicker than the other regions of the coating). Regarding Claim 15, Kimata teaches a circuit board assembly manufactured through the method of claim 1 (Kimata Fig. 17c and paragraph [0065], see electronic control unit equipped with a protective coating). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kimata as applied to claims 4 and 6 above, respectively, and further in view of Lemelson, US Patent No. 5,360,329. Regarding Claim 5, Kimata does not explicitly teach wherein predetermined vibration is applied to the protective material through the mold. Lemelson teaches wherein predetermined vibration is applied to the protective material through the mold (Lemelson Col. 4, Lines 14-68, wherein vibrations are applied during the molding cycle to improve the structure of the molding material). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimata and Lemelson to apply the known technique of introducing vibrations during the molding process as taught by Lemelson to improve on the molding process of Kimata, yielding the predictable results of improved material structure. Regarding Claim 7, Kimata further teaches wherein the melted protective material is injected through tubes, which is formed to pass through the convex portion (Kimata paragraph [0064], wherein the gate is a tube that is used to inject the hot melt). Kimata does not explicitly teach air is exhausted through tubes, which is formed to pass through the concave portion, among a plurality of tubes formed to pass through the concave portion and the convex portion of the mold. Lemelson teaches air is exhausted through tubes, which is formed to pass through the concave portion, among a plurality of tubes formed to pass through the concave portion and the convex portion of the mold (Lemelson Col. 11, Lines 55-64, wherein a pump is used to exhaust air through passageways in the mold). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimata and Lemelson to apply the known technique of introducing vibrations during the molding process as taught by Lemelson to improve on the molding process of Kimata, yielding the predictable results of improved material structure. Regarding Claim 8, Kimata does not explicitly teach wherein the air is exhausted through a filter provided in an opening of each of the tubes, which are formed to pass through the concave portion, to suppress or prevent leakage of the melted protective material. Lemelson teaches wherein the air is exhausted through a filter provided in an opening of each of the tubes, which are formed to pass through the concave portion, to suppress or prevent leakage of the melted protective material (Lemelson Col. 4, Lines 26-55, wherein plugs are used to prevent leakage of molding material). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimata and Lemelson to apply the known technique of introducing vibrations during the molding process as taught by Lemelson to improve on the molding process of Kimata, yielding the predictable results of improved material structure. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kimata as applied to claim 1 above, and further in view of Nomura et al., hereinafter Nomura, US Publication No. 2020/0388509. Regarding Claim 14, Kimata does not explicitly teach wherein the protective layer has a thickness of 5 μm to 1 mm. Nomura teaches wherein the protective layer has a thickness of 5 μm to 1 mm (Nomura paragraph [0104], wherein the thickness of the sealing sheet is less than 1 mm). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimata and Nomura to apply the known technique of thin sheets during the molding process as taught by Nomura to improve on the protective coating of Kimata, yielding the predictable results of improved molding material coverage and conformity to circuit elements, thereby increasing the effectiveness of the protective layer. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kimata as applied to claim 1 above, and further in view of Wilson et al., hereinafter Wilson, US Publication No. 2019/0081362. Regarding Claim 16, Kimata further teaches an electric vehicle comprising a battery that provides electric energy (Kimata paragraph [0039], see battery), a controller that controls a state of the electric vehicle (Kimata paragraphs [0039]-[0042], see electronic control unit), and a motor that drives the electric vehicle (Kimata paragraph [0021], see electric motors), wherein the controller is a second component of a second circuit board assembly (Kimata paragraphs [0035]-[0037], wherein the electronic control unit is on a printed wiring board), and wherein the first circuit board assembly and the second circuit board assembly are manufactured by the method of claim 1 (Kimata paragraphs [0035]-[0037], wherein the electronic control unit manufactured with a coating). Kimata does not explicitly teach a BMS that manages the battery, wherein the BMS is a first component of a first circuit board assembly. Wilson teaches a BMS that manages the battery (Wilson paragraph [0001], wherein a battery management system is used to manage a battery), wherein the BMS is a first component of a first circuit board assembly (Wilson paragraphs [0001], [0004] and [0022], wherein the battery management circuitry is on a printed circuit board that is covered and protected by an injection molded resin). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kimata and Wilson because the combination would allow the battery as taught by Kimata to be managed by the battery management system as taught by Wilson, yielding the predictable results of improved battery performance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC D LEE whose telephone number is (571)270-7098. The examiner can normally be reached Monday-Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC D LEE/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Aug 18, 2022
Application Filed
Jan 08, 2026
Non-Final Rejection — §102, §103
Apr 16, 2026
Examiner Interview Summary
Apr 16, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+19.3%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 644 resolved cases by this examiner. Grant probability derived from career allow rate.

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