DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 08/25/2022. Claims 1-8 are currently pending, of which claims 1-8 are currently rejected.
Claim Objections
Claims 1 and 6 are objected to because of the following informalities:
“includes a plurality of radix-n butterfly computation processing unit (where n is a multiple of 2) a number of which is equal to or more than a number of the plurality of sets,” when it should read “includes a plurality of radix-n butterfly computation processing units (where n is a multiple of 2), a number of which is equal to or more than a number of the plurality of sets,”
“first order from the plurality of radix-n butterfly computation processing unit.” When it should read “first order from the plurality of radix-n butterfly computation processing units.”
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the fast Fourier transform device comprising a “ twiddle multiplication processing unit” and a “second butterfly computation processing unit” recited in claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim #
Generic placeholder plus functional language:
Interpretation:
1
First transform unit that generates a plurality of sets of a plurality of pieces of first output data by performing a fast Fourier transform or an inverse fast Fourier transform
Interpreted to include First Butterfly Computation Processing Unit as disclosed in Fig. 21 and paragraph 0151 of the specification.
1
first butterfly computation processing unit that performs butterfly computation processing and outputting the plurality of sets of a plurality of pieces of first output data in the first order
Interpreted to be coupled to a first data processing unit and a second data processing unit and to include a plurality of radix-n butterfly computation processing units that process radix-n butterfly operations in parallel as disclosed in Figs. 1, 9, 19, and 21, and in paragraphs 0025, 0042, and 0079.
1
first data sorting processing unit that, based on an output order setting, rearranges, in a second order, the plurality of sets of a plurality of pieces of first output data output in a first order
Interpreted as the second data sorting processing unit of Figs. 1, 9, and 19, and ¶0005, 0031, and 0048-0058, coupled to the first butterfly computation processing unit, the read address generation unit, and the twiddle multiplication processing unit, and to include an array of storage locations to store data in a sequential order and a reading circuit, as disclosed in fig. 8 and ¶0031, 0061, and 0078.
5
a twiddle multiplication processing unit that performs twiddle multiplication processing on the plurality of sets of a plurality of pieces of first output data output in the first order
Interpreted to be coupled to the second data sorting processing unit and to the second butterfly computation processing unit as disclosed in Figs. 1, 9, and 19, and ¶0031, 0051, 0077, 0084.
5
a second butterfly computation processing unit that performs butterfly computation processing on data from the twiddle multiplication processing unit and outputs the resulting data.
Interpreted to be coupled to the twiddle multiplication processing unit as shown in Figs. 1, 9, and 19, and to include a plurality of radix-n butterfly computation processing units that process radix-n butterfly operations in parallel as disclosed in Figs. 1, 9, and 19, and ¶0052, 0065, 0077, and 0085.
7
a complex conjugate generation unit that generates second complex data including a conjugate complex number for every complex number
Interpreted to be included in digital
filter circuit and coupled to the FFT and filters as shown in Fig. 13, and to include a multiplier and to receive and output two signals as disclosed in Fig. 14 and ¶0105 and 0116.
7
a filter coefficient generation unit that generates first and second frequency-domain filter coefficients being complex numbers from input first, second, and third input filter coefficients being complex numbers
Interpreted to be included in the digital filter circuit and coupled to the filters as down in Fig. 13, and to include a plurality of multipliers and adders to produce two complex signals as shown in Fig. 18 and ¶0109.
7
a first filter unit that performs filter processing on the first complex data with the first frequency-domain filter coefficient and outputting third complex data
Interpreted to be included in the digital filter circuit and coupled to the complex conjugate generation circuit, the filter coefficient generation circuit, and the complex conjugate synthesis circuit as shown in Fig. 13, and to include a plurality of multipliers and adders as shown in Fig. 15 and described in ¶0118.
7
a second filter unit that performs filter processing on the second complex data with the second frequency-domain filter coefficient and outputting fourth complex data
Interpreted to be included in the digital filter circuit and coupled to the complex conjugate generation circuit, the filter coefficient generation circuit, and the complex conjugate synthesis circuit as shown in Fig. 13, and to include a plurality of multipliers and adders as shown in Fig. 16 and described in ¶0119.
7
a complex conjugate synthesis unit that generates fifth complex data by synthesis from the third complex data and the fourth complex data
Interpreted to be included in the digital filter circuit and coupled to first and second filters, and to the IFFT as shown in Fig. 13, and to include two pairs of adder and multiplier connected sequentially as shown in Fig. 17 and described in ¶0122.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “First transform unit”. Claims 2-7 recite the same limitation by reason of dependence. This limitation invokes 35 U.S.C. 112 (f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to provide adequate written description of the corresponding structure, material, or acts for performing the entire claimed functions of this limitation. See rejection under 35 U.S.C. 112 (b) below for further details as to the requirement for the written description.
Claims 2-7 inherit the same deficiency as claim 1 by reason of dependence.
Claim 5 recites the limitation “twiddle multiplication processing unit”. Claim 6 recites the same limitation by reason of dependence. This limitation invokes 35 U.S.C. 112 (f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to provide adequate written description of the corresponding structure, material, or acts for performing the entire claimed functions of this limitation. See rejection under 35 U.S.C. 112 (b) below for further details as to the requirement for the written description.
Claim 6 inherits the same deficiency as claim 5 by reason of dependence.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a plurality of pieces” in line 9 of claim 1. It is unclear if applicant intends the plurality of pieces to be the plurality of pieces mentioned above. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-7 inherit the same deficiency as claim 1 by reason of dependence.
Claim limitations “First transform unit” and “twiddle multiplication processing unit” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
As to the “First transform unit”, this unit is shown in Fig. 21 including the First Butterfly Computation Processing Means. However, there is no indication that there is any other structure in this unit other than the First Butterfly Computation Processing Means, and ¶0031 describes the first butterfly computation processing unit 21 as an example of a first transform means. There is no other form of structure or algorithm to perform the functional limitation. For reason of prior art rejection, the “First transform unit” will be interpreted as the “first butterfly computation processing unit”
As to the “twiddle multiplication processing unit”, this unit is merely described in ¶0051, 0077, and 0084. These descriptions merely mention the unit and describe the function performed by the unit, and no algorithm or structure could be found in the specification.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over SHIBAYAMA et al (U.S. Patent Application Publication No.: US 20150363360 A1), cited in IDS on 11/22/2022, hereinafter “SHIBAYAMA”, in view of Davey et al. (U.S. Patent Application Publication No.: US 20040034677 A1), hereinafter “Davey”.
Regarding Claim 1, SHIBAYAMA teaches:
A fast Fourier transform device comprising:
a first transform unit that generates a plurality of sets of a plurality of pieces of first output data by performing a fast Fourier transform or an inverse fast Fourier transform and outputting the generated data in a first order (Fig. 1, e.g., shows first butterfly computation processing unit 21 (first transform unit including first butterfly computation processing unit); ¶0049, e.g., FFT device 10 performs a fast fourier transform; ¶0140, e.g., Fig. 2 shows output of first butterfly computation processing unit 21; ¶0084),
the first transform unit including first butterfly computation processing unit that performs butterfly computation processing and outputting the plurality of sets of a plurality of pieces of first output data in the first order (Fig. 1, e.g., shows first butterfly computation processing unit 21 (first transform unit including first butterfly computation processing unit); ¶0054; ¶0065, e.g., first butterfly computation processing unit 21 outputs data y(n) (plurality of sets of a plurality of pieces of first output data in the first order); ¶0140, e.g., Fig. 2 shows output of first butterfly computation processing unit 21; Fig. 2, e.g., shows datasets of pieces of data); and
a first data sorting processing unit that, based on an output order setting, rearranges, in a second order, the plurality of sets of a plurality of pieces of first output data output in a first order from the first butterfly computation processing unit in the first transform unit (Fig. 1, e.g., second data sorting processing unit 12 (first data sorting processing unit) receives data y(n) from First Butterfly Computation Processing unit 21 (in a first order) and outputs; ¶0066, e.g., second data sorting processing unit 12 rearranges the data outputted from first butterfly computation processing unit 21; Fig. 6, e.g., shows array of storage locations and reading circuit 205; ¶0141), wherein the first butterfly computation processing unit includes a plurality of radix- n butterfly computation processing unit (where n is a multiple of 2) a number of which is equal to or more than a number of the plurality of sets, and the plurality of sets of a plurality of pieces of first output data are output in the first order from the plurality of radix-n butterfly computation processing unit (Fig. 9, e.g., shows Radix-8 Butterfly Computation Processing units (plurality of radix- n butterfly computation processing unit) inside butterfly computation processes 502; ¶0065, e.g., first butterfly computation processing unit 21 outputs the results of the butterfly computation in the sequential order shown in FIG. 2; Fig. 2, e.g., shows pieces of data ps for every dataset P).
SHIBAYAMA does not teach the first butterfly computation processing unit performing radix-8 butterfly computations in parallel as disclosed in ¶0042 of the specification. However, in the same field of endeavor, Davey discloses performing butterfly computations in parallel using a processing engine that comprises a pair of butterfly elements. Davey explains “The two butterflies of the processor 30A operate in parallel which means that the 53,248 (N/2 log.sub.2N) butterfly calculations required for the 8192-point FFT can be performed in 26,624 clock cycles, plus some latency.” (Davey: ¶0055)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the parallel processing of butterfly elements as taught by Davey with the first butterfly computation processing unit including the radix-8 butterfly computation processing units as taught by SHIBAYAMA. One would have been motivated to combine these references because both references disclose butterfly operations performed in fast fourier transform, and Davey enhances the model of SHIBAYAMA by allowing for the radix-8 butterfly computation processing units to process in parallel and “in 26,624 clock cycles, plus some latency.” (Davey: ¶0055)
Regarding Claim 2, SHIBAYAMA in view of Davey teach:
The fast Fourier transform device according to claim 1, wherein, when the plurality of pieces of first output data are denoted by X(k) (where k is an integer satisfying 0 k N-1 and N is a number of one or more points in a fast Fourier transform or an inverse Fourier transform and satisfies N > 0), the first data sorting processing unit outputs X(k) and X(N-k) in a same cycle for any k (SHIBAYAMA: Fig. 19, e.g., outputs of Radix-8 Butterfly Computation Processing Units are X(0-63) (X(k)) in parallel (same cycle); ¶0016, e.g., FFT outputs X(k) and X(N−k) at the same cycle).
Regarding Claim 3, SHIBAYAMA in view of Davey teach:
The fast Fourier transform device according to claim 1, wherein, when the plurality of pieces of first output data are denoted by X(k) (where k is an integer satisfying 0 k N-1 and N is a number of one or more points in a fast Fourier transform or an inverse Fourier transform and satisfies N > 0), the first data sorting processing unit outputs X(k) and X(N-k) with a time difference within one cycle for any k (SHIBAYAMA: ¶0015, e.g., X(k) and X(N-k) can be outputted in different cycles).
Regarding Claim 4, SHIBAYAMA in view of Davey teach:
The fast Fourier transform device according to claim1, wherein the first data sorting processing unit includes a first storage unit that stores the N pieces of second input data and a read address generation unit that generates read addresses of the N pieces of first output data from the first storage unit, based on an output order setting and stores the plurality of pieces of second input data in the first order and reads the plurality of pieces of second input data in the second order (Fig. 1, e.g., shows second data sorting processing unit 12 (first data sorting processing unit) receiving data from first butterfly computation processing unit 21 (N pieces of second input data); Fig. 9, e.g., read address generation unit 43 inputs addresses to second data sorting processing unit 16; ¶0078, e.g., reading circuit 205 selects data based on addresses; Fig. 6, e.g., shows second data sorting processing unit 16 implementation; ¶0072, e.g., read address generation unit 41 refers to output order setting 52 for outputting data (in a second order)).
Regarding Claim 5, SHIBAYAMA in view of Davey teach:
The fast Fourier transform device according to claim 1, further comprising:
a twiddle multiplication processing unit that performs twiddle multiplication processing on the plurality of sets of a plurality of pieces of first output data output in the first order from the first data sorting processing unit (SHIBAYAMA: Fig. 1, e.g., Twiddle multiplication processing unit 31 receives data from second data sorting processing unit 12; ¶0067, e.g., Twiddle multiplication processing unit 31 performs twiddle multiplication);
and a second butterfly computation processing unit that performs butterfly computation processing on data from the twiddle multiplication processing unit and outputs the resulting data (SHIBAYAMA: Fig. 1, e.g., shows second butterfly computation processing unit 22 receiving data from Twiddle multiplication processing unit 31).
Regarding Claim 6, SHIBAYAMA in view of Davey teach:
The fast Fourier transform device according to claim 5, wherein the second butterfly computation processing unit includes a plurality of radix-n butterfly computation processing unit (where n is a multiple of 2) a number of which is equal to or more than a number of the plurality of sets, and the plurality of sets of a plurality of pieces of first output data are output in the first order from the plurality of radix-n butterfly computation processing unit (SHIBAYAMA: Fig. 19, e.g., Radix-8 Butterfly Computation Processing Units 503 output data (in the first order); ¶0068).
Regarding Claim 7, SHIBAYAMA in view of Davey teach:
A digital filter device comprising (SHIBAYAMA: Fig. 13):
the fast Fourier transform device according to claim1;
a complex conjugate generation unit that generates second complex data including a conjugate complex number for every complex number constituting a plurality of pieces of frequency-domain first complex data generated by the fast Fourier transform device by Fourier-transforming the plurality of pieces of first input data being input time-domain complex numbers (SHIBAYAMA: Fig. 13, e.g., shows digital filter circuit 400 (digital filter device) including complex conjugate generation circuit 415 coupled to the FFT 413 and filters 421 and 422; ¶0167-0168, e.g., FFT circuit 413 outputs frequency-domain complex signal 431 (inputted complex conjugate generation circuit 415) based on time-domain complex signal x(n); ¶0172, e.g., complex conjugate generation circuit 415 outputs complex signals 432 and 433; ¶0254; Fig. 14, e.g., shows complex conjugate generation circuit 415 including a multiplier and two input and output signals);
a filter coefficient generation unit that generates first and second frequency-domain filter coefficients being complex numbers from input first, second, and third input filter coefficients being complex numbers (SHIBAYAMA: Fig. 13, e.g., shows filter coefficient generation circuit 441 coupled to the filters 421 and 422, and outputting signals 445 and 446 (first and second frequency-domain filter coefficients); ¶0174-0177, e.g., filter coefficient generation circuit 441 receives complex coefficients V(k), W(k), and H(k) to generate complex signals 445 and 446; ¶0255; Fig. 18, e.g., shows plurality of multipliers and adders in the same order as disclosed in Fig. 18 of instant application);
a first filter unit that performs filter processing on the first complex data with the first frequency-domain filter coefficient and outputting third complex data (SHIBAYAMA: Fig. 13, e.g., shows a filter circuit 421 coupled to the complex conjugate generation circuit 415, the filter coefficient generation circuit 441, and the complex conjugate synthesis circuit 416; ¶0176, e.g., filter circuit 421 performs complex filtering processes through a complex multiplication complex data signal 434; ¶0256; Fig. 15, e.g., shows plurality of multipliers and adders in the same order as disclosed in Fig. 15 of instant application);
a second filter unit that performs filter processing on the second complex data with the second frequency-domain filter coefficient and outputting fourth complex data (SHIBAYAMA: Fig. 13, e.g., shows a filter circuit 422 coupled to the complex conjugate generation circuit 415, the filter coefficient generation circuit 441; ¶0177-0182, e.g., filter circuit 422 performs complex filtering processes through a complex multiplication to output complex data signal 435; ¶0257; Fig. 16, e.g., shows plurality of multipliers and adders in the same order as disclosed in Fig. 16 of instant application); and
a complex conjugate synthesis unit that generates fifth complex data by synthesis from the third complex data and the fourth complex data (SHIBAYAMA: Fig. 13, e.g., complex conjugate synthesis circuit 416 coupled to first and second filters 421 and 422, and to the IFFT 414; ¶0179, e.g., complex conjugate synthesis circuit 416 generates a complex signal by synthesizing signals 434 and 435 from filters 421 and 422; ¶0258; Fig. 17, e.g., shows plurality of multipliers and adders in the same order as disclosed in Fig. 17 of instant application).
Regarding Claim 8, it is a method claim practiced by the apparatus of claim 1. It is rejected for the same reasons as claim 1.
Prior Art Made of Record
US 20150301986 A1 – teaches an FFT circuit that includes first, second, and third data-sorting processing circuits 11, 13, and 16, first and second butterfly calculation processing circuits 12 and 15, a first data selection circuit 21 and a second data selection circuit 22, and a twiddle multiplication processing circuit 14. See Fig. 1 and ¶0124-0139.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182