DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 08/14/2026 have been fully considered but they are not persuasive.
Applicant contends that “the Office has not proffered a proper reason for” the combination of Kim in view of Yamashita (pg. 6). To support this argument, applicant has modified Fig. 10A of Kim to extend the protrusion 32b to the mounting surface. Applicant contends “the Office has not explained why one skilled in the art would extend 32b when the main frame 32a already has a significantly larger surface that is for heat dissipation”. Applicant’s amended figure of Kim entirely ignores the teachings of Yamashita. For instance, Fig. 4, which applicant supplies in the response, clearly shows a larger portion 43a and a smaller portion of the 42a of the equivalent “main frame”. Furthermore, Yamashita provides explicit reasoning as to why Kim’s “protrusions” would be provided at both the side (Kim 31c; Yamashita 42s) and the mounting surface (Yamashita 42a). Yamashita explains that the second exposed portion allows heat to be effectively dispersed from both exposed surfaces ([0169]) and that it allows easy electrical connection with a copper foil without the need to use the larger exposed area to conduct electricity ([0090]-[0091]). Accordingly, a proper analysis of the references clearly discloses and explains why a person of ordinary skill in the art would modify Kim with the first inner region and the first edge region is exposed on the mounting side of the housing as disclosed by Yamashita in the specific configuration as claimed by applicant.
All rejections are maintained.
Priority
This application is a national stage entry of PCT/EP2021/055581 filed on 03/05/2021 and further claims priority to DE102020107409.3 filed on 03/18/2020.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Interpretation
“The lead frame is exposed solely at a first connection point of the first lead frame part and at a second connection point of the second lead frame part of the lead frame in the cavity” is being interpreted the same as in previous actions.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 4-6, 10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR20180041489), hereafter Kim, in view of Yamashita et al. (US20120120671A1), hereafter Yamashita.
Regarding claim 1, Kim discloses a housing for an optoelectronic semiconductor component (Title; Fig. 1) with a mounting side (Fig. 6 element 1 on element 2), a lead frame (Fig. 2b elements 31 and 32), and a housing body which is integrally moulded onto the lead frame (Fig. 2a element 1; [0036]), wherein - the lead frame comprises a first lead frame part (Fig. 2a element 31) and a second lead frame part (Fig. 2a element 32); - the housing body comprises a cavity on a front side facing away from the mounting side for accommodating an optoelectronic semiconductor chip (Fig. 2a element 11); - the lead frame is exposed solely at a first connection point of the first lead frame part (Fig. 2a element 31 is only exposed at 31d) and at a second connection point of the second lead frame part of the lead frame in the cavity (Fig. 2a element 32 is only exposed at element 32d);- the first lead frame part has a first inner region (Fig. 2a element 31a) and a first edge region (Fig. 1 element 31C; Fig. 2a element 31b);- the first inner region is exposed on the mounting side of the housing (Fig. 2a element 31a);- the first inner region in plan view of the housing overlaps with the first connection point (Fig. 2a element 31a overlaps element 31d);- the first edge region is exposed on a first side face of the housing (Fig. 1 element 31c); and- the first inner region and the first edge region are connected to one another via a front- side region of the first lead frame part (Fig. 2a element 31a is connected to element 31b by element 31f), wherein the front-side region is distanced from the mounting side (Fig. 2a element 31b), wherein the first connection point and the second connection point are configured to bond to the optoelectronic semiconductor chip via connecting means without bonding wires (Fig. 2a elements 41 and 42). Kim does not explicitly disclose the first edge region is exposed on the mounting side of the housing. However, Yamashita disclose the first inner region and the first edge region is exposed on the mounting side of the housing (Fig. 4 element 43A and 42A). An advantage is to allow heat transfer from the optoelectronic component while allowing easy electrical connections to the component ([0090]-[0091], [0169]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kim with the first edge region is exposed on the mounting side of the housing as disclosed by Yamashita in order to allow heat transfer from the optoelectronic component while allowing easy electrical connections to the component.
Regarding claim 2, Kim further discloses a bottom face of the cavity in a region of the first connection point and the second connection point has an indentation (Fig. 2a element 14), in which the first connection point and the second connection point are exposed (Fig. 2a elements 31d and 32d in element 14).
Regarding claim 4, Yamashita further discloses the first edge region has a recess which is accessible on the mounting side and on a side face of the housing (Fig. 4 element 42S).
Regarding claim 5, Yamashita further discloses the first front-side region in plan view of the housing runs along two edges of the first inner region (Fig. 4 element 41 extends along two edges of element 43).
Regarding claim 6, Yamashita further discloses the first lead frame part between the first inner region and the first edge region in plan view of the housing is interrupted along a longitudinal axis of the housing (Fig. 3 element 41 has a cutout between 42 and 43).
Regarding claim 10, Kim in view of Yamashita do not explicitly disclose an area dimension of the first connection point and an area dimension of the second connection point is in each case at most 30% of an area dimension of a bottom face of the cavity. However, Kim discloses optimizing the area of the cavity and the area of the connection points in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder ([0041]-[0046]; [0061]-[0062]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kim in view of Yamashita with an area dimension of the first connection point and an area dimension of the second connection point is in each case at most 30% of an area dimension of a bottom face of the cavity, since Kim discloses optimizing the area of the cavity and the area of the connection points in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 12, Kim further disclose the optoelectronic semiconductor chip which is arranged in the cavity (Fig. 1 element 100) and electrically conductively connected to the first connection point and the second connection point (Fig. 2a element 100 is connected via elements 41 and 42).
Regarding claim 13, Kim further discloses the optoelectronic semiconductor chip covers the first connection point and the second connection point fully (Fig. 1 and 2A element 100 completely covers elements 31d and 32d).
Regarding claim 14, Kim, for the same reasons discussed in claim 13, further discloses the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip (Fig. 3 elements 41 and 42 are shown to be less than half the semiconductor chip; See also [0061]-[0062] indicating that the connection point should be at 1.1 to 2 times the size of the electrode and Fig. 3 shows each electrode is less than half the size of the optoelectronic semiconductor chip). Alternatively, if it is found that Kim does not sufficiently disclose the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip, Kim discloses optimizing the size of the connection points relative to the size of the electrodes of the optoelectronic semiconductor chip ([0061]-[0062]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Kim in view of Yamashita with the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip, since Kim discloses optimizing the size of the connection points relative to the size of the electrodes of the optoelectronic semiconductor chip and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 15, Kim, for the same reasons discussed in claim 13, further discloses the optoelectronic semiconductor chip is embedded in a potting compound, wherein the potting compound does not at any point directly border the lead frame (Fig. 1 and 2a element 17).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yamashita , as applied to claim 1, in further view of Ichihara et al. (US20170222110A1), hereafter Ichihara.
Regarding claim 7, Kim in view of Yamashita does not explicitly disclose the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis. However, Ichihara discloses the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis (See annotated Fig. 4A below). An advantage is to allow for the electrical connection in the desired location on the edge of the device ([0055]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Kim in view of Yamashita with the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis as disclosed by Ichihara in order to allow for the electrical connection in the desired location on the edge of the device and since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
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Regarding claim 8, Kim in view of Yamashita does not explicitly disclose the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing. However, Ichihara discloses the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing (See annotated Fig. 4A below). An advantage is to reduce cracking and splitting of the resin molding ([0010]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Kim in view of Yamashita with the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing as disclosed by Ichihara in order to reduce cracking and splitting of the resin molding.
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Regarding claim 9, Kim in view of Yamashita in further view of Ichihara do not explicitly disclose the first extension, seen along the longitudinal axis, runs along at least 50% of an extent of the second connection point. However, Ichihara discloses defining suspension pins to extend to the edge of the housing in order to reduce cracking and splitting of the resin molding ([0009]-[0010]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Kim in view of Yamashita in further view of Ichihara with the first extension, seen along the longitudinal axis, runs along at least 50% of an extent of the second connection point, since Ichihara discloses optimizing the length of the suspension pins in order to reduce cracking and splitting of the resin molding and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yamashita, as applied to claim 1, in further view of Kim (KR20190074200A)1, hereafter Kim 2.
Regarding claim 11, Kim in view of Yamashita does not explicitly disclose wherein the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape. However, Kim 2 discloses wherein the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape (Fig. 2 elements 110, 114, 120, and 124). An advantage is to prevent defective electrical contact (Abstract). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Kim in view of Yamashita with the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape as disclosed by Kim 2 in order to prevent defective electrical contact.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attached Notice of References Cited.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA KING whose telephone number is (571)270-1441. The examiner can normally be reached Monday to Friday 10am-5pm MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Min Sun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Joshua King/Primary Examiner, Art Unit 2828 09/30/2026
1 Cite No. 1 in the IDS filed 10/12/2023
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