DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 01/14/2026 have been fully considered but they are not persuasive.
On pages 5-6, applicant contends the rejection is improper because the Office has ignored the word “solely”. The Office did not ignore the word “solely” and provided a complete explanation of how the word was being interpreted on pages 2-4 of the previous action. Merriam webster defines “solely” as “without another”. This definition supports the Office’s interpretation of the claim, which is explained again below. The Office also notes that applicant has not suggested any alternative interpretation.
On page 6, applicant asks “how would the Office interpret this feature” is the claim did not include the word solely. As noted in the previous rejection, art such as Fig. 4 and 5 below would also read on applicant’s theoretical claim, because the frame isn’t exposed “solely” at the first connection point and the second connection point. That is, Figs. 4 and 5 below do now show first and second connection points “without another”. Figs. 4 and 5 show multiple connection points in addition to the first and second connection point.
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Accordingly, the Office has properly considered all the words of claim 1 and has provided art that reads on the scope of claim 1. Accordingly, the rejection is proper.
On pages 7-8, applicant further contends the rejection of claim 2 and 4-15 are improper. Applicant accuses the Office of combining the references using mere conclusory statements. However, the Office has provided a detailed explanation for the rejection of each claim. For example, the rejection of claim 2 recites “An advantage is to prevent misalignment during mounting ([0044])” and the rejection of claim 10 recites “optimizing the area of the cavity and the area of the connection points in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder ([0041]-[0046]; [0061]-[0062])”. These are not “conclusory statements” such as “well within the ordinary skill of the art”. Rather these are an articulated reasoning of the considerations a person of ordinary skill in the art would have that would lead them to arrive at the claimed invention.
On page 8, applicant attempts to distinguish Yamashita and Kim 2 for claims 10 and 13, because they connect the optoelectronic component to the lead frame in different ways. As was outlined in claims 2, 10 and 13, the alternative bonding method of Kim 2 has advantages that render the claims obvious to a person of ordinary skill in the art.
Accordingly, all rejections are maintained.
Priority
This application is a national stage entry of PCT/EP2021/055581 filed on 03/05/2021 and further claims priority to DE102020107409.3 filed on 03/18/2020.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/25/2022 and 10/12/2023 were filed on or after the national stage entry date of this application on 08/25/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
Claim 1 recites “the lead frame is exposed solely at a first connection point of the first lead frame part and at a second connection point of the second lead frame part of the lead frame in the cavity.” This language is being interpreted to only allow for two connection points of any size relative to the actual connection so long as that area is continuous.
For instance, this figure shows “the lead frame is exposed solely at a first connection point of the first lead frame part and at a second connection point of the second lead frame part of the lead frame in the cavity” because there are only two connection points that the lead frame is exposed in.
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While figures 4 and 5 do not show the lead frame is exposed solely at a first connection point of the first lead frame part and at a second connection point of the second lead frame part of the lead frame in the cavity” because there are more than two connection points where the lead frame is exposed.
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The Office notes that the dependent claims, e.g. claims 10 and 13, support this interpretation as the broadest reasonable interpretation of claim 1 based on the legal doctrine of claim differentiation, because claim 1 is silent regarding the sizes of the exposed connection points and claims 10 and 13 recites the sizes of the exposed connection points relative to other elements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al. (US20120120671A1), hereafter Yamashita.
Regarding claim 1, Yamashita discloses a housing for an optoelectronic semiconductor component (Title; Fig. 1) with a mounting side (Fig. 4), a lead frame (Fig. 1 elements 40 and 50), and a housing body which is integrally moulded onto the lead frame (Fig. 1 element 30; [0052]), wherein - the lead frame comprises a first lead frame part (Fig. 1 element 40) and a second lead frame part (Fig. 1 element 50); - the housing body comprises a cavity on a front side facing away from the mounting side for accommodating an optoelectronic semiconductor chip (Fig. 1 element 20F where element 10 is located); - the lead frame is exposed solely at a first connection point of the first lead frame part (Fig. 1 element 40 where element 10 is located) and at a second connection point of the second lead frame part of the lead frame in the cavity (Fig. 1 element 50);- the first lead frame part has a first inner region and a first edge region (Fig. 1 elements 42A and 43a);- the first inner region and the first edge region are exposed on the mounting side of the housing (Fig. 4);- the first inner region in plan view of the housing overlaps with the first connection point (Fig. 3 element 43 overlaps with element 10);- the first edge region is exposed on a first side face of the housing (Fig. 4 element 42A); and- the first inner region and the first edge region are connected to one another via a front- side region of the first lead frame part (Fig. 4 element 41), wherein the front-side region is distanced from the mounting side (Fig. 4 element 41; [0065]).
Regarding claim 4, Yamashita further discloses the first edge region has a recess which is accessible on the mounting side and on a side face of the housing (Fig. 4 element 42S).
Regarding claim 5, Yamashita further discloses the first front-side region in plan view of the housing runs along two edges of the first inner region (Fig. 4 element 41 extends along two edges of element 43).
Regarding claim 6, Yamashita further discloses the first lead frame part between the first inner region and the first edge region in plan view of the housing is interrupted along a longitudinal axis of the housing (Fig. 3 element 41 has a cutout between 42 and 43).
Regarding claim 12, Yamashita further disclose the optoelectronic semiconductor chip which is arranged in the cavity (Fig. 1 element 10) and electrically conductively connected to the first connection point and the second connection point (Fig. 1 element 10 is connected via wirebonds 11 and 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 10, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Kim et al. (KR20180041489), hereafter Kim.
Regarding claim 2, Yamashita does not explicitly disclose a bottom face of the cavity in a region of the first connection point and the second connection point has an indentation, in which the first connection point and the second connection point are exposed. However, Kim discloses a bottom face of the cavity in a region of the first connection point and the second connection point has an indentation (Fig. 2a element 14), in which the first connection point and the second connection point are exposed (Fig. 2a elements 31d and 32d in element 14). An advantage is to prevent misalignment during mounting ([0044]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with a bottom face of the cavity in a region of the first connection point and the second connection point has an indentation, in which the first connection point and the second connection point are exposed as disclosed by Kim in order to prevent misalignment during mounting.
Regarding claim 10, Yamashita does not explicitly disclose an area dimension of the first connection point and an area dimension of the second connection point is in each case at most 30% of an area dimension of a bottom face of the cavity. However, Kim discloses optimizing the area of the cavity and the area of the connection points in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder ([0041]-[0046]; [0061]-[0062]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with an area dimension of the first connection point and an area dimension of the second connection point is in each case at most 30% of an area dimension of a bottom face of the cavity, since Kim discloses optimizing the area of the cavity and the area of the connection points in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 13, Kim further discloses the optoelectronic semiconductor chip covers the first connection point and the second connection point fully (Fig. 1 and 2A element 100 completely covers elements 31d and 32d). An advantage is to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder ([0041]-[0046]; [0061]-[0062]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with the optoelectronic semiconductor chip covers the first connection point and the second connection point fully as disclosed by Kim in order to balance the difficulty in mounting the LED and the prevention of spreading solder or using too much solder.
Regarding claim 14, Kim, for the same reasons discussed in claim 13, further discloses the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip (Fig. 3 elements 41 and 42 are shown to be less than half the semiconductor chip; See also [0061]-[0062] indicating that the connection point should be at 1.1 to 2 times the size of the electrode and Fig. 3 shows each electrode is less than half the size of the optoelectronic semiconductor chip). Alternatively, if it is found that Kim does not sufficiently disclose the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip, Kim discloses optimizing the size of the connection points relative to the size of the electrodes of the optoelectronic semiconductor chip ([0061]-[0062]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Yamashita in view of Kim with the first connection point and the second connection point in plan view of the optoelectronic semiconductor component are each at most half of a size of the optoelectronic semiconductor chip, since Kim discloses optimizing the size of the connection points relative to the size of the electrodes of the optoelectronic semiconductor chip and it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 15, Kim, for the same reasons discussed in claim 13, further discloses the optoelectronic semiconductor chip is embedded in a potting compound, wherein the potting compound does not at any point directly border the lead frame (Fig. 1 and 2a element 17).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Ichihara et al. (US20170222110A1), hereafter Ichihara.
Regarding claim 7, Yamashita does not explicitly disclose the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis. However, Ichihara discloses the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis (See annotated Fig. 4A below). An advantage is to allow for the electrical connection in the desired location on the edge of the device ([0055]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with the first inner region and the first edge region in plan view of the housing, seen along a longitudinal axis of the housing, are connected to one another via the first front-side region only on one side of the longitudinal axis as disclosed by Ichihara in order to allow for the electrical connection in the desired location on the edge of the device and since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
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Regarding claim 8, Yamashita does not explicitly disclose the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing. However, Ichihara discloses the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing (See annotated Fig. 4A below). An advantage is to reduce cracking and splitting of the resin molding ([0010]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with the first front-side region of the first lead frame part has a first extension, which extends between the second connection point and a second side face of the housing, said second side face running parallel to a longitudinal axis of the housing as disclosed by Ichihara in order to reduce cracking and splitting of the resin molding.
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Regarding claim 9, Yamashita in view of Ichihara do not explicitly disclose the first extension, seen along the longitudinal axis, runs along at least 50% of an extent of the second connection point. However, Ichihara discloses defining suspension pins to extend to the edge of the housing in order to reduce cracking and splitting of the resin molding ([0009]-[0010]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to further modify Yamashita in view of Ichihara with the first extension, seen along the longitudinal axis, runs along at least 50% of an extent of the second connection point, since Ichihara discloses optimizing the length of the suspension pins in order to reduce cracking and splitting of the resin molding and since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Kim (KR20190074200A)1, hereafter Kim 2.
Regarding claim 11, Yamashita does not explicitly disclose wherein the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape. However, Kim 2 discloses wherein the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape (Fig. 2 elements 110, 114, 120, and 124). An advantage is to prevent defective electrical contact (Abstract). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamashita with the second lead frame part and the first lead frame part are point-symmetrical to one another in respect of their basic shape as disclosed by Kim 2 in order to prevent defective electrical contact.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attached Notice of References Cited.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA KING whose telephone number is (571)270-1441. The examiner can normally be reached Monday to Friday 10am-5pm MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Min Sun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Joshua King/Primary Examiner, Art Unit 2828 04/02/2026
1 Cite No. 1 in the IDS filed 10/12/2023