DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Examiner acknowledges the amendments made to claims 1-4 and 7. New claims 8-10 have been added.
Response to Arguments
Applicant's arguments filed 01/29/2026 have been fully considered but they are respectfully found not persuasive.
Regarding the remarks made that the combination of Kitamura and Shimizu does not teach, suggest, or render obvious at least the features of “a first conductivity-type semiconductor layer in contact with the first conductivity-type contact layer at the bottom portion of the mesa part, wherein the first conductivity-type contact layer is between the first conductivity-type semiconductor layer and the mesa part” as recited in amended independent claim 1, Examiner respectfully finds the argument non-persuasive.
Specifically, Applicant argues that Shimizu fails to teach that the p-type contact layer [12] and the p-type spacer layer [11] are at the bottom portion of the mesa post [M] and therefore a person of ordinary skill would be discouraged from following the claimed structure.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Examiner notes that the contact layer [21] of Kitamura is disclosed as having a p-type conductivity (Kitamura Para. [0050]) and is shown to be at the bottom of a mesa portion [2A] as shown in Fig. 1 of Kitamura. Shimizu discloses that the contact layer [12] and the spacer layer [11] are both p-type conductivity layers. Therefore, when the p-type spacer layer [11] of Shimizu (first conductivity-type semiconductor layer) is implemented under the p-type contact layer [21] of Kitamura (first conductivity-type contact layer) in the same manner as shown in Shimizu, the combination of Kitamura and Shimizu with meet the limitation of:
“a first conductivity-type semiconductor layer [Shimizu 11 Fig. 1] (Shimizu Para. [0039]) in contact with the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Kitamura Para. [0050]) at the bottom portion of the mesa part [Kitamura 2A Fig. 1], wherein the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Kitamura Para. [0050]) is between the first conductivity-type semiconductor layer [Shimizu 11 Fig. 1] (Shimizu Para. [0039]) and the mesa part [Kitamura 2A Fig. 1]”
It is further noted that one of ordinary skill in the art would not be discouraged from implementing the p-type spacer layer [11] of Shimizu directly under the p-type contact layer [21] of Kitamura due to the shared conductivity type of a p-type. If the spacer layer of Shimizu was implemented at the top of the mesa portion of Kitamura the p-type spacer layer of Shimizu would be implemented under an n-type contact layer.
The reference of Shimizu is not relied upon for the positioning of the respective contact and semiconductor layers in relation to the mesa part, but is relied upon for the p-type spacer layer (first conductivity-type semiconductor layer) and doping relationships of the contact layer and the spacer layer as shown in Shimizu.
Further, the paragraphs at the end of page 5 and beginning of page 6 of the remarks filed 01/29/2026 argues that a person skilled in the part would be discouraged from adopting the claimed combination due to the respective electrode structures of Kitamura and Shimizu. The Applicant is arguing against a combination which has not been made or relied upon in the previous rejection. Specifically, the remarks state on pages 5 and 6, “Shimizu, in contrast, reaches non-coplanar electrode placement along with the placement of the p-type spacer layer 11 and the p-type conduct layer in the mesa post M …, which would be rendered unsatisfactory if modified to meet the claimed limitations.”
This argument is based upon modifying the Shimizu mesa portion and electrode structure of Shimizu to meet the claimed limitation where the rejection is based on the primary reference of Kitamura being modified with the secondary reference of Shimizu in relation to the p-type spacer layer and p-type doping concentrations.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Lines 1 and 2 of claim 8 recites “further comprising a second conductivity-type semiconductor substrate at a position opposed to the mesa part”. Paragraph [0010] of the specification discloses the relationship of the term “second conductivity-type” equating to an n-type doping. The specification only discloses the use of a semi-insulating or p-type substrate as recited in paragraph [0014] of the specification of the claimed application. The claimed application does not disclose the use of an n-type substrate in the specification.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kitamura et al. (hereinafter Kitamura) (US 20020137245 A1) in view of Shimizu et al. (hereinafter Shimizu) (US 20110241564 A1).
Regarding claim 1, Kitamura discloses in Fig. 1
A surface emitting laser [100] (Para. [0048]) comprising:
a mesa part [2A] that includes a first conductivity-type distributed Bragg reflector (DBR) layer [22], an active layer [24], a second conductivity-type DBR layer [27], and a second conductivity-type contact layer [28] (Para. [0049]);
a first conductivity-type contact layer [21] (Para. [0050]) in a region on a side of the first conductivity-type DBR layer [22], wherein the first conductivity-type contact layer [21] (para. [0050]) is in a positional relationship with respect to the mesa part [2A] at a bottom portion of the mesa part [2A] [bottom of stack shown in 2A Fig. 1]; (Para. [0049])
a first electrode layer [4] in contact with the first conductivity-type contact layer [21] (Para. [0057]);
and a second electrode layer [5] in contact with the second conductivity-type contact layer [28] (Para. [0059]) at a top portion of the mesa part [top of stack shown in 2A Fig. 1].
Kitamura fails to disclose,
a first conductivity-type semiconductor layer in contact with the first conductivity-type contact layer at the bottom portion of the mesa part,
the first conductivity-type contact layer is between the first conductivity-type semiconductor layer and the mesa part, and
the first conductivity-type semiconductor layer has a lower impurity concentration than the first conductivity-type contact layer;
Shimizu discloses in Fig. 2,
a first conductivity-type semiconductor layer [11] (Paras [0038,0039]) under and in contact with a first conductivity-type contact layer [12] (Paras [0038,0039]) and
the first conductivity-type semiconductor layer [11] (Paras [0038,0039]) has a lower impurity concentration than the first conductivity-type contact layer [12] (Para. [0039])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the first conductivity type semiconductor layer of Shimizu below the contact layer of Kitamura with the impurity concentration relationships disclosed in Shimizu for the purpose of having more effective current injection. (Shimizu Para. [0039])
Examiner notes the semiconductor layer [11 Shimizu] is formed directly under and in contact with the contact layer [12 Shimizu] of Shimizu. Therefore, when implemented into the device of Kitamura in the same manner as shown in Shimizu, the semiconductor layer [11 Shimizu] of Shimizu is implemented directly under and in contact with the contact layer [21 Kitamura] of Kitamura, meeting the limitation of :
“a first conductivity-type semiconductor layer [Shimizu 11 Fig. 1] (Shimizu Para. [0039]) in contact with the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Kitamura Para. [0050]) at the bottom portion of the mesa part [Kitamura 2A Fig. 1], wherein the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Kitamura Para. [0050]) is between the first conductivity-type semiconductor layer [Shimizu 11 Fig. 1] (Shimizu Para. [0039]) and the mesa part [Kitamura 2A Fig. 1]”
Regarding claim 2, Kitamura in view of Shimizu as applied to claim 1 further discloses,
a semi-insulating semiconductor substrate [Kitamura 1, Fig. 1] (Para. [0048]) at a position opposed to the mesa part [Kitamura 2A Fig. 1], wherein
the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Para. [0049]) and the first conductivity-type semiconductor layer [Shimizu 11 Fig. 2] (Para. [0038]) is between the mesa part [Kitamura 2A Fig. 1] and the semi-insulating semiconductor substrate [Kitamura 1, Fig. 1], and
the first electrode layer [Kitamura 4 Fig. 1] is in contact with a surface, of the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Para. [0048]), on a side of the mesa part [Kitamura 2A Fig. 1].
Examiner notes that the positional relationship of the substrate layers, semiconductor layers, and electrode layers in the modified device of Kitamura in view of Shimizu will maintain the same positional relationship as the original device of Kitamura when the respective layers are implemented into the original device.
Regarding claim 3, Kitamura in view of Shimizu as applied to claim 2 above further discloses,
wherein the first conductivity- type semiconductor layer [Shimizu 11 Fig. 2] (Para. [0062]), the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Para. [0048]), the first conductivity- type DBR layer [Kitamura 22 Fig. 1] (Para. [0049]), the active layer [Kitamura 24 Fig. 1] (Para. [0049]), the second conductivity-type DBR layer [Kitamura 27 Fig. 1] (Para. [0049]), and the second conductivity-type contact layer [Kitamura 28 Fig. 1] are based on an epitaxial crystal growth method (Kitamura Para. [0076]), and the semi-insulating semiconductor substrate [Kitamura 1, Fig. 1] (Para. [0048]) is utilized as a crystal growth substrate (Kitamura Para. [0076]).
Regarding claim 7, Kitamura in view of Shimizu as applied to claim 1 above further discloses in Kitamura Fig. 1,
wherein a conductivity type of the first conductivity-type contact layer comprises a p type (Para. [0049,0050]), and
a conductivity type of the second conductivity-type contact layer comprises an n type (Para. [0049,0050]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Shimizu as applied to claim 2 above, and further in view of See et al. (hereinafter See) (US 20050230694 A1).
Regarding claim 4, Kitamura in view of Shimizu discloses the device outlined in the rejection of claim 2 above but fails to disclose,
an undoped semiconductor layer between the first conductivity-type semiconductor layer and the semi-insulating semiconductor substrate.
See discloses in Fig. 1,
An undoped buffer layer [3] (Paras. [0083-0085]) directly above a substrate [1] (Paras. [0083-0085])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the undoped buffer layer of See directly above the substrate of the modified device of Kitamura as shown in See for the purpose of mitigating lattice constant differences.
Claim 5 is rejected under 35 U.S.S. 103 as being unpatentable over Kitamura (US 20020137245 A1) in view of Shimizu (US 20110241564 A1) as applied to claim 1 above and further in view of Tsuji (US 20180331491 A1)
Regarding claim 5, Kitamura in view of Shimizu discloses the device outlined in the rejection of claim 1 above but fails to disclose,
Wherein the first conductivity-type semiconductor layer is thicker than the first conductivity-type contact layer
Tsuji discloses in Fig. 1,
a semiconductor layer [11] (Para. [0040]) that is thicker than a contact layer [12] (Para. [0041])
It would have been obvious to one of ordinary skill in the art before the effect filing date of the claimed invention to implement a contact layer structure that is thinner than an underlying semiconductor layer as shown in Tsuji with the contact layer of the modified device of Kitamura for the purpose of reducing the contact resistance of the contact layer. (Tsuji Para. [0072])
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kitamura (US 20020137245 A1) in view of Shimizu (US 20110241564 A1) as applied to claim 1 above, and further in view of Yeh (US 20030031218 A1).
Regarding claim 6, Kitamura in view of Shimizu discloses the device outlined in the rejection of claim 1 above, the modified device of Kitamura fails to disclose,
wherein the second conductivity-type DBR layer is configured to have a greater reflectance than the first conductivity-type DBR layer, with respect to an oscillation wavelength of a vertical resonator in the mesa part.
Yeh discloses in Fig. 2,
wherein the second conductivity-type DBR layer [215] (Para. [0041]) is configured to have a greater reflectance than the first conductivity-type DBR layer [212] (Para. [0041,0042]), with respect to an oscillation wavelength of a vertical resonator in the mesa part [210] (Para. [0041,0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the reflectivity of the mirrors of Yeh into the mirrors of the modified device of Kitamura in view of Shimizu for the purpose of achieving bottom emission of light. (Yeh Para. [0042])
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Shimizu as applied to claim 1 above, and further in view of Weichmann et al. (hereinafter Weichmann) (US 20200403376 A1).
Regarding claim 8, Kitamura in view of Shimizu as applied to claim 1 above further discloses,
further comprising a semiconductor substrate [Kitamura 1, Fig. 1] (Para. [0048]) at a position opposed to the mesa part [Kitamura 2A Fig. 1], wherein:
the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Para. [0049]) and the first conductivity-type semiconductor layer [Shimizu 11 Fig. 2] (Para. [0038]) is between the mesa part [Kitamura 2A Fig. 1] and the semiconductor substrate[Kitamura 1, Fig. 1],
the first electrode layer [Kitamura 4 Fig. 1] is in contact with a surface, of the first conductivity-type contact layer [Kitamura 21 Fig. 1] (Para. [0048]), on a side of the mesa part [Kitamura 2A Fig. 1], and
the semiconductor substrate [Kitamura 1, Fig. 1] is utilized as a crystal growth substrate (Kitamura Para. [0076]).
Kitamura in view of Shimizu fails to disclose,
the semiconductor substrate comprising a second conductivity-type semiconductor substrate
Weichmann discloses in Fig. 1,
a substrate of the second conductivity-type (n-type) (Para. [0081])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the n-type doping of the substrate described in Weichmann as the conductivity type of the substrate of the modified device of Kitamura for the purpose of using a substrate with reasonable cost and high quality. (Weichmann Para. [0081])
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Shimizu as applied to claim 1 above, and further in view of Sato (US 8325777 B2).
Regarding claim 9, Kitamura in view of Shimizu discloses the device outlined in the rejection of claim 1 above and further discloses in Kitamura Fig. 1,
further comprising a current constriction layer [26] (Para. [0054]),
wherein the current constriction layer [26] comprises a current injection region [middle of 26 in 2A] (Para. [0054]) and a current constriction region [26a] (Para. [0054]) formed in a surrounding region of the current injection region [middle of 26 in 2A] (Para. [0054]).
Kitamura in view of Shimizu fails to disclose,
the current constriction layer in the first conductivity-type DBR layer
Sato discloses in Fig. 1,
a current constriction layer [107] (Col. 13, line 66 – Col. 14, line 2) in a p-type DBR layer [106] (Col. 13, lines 59-65)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the current constriction layer of the modified device of Kitamura inside the p-type DBR layer as disclosed in Sato for the purpose of performing oscillation with low threshold current. (Sato Col. 14, lines 22-30)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kitamura in view of Shimizu as applied to claim 2 above, and further in view of Matsubara et al. (hereinafter Matsubara) (US 20160156157 A1).
Regarding claim 10, Kitamura in view of Shimizu discloses the device outlined in the rejection of claim 2 above but fails to disclose,
wherein the semi-insulating semiconductor substrate has a resistivity in a range of 1.0 x 106 ohms and 1.0 x 1012 ohms.
Matsubara discloses in Fig. 2,
a substrate [11] with a resistivity in a range of 1.0 x 106 ohms and 1.0 x 1012 ohms (Para. [0072])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the resistivity value of the substrate of Matsubara into the substrate of the modified device of Kitamura for the purpose of maintaining semi-insulating properties. (Matsubara Para. [0072])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828
/XINNING(Tom) NIU/ Primary Examiner, Art Unit 2828