DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 06/04/2026. Claims 1-23 are pending in the case. This action is Final.
Applicant Response
In Applicant’s response dated 06/04/2026, Applicant amended Claims 1, 9 and 17 and argued against all objections and rejections previously set forth in the Office Action dated 02/05/2026.
Claim Interpretation
4. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: module
decomposing, by a gate decomposition module …; providing, by an instruction generation module …; transforming, by a data processing module,” in claims 1, 9, and 17.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
As per Applicant’s specifications:
[0030], Gate decomposition module 213 (which may be implemented as a submodule of compilation module 211) can be configured to decompose the gate sequences determined by compilation module 211 into sequences of native gates that can be physically implemented on quantum component 220.
[0032] Quantum controller 215 can include an instruction generation module 216. The capabilities of instruction generation module 216 can depend on the particular implementation of quantum component 220.
[0034] In various embodiments, quantum controller 215 can include a data processing module 217. The capabilities of data processing module 217 can depend on the particular implementation of quantum component 220
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner Comments
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-23 are rejected under 35 U.S.C. 103 as being unpatentable over Castrillo (Pub. No. US 20220230087 B1, Pub. Date 2022-07-21 ) in view of Aaronson (NPL: Title: Improved simulation of stabilizer circuits (Received 25 June 2004; published 30 November 2004) in further view of Smith ( Pub. No. US 20180260245 A1, , Pub. Date 2018-09-13)
Castrillo teaches a method of benchmarking a quantum device (see Castrillo: Fig.1, [0041] illustrating system for benchmarking quantum computing hardware.”), comprising:
selecting a sequence of M quantum gates from a group of quantum gates according to a probability distribution (see Castrillo: Fig.1, [0050], “a random quantum circuit of depth d (M quantum gates), the random quantum circuit generator 110 is configured to randomly sample single qubit gates from a predefined set of single qubit gates, e.g., a set of single qubit gates that can be implemented by quantum hardware 120.”), the quantum gates in the group being capable of [… ] classical simulation (see Castrillo: Fig.1, [0072], “The action of a selected observable O.sub.U=Σ.sub.zO.sub.U(z)|zcustom-charactercustom-characterz| maps each bit string or measurement outcome z to a real value O.sub.U(z). Each value O.sub.U(z) depends on the random circuit U, and the calculation of experimental values {O.sub.U(z.sub.j)} requires classical simulations of U, e.g., for a linear cross entropy observable Np.sub.U(z) where p.sub.U(z)=|custom-characterz|U|Ocustom-character.sup.2 if the initial state is |Ocustom-character, calculating the value p.sub.U(z.sub.j)=|custom-characterz.sub.j|U|Ocustom-character|.sup.2 for a specific bit string z.sub.j measured in an experiment requires a simulation of U. For a set of M measurement results {z.sub.j}”
obtaining an outcome value by applying the sequence of M quantum gates to N qubits of a quantum computing device (see Castrillo: Fig.1, [0046], “The classical processor 102 receives as input data 106 representing a quantum logic gate or quantum circuit to be benchmarked. For example, the input data 106 may include data representing an n-qubit quantum logic gate that the quantum computing hardware 104 is configured to implement. The input data 106 may also specify a type of observable to use when benchmarking the quantum logic gate or quantum circuit. Example observables are described in detail below with reference to FIGS. 2 and 3.”);
obtaining, by [… ] classical simulation, a probability of obtaining the outcome value given the application of the selected sequence of M quantum gates (see Castrillo: Fig.4, [0101], “The system performs statistical tests using the calculated distribution of random variables associated with the selected observable to obtain additional statistical information about the quantum circuit (step 404). For example, the system can validate fidelities estimated using process 200 or 300 by performing a Kolmogorov-Smirnov test using experimental data, e.g., data obtained based on Equation (6), to reject the null hypothesis that the fidelity estimates are 0. As another example, the system can determine a Kolmogorov-Smirnov p-value for the cumulative distribution function of the experimental data given the estimate of the fidelity α. A large Kolmogorov-Smirnov p-value indicates that the assumptions of the model and the estimate of alpha are correct.”)
generating an averaged probability using the obtained probability and second probabilities obtained by applying to the N qubits second sequences of M quantum gates selected from the group (see Castrillo: Fig.2: [0095], “The system determines the estimate of the fidelity {circumflex over (α)} of the random quantum circuit U using the determined estimate {circumflex over (R)}.sub.U, {circumflex over (V)}.sub.U and {circumflex over (N)}.sub.U. That is, the system solves for {circumflex over (α)} in Equation (14) using {circumflex over (R)}.sub.U, {circumflex over (V)}.sub.U and {circumflex over (N)}.sub.U. The system can then determine an average of the determined estimates for each random quantum circuit to obtain an estimate of circuit fidelity at the circuit depth d and number of qubits n.” … see also [0097] describing “system may further determine one or more properties of the random quantum circuit using individual estimations of the fidelity of a random quantum circuit {circumflex over (α)}, an average estimate of fidelity and/or additional information about the random quantum circuit obtained using the example process 400 described below with reference to FIG. 4.”); and
providing a fidelity benchmark for the M quantum gates based at least in part on the obtained probability (see Castrillo: Fig.6, [0090], “The system determines an estimate of the fidelity {circumflex over (α)} for each defined random quantum circuit (step 306). The system estimates the fidelity {circumflex over (α)} for a respective random quantum circuit by solving Equation (12) for the random quantum circuit. That is, the system estimates the expectation value Trρ.sub.UO.sub.U (left hand side of Equation 12) of the selected observable O.sub.U with respect to the output ρ.sub.U of an experimental implementation of the random quantum circuit.”)
Castrillo does not teach a method of benchmarking a quantum device comprising:
the quantum gates in the group being capable of polynomial-time classical simulation and
obtaining, by polynomial-time classical simulation, a probability of obtaining the outcome value.
wherein obtaining an outcome value by applying the sequence of M quantum gates to N qubits of a quantum computing device comprises: decomposing, by a gate decomposition module, the sequence of M quantum gates into sequence of native gates physically implemented on the quantum computing device; providing, by an instruction generation module, microwave pulses to the N qubits to apply the native gates; and transforming, by a data processing module, output signal of the quantum computing device into discrete outcome value.
However, Aaronson teaches a method of benchmarking a quantum device comprising:
the quantum gates in the group being capable of polynomial-time classical simulation ( see Aaronson: Pg.1, Section 1: stating:
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obtaining, by polynomial-time classical simulation, a probability of obtaining the outcome value (see Aaronson: Pg.3, Section III stating:
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Because both Castrillo and Aaronson are in the same/similar field of quantum computing, accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the random circuit benchmarking method of Castrillo to include the randomly selected gate sequence to Clifford dates and to obtain the outcome probabilities using the polynomial time classical stabilizer simulation technique as taught by Aaronson. One would have been motivated to make such a combination in order to provide improved benchmarking process faster scalable and traceable without affection the fidelity models and results.
Castrillo and Aaronson does not teach the system wherein:
obtaining an outcome value by applying the sequence of M quantum gates to N qubits of a quantum computing device comprises: decomposing, by a gate decomposition module, the sequence of M quantum gates into sequence of native gates physically implemented on the quantum computing device; providing, by an instruction generation module, microwave pulses to the N qubits to apply the native gates; and transforming, by a data processing module, output signal of the quantum computing device into discrete outcome value.
However, Smith teaches the system wherein:
obtaining an outcome value by applying the sequence of M quantum gates to N qubits of a quantum computing device (see Smith: Fig.3, [0067], “At 310, the schedule generated at 308 is executed. Executing the schedule may include generating and sending control signals to components of a quantum computing system (e.g., qubit devices, resonator devices, or other types of quantum circuit devices), modifying (writing, updating, or other operations) the memory 202, or both, according to the schedule. T”), comprises:
decomposing, by a gate decomposition module, the sequence of M quantum gates into sequence of native gates physically implemented on the quantum computing device (see Smith: Fig.3, [0064], “At 304, native instructions are generated. The native instructions may be instructions for a particular quantum computing system architecture that will execute the quantum program obtained at 302.”);
providing, by an instruction generation module, microwave pulses to the N qubits to apply the native gates(see Smith: Fig.3, [0065], “At 306, events are identified based on the native instructions generated at 304. The events may be configured, for example, to encode information in qubit devices, to process the information by performing quantum logic gates or other types of operations, or to extract information from qubit devices. For example, in some instances, the events are microwave pulses configured to stimulate a qubit device, a resonator device, or another type of microwave quantum circuit device.”); and
transforming, by a data processing module, output signal of the quantum computing device into discrete outcome value (see Smith: Fig.1A, [0028], “the signal delivery system 106 receives qubit readout signals from the quantum processor cell and delivers the qubit readout signals to the control system 110. In some instances, the signal delivery system 106 performs preprocessing, signal conditioning or other operations on the readout signals before delivering them to the control system 110. In some implementations, the signal delivery system 106 includes input and output processing hardware, input and output connections, and other components. The input and processing hardware may include, for example, filters, attenuators, directional couplers, multiplexers, diplexers, bias components, signal channels, isolators, amplifiers, power dividers and other types of components.”)
Because Castrillo, Aaronson and Smith are in the same/similar field of quantum computing, accordingly, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the random circuit benchmarking method of Castrillo to include the native gate compilation, microwave pulse control and digitized qubit readout processing as taught by Aaronson. One would have been motivated to make such a combination in order to provide improved supercomputers in computing performance and efficiency, and may be used in pharmaceutical applications (e.g., drug discovery), chemical engineering and synthesis, machine learning and artificial intelligence, medicine or medical diagnosis, or other applications which might benefit from high-performance computers. (see Smith [0016])
Regarding Claim 2,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the method wherein:
providing the fidelity benchmark comprises: dividing by M a function of the averaged probability, the quotient being the fidelity benchmark (see Castrillo: Fig.2, [0075], “The system processes the estimated polarization parameter values p.sup.d to obtain an estimate of the value of the polarization parameter p of Equation (1) (step 208). For example, the system can fit the estimates p.sup.d for different depths d as an exponential decay in d and extrapolate to obtain an estimate of p for d=1. Fitting the estimates this way distinguishes the polarization parameter p for the single application of the quantum circuit from state preparation and measurement errors (SPAM). More explicitly, SPAM errors can be modeled as a constant depolarizing fidelity S, independent of d, and fitting the exponential decay of Sp.sup.d as a function of d enables the system to fit p independently of the SPAM errors.”)
Regarding Claim 3,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the method wherein:
providing the fidelity benchmark comprises: determining, based in part on the averaged probability, a fidelity function, an exponential decay coefficient of the fidelity function being the fidelity benchmark (see Castrillo: Fig.2, [0076], “The system can use the estimate of p for d=1 (the polarization per cycle) to determine the fidelity of the individual gate G.sub.n. For example, the system can obtain an estimate of the polarization p.sub.1,n for a single qubit gate in a circuit with n qubits from previous randomized benchmarking or cross-entropy benchmarking experiments. The system can then estimate a polarization per cycle p.sub.n for the gate G.sub.n as p/p.sub.1,n.sup.n. This polarization per cycle p.sub.n can be converted into a measure of fidelity for the gate G.sub.n using F=p.sub.n+(1−p.sub.n)/D, where D=2.sup.n represents the Hilbert space dimension.”)
Regarding Claim 4,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the method wherein:
the group of quantum gates comprises a group of Clifford gates (see Aaronson: Pg.3, Section III stating [0070], We call a stabilizer circuit unitary if it does not contain measurement gates. Unitary stabilizer circuits are also known as Clifford group circuits.”
See motivation to combine in Claim 1
Regarding Claim 5,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the method wherein:
the N qubits comprise superconducting circuit, trapped ion, or photonic qubits (see Castrillo: Fig.1, [0043], “The quantum computing hardware 104 includes components for performing quantum computations using quantum circuits. For example, the quantum computing hardware 104 includes a quantum system 120 and control devices 122. The quantum system 120 includes one or more multi-level quantum subsystems, e.g., qubits, that are used to perform algorithmic operations or quantum computations.”)
Regarding Claim 6,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the system comprising :
N is greater than 100 (see Castrillo: Fig.1, [0031], “In addition, the presently described techniques are not restricted to particular observables, e.g., cross entropy observables, but can be applied in conjunction with different observables that can provide more accurate estimates of fidelity for a particular quantum circuit. In addition, the presently described techniques are applicable to any quantum logic gates and is not restricted to Clifford gates. In addition, the presently described techniques provide increased scalability, e.g., to 40 qubits or beyond.”)
Regarding Claim 7,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the system comprising :
M is greater than 20 (see Castrillo: Fig.1, [0075], “The system can fit the estimates p.sup.d for different depths d as an exponential decay in d and extrapolate to obtain an estimate of p for d=1. Fitting the estimates this way distinguishes the polarization parameter p for the single application of the quantum circuit from state preparation and measurement errors (SPAM). More explicitly, SPAM errors can be modeled as a constant depolarizing fidelity S, independent of d, and fitting the exponential decay of Sp.sup.d as a function of d enables the system to fit p independently of the SPAM errors.”)
Regarding Claim 8,
As shown above, Castrillo, Aaronson and Smith teaches all the limitations of claim 1. Castrillo further teaches the system comprising :
the N qubits comprise a transmon or fluxonium qubit (see Castrillo: Fig.1, [0043], “quantum computing hardware 104 includes and how they interact with one another is dependent on a variety of factors including the type of quantum computations that the quantum computing hardware is performing. For example, the multi-level quantum subsystems may include qubits that are realized via atomic, molecular or solid-state quantum systems. In other examples the qubits may include, but are not limited to, superconducting qubits or semi-conducting qubits.”)
Regarding independent Claim 9 and Claim 17,
Claim 9 is directed to a system claim and Claim 17 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 1 and are rejected under same rationale respectively.
Regarding claim 10 and 18,
Claim 10 is directed to a system claim and Claim 18 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 2 and are rejected under same rationale respectively.
Regarding Claim 11 and 19,
Claim 11 is directed to a system claim and Claim 19 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 3 and are rejected under same rationale respectively.
Regarding Claim 12 and 20,
Claim 12 is directed to a system claim and Claim 20 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 4 and are rejected under same rationale respectively.
Regarding Claim 13 and 21,
Claim 13 is directed to a system claim and Claim 21is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 5 and are rejected under same rationale respectively.
Regarding Claim 14 and 22,
Claim 14 is directed to a system claim and Claim 22 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 6/7 and are rejected under same rationale respectively.
Regarding Claim 15 and 22,
Claim 15 is directed to a system claim and Claim 22 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 6/7 and are rejected under same rationale respectively.
Regarding Claim 16 and 23,
Claim 16 is directed to a system claim and Claim 23 is directed to computer readable medium claim and the claims have similar/same claim limitation as Claim 8 and are rejected under same rationale respectively.
Response to Arguments
Claim Rejections - 35 U.S.C. § 101
Regarding the 35 U.S.C. 101 rejection for being directed non-statutory subject matter has been withdrawn based on applicant amendments and. Therefore, the 35 U.S.C. 101 rejection has been withdrawn.
Claim Rejections - 35 U.S.C. § 103,
Applicant’s arguments with respect to claim amendments have been considered but are moot considering the new combination of references being used in the current rejection. The new combination of references was necessitated by Applicant’s claim amendments. Therefore, the claims are rejected under the new combination of references as indicated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PGPUB
NUMBER:
INVENTOR-INFORMATION:
TITLE / DESCRIPTION
US 20230176935 A1
Earnest-Noble;
Title: QUANTUM ERROR MITIGATION BASED ON SCALED GATES
Description: The subject disclosure relates to error mitigation in quantum circuits, and more specifically, to the incorporation of scaled quantum gates into a quantum circuit to achieve one or more stretch factors that can control an amount of noise experienced by the quantum circuit.
US 20190156239 A1
Martinis; John
Title: FIDELITY ESTIMATION FOR QUANTUM COMPUTING SYSTEMS
Description: ] This specification relates to quantum computing.;
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZELALEM W SHALU whose telephone number is (571)272-3003. The examiner can normally be reached M- F 0800am- 0500pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cesar Paula can be reached at (571) 272-4128. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zelalem Shalu/Examiner, Art Unit 2145
/CESAR B PAULA/Supervisory Patent Examiner, Art Unit 2145
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