Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to remarks filed 12/09/2025.
Claims 1, 5-11, 15, 16, and 20 are pending and presented for examination. Claims 1, 7, 8, and 15 are amended. Claims 2-4, 12-14, and 17-19 are cancelled. No claims are added.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/09/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 5, 7, 11, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Birrittella et al. (US 20150222533 A1, hereinafter, “Birrittella”), in view of Dinan et al. (US 20170085625 A1, hereinafter “Dinan”).
RE Claim 1: Birrittella discloses:
A method of static dispersive routing of packets in a high-performance computing ('HPC') environment, the HPC computing environment including a fabric comprising a topology of a plurality of switches and links, (Dispersive routing of packets using an Entropy Field in a high performance computing environment. Network fabric topology consists of multiple ethernet links and switches.) (¶0001 High-performance computing (HPC); ¶0355 The Entropy field is used for dispersive routing; ¶0355 packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion; Fig. 1 element 102; ¶0007 Recently, high-speed interconnect fabrics are being developed that provide enhancements over Ethernet and InfiniBand that are facilitated, in part, by new protocols. However, much of the current HPC software has been developed to exchange data using Ethernet and/or InfiniBand protocols; Fig. 1 elements 124, 132, 134, 136; ¶0088 Host Fabric Interface (HFI); ¶0089 Links are full-duplex, point-to-point interconnects that connect HFIs to switches, switches to other switches, or switches to gateways)
the method comprising:
generating an entropy value ( entropy field value computed as function of address by network software for an OS on a VM machine) (Fig. 50a, 50b; ¶0355 The Entropy field is used for dispersive routing; ¶0393 An Entropy value is contained in the Entropy field that enables in-order multi-pathing of different flows between endpoints across the fabric, the entropy field value may be computed by a hash function of the source and destination MAC addresses; ¶0431 Prior to becoming Ethernet frames, various operations would be performed by networking software for an OS running on a VM on node 5308, such as Layer 4, Layer 3, and Layer 2 operations. Optionally, some of these operations are performed by Fab-vNIC 5316.);
wherein the entropy value is calculated by an application in dependence upon information describing a fabric provided by a fabric manager (¶0092 switches are a Layer 2 devices and act as packet forwarding mechanisms within a fabric. Switches are centrally provisioned and managed by the fabric management software, and each switch includes a management agent to respond to management transactions. Central provisioning means that the forwarding tables are programmed by the fabric management software to implement specific fabric topologies and forwarding capabilities, like alternate routes for adaptive routing; Fig. 47/50a 10B header format with Entropy, Fig. 48/50b 16B header format with Entropy; Fig. 53a elements 5302, 5306, 5304, 5314, 5308, 5326; ¶0389 As shown in FIGS. 50a and 50b, the header fields in the first 8 bytes both formats are the same. The first of these header fields is a 20-bit SLID that identifies the HFI or gateway endpoint source that introduced the Ethernet packet onto the fabric, and is assigned by the Fabric Manager during initialization. This is followed by an 11-bit length field that identifies the length of the entire FP content in flits. The 20-bit DLID identifies the intended destination(s) for the encapsulated Ethernet packet on the fabric; Fig. 55a, 55b);
receiving, by a switch, a plurality of packets, where each packet includes a header with the entropy value and a destination local identifier ('DLID') value (10B and 16B header formats define packets with entropy and DLID information) (Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; ¶0393 The Entropy field is 8 bits for the 10B header and 16 bits for the 16B header; Fig. 38; ¶0307 forwarding routing table 3808 uses the Destination Local Identifier (DLID) of packet 3818 to determine an output port for this packet; ¶0338 Routing Header and the Base Transport Header are directly used by the Link Fabric Sub-Layer when routing this packet. These fields include the SC, LVer, SL, LNH, DLID, Length, SLID, P_Key, (F)ECN, and (B)ECN fields, which are depicted with crosshatching in FIG. 49);
and routing , by the switch in dependence upon the entropy value and the DLID value, the packets to a next switch in order. (Fabric packet header fields, Fig. 17, 55, 55b; Table 3, contain an entropy value and DLID value which are used to determine routing of the packet to the next hop.) (Fig. 17, 55, 55b; Table 3; ¶0092 Central provisioning means that the forwarding tables are programmed by the fabric management software to implement specific fabric topologies and forwarding capabilities, like alternate routes for adaptive routing. Switches are responsible for executing QoS features such as adaptive routing and load balancing, and also implement congestion management functions; ¶Abstract The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated; ¶0148 When the flits for a Fabric Packet traverse a routing path including multiple hops, a portion of the flits may be preempted at one or more switches; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices.; Table 3, Link Next Header; ¶0334 A set of Fabric Packet header fields are present at the beginning of each packet spanning multiple bytes that provides a variety of information to help route the packet toward the destination endpoint; ¶0428 The 64b/66b encoded Ethernet frames are then transmitted to the next hop to reach the Ethernet endpoint device associated with the MAC destination address. In the example of FIG. 53a, the next hop is Ethernet switch 5324)
Birrittella does not explicitly disclose:
wherein the application calculates the entropy value in dependence upon a rank, tag, and context value;
However, Dinan discloses:
wherein the application calculates the entropy value in dependence upon a rank, tag, and context value (Each MPI may be described by a three-tuple (c, s, t) corresponding to a communicator, a source rank, and a tag. Communicator is an integer identifier, e.g. Context ID, source rank is the rank of the sending process, and the tag is a user defined tag. Further, source rank and/or the tag may be expressed as a wildcard or “don’t care” value. ¶0028. Hash module generates a hash according to hash(c, s, t) where c is the communicator, s is source rank, and t is tag. ¶0029; Hash function and/or parameters used may vary depending on embodiment. ¶0026; Examiner interprets hash function of three values results as an entropy value given a single bit change of input values results in a different hash output.);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Birrittella, generating an entropy value based on switch fabric information, with the teachings of Dinan, generating an entropy value based on message passing protocols.
The motivation in doing so would be to support dispersive routing where the content of the field is controlled by the upper L4 transfer layer such as MPI. By using this field, packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion. Entropy may also be used by an L4 implementation to provide receive side scaling, in which case the entropy value may be used by an end point to select which receive queue and/or receive processing thread is to be used to process the packet. (Birrittella: Abstract, ¶¶0003, 0006, 0007, 0355, 0393; Dinan: Abstract: ¶¶0001, 0027-0031, Fig. 2)
RE Claim 5: Birrittella discloses:
The method wherein routing, by the switch in dependence upon the entropy value and the DLID value, the packet to a next switch includes parsing entropy and DLID values and determining whether to forward the packets along a minimal or non-minimal hop toward the destination. (Entropy field is used for dispersive routing where packets may hash over all valid paths. The entropy value contained in the Entropy field enables in-order (minimal) or out-of-order (non-minimal) traffic. In addition the Link Fabric may optimize for latency with minimal hop-count or non-minimal hops depending on latency requirements) (Fig. 50a, 50b; ¶0355 The Entropy field is used for dispersive routing, by using this field, packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion.; ¶0393 An Entropy value is contained in the Entropy field that enables in-order multi-pathing of different flows between endpoints across the fabric, the entropy field value may be computed by a hash function of the source and destination MAC addresses; Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; ¶0393 The Entropy field is 8 bits for the 10B header and 16 bits for the 16B header; Fig. 38; ¶0307 forwarding routing table 3808 uses the Destination Local Identifier (DLID) of packet 3818 to determine an output port for this packet; ¶0338 Routing Header and the Base Transport Header are directly used by the Link Fabric Sub-Layer when routing this packet. These fields include the SC, LVer, SL, LNH, DLID, Length, SLID, P_Key, (F)ECN, and (B)ECN fields, which are depicted with crosshatching in FIG. 49; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; When optimizing for latency, the fabric minimizes the hop-count toward the destination. When optimizing for bandwidth, non-minimal routing may be utilized for spreading the traffic to reduce congestion.)
RE Claim 7: Birrittella discloses:
The method further comprising identifying an intermediate hop in dependence upon the entropy value when the parsed entropy and DLID values determine a non-minimal hop. (Entropy field is used for dispersive routing where packets may hash over all valid paths. The entropy value contained in the Entropy field enables in-order (minimal) or out-of-order (non-minimal) traffic. In addition the Link Fabric may optimize for latency with minimal hop-count or non-minimal hops depending on latency requirements) (Fig. 50a, 50b; ¶0355 The Entropy field is used for dispersive routing, by using this field, packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion.; ¶0393 An Entropy value is contained in the Entropy field that enables in-order multi-pathing of different flows between endpoints across the fabric, the entropy field value may be computed by a hash function of the source and destination MAC addresses; Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; ¶0393 The Entropy field is 8 bits for the 10B header and 16 bits for the 16B header; Fig. 38; ¶0307 forwarding routing table 3808 uses the Destination Local Identifier (DLID) of packet 3818 to determine an output port for this packet; ¶0347 For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; When optimizing for latency, the fabric minimizes the hop-count toward the destination. When optimizing for bandwidth, non-minimal routing may be utilized for spreading the traffic to reduce congestion.)
RE Claim 11: Birrittella discloses:
The method wherein the entropy value comprises a hashed pseudorandom value.
( Entropy field value may be calculated by a hash of addresses. Packet may be routed in-order, out-of-order, randomly, or fixed. For random routing the address is selected randomly and hashed) (¶0355 The Entropy field is used for dispersive routing; ¶0355 packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion; ¶0393 For Ethernet packets, the entropy field value may be computed by a hash function of the source and destination MAC addresses present in the L2 header of the Ethernet packet, or by any other means designed to provide diversity in the hash value while maintaining the same value for a given packet flow when in-order delivery across the fabric is important.; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; ¶0356 adaptive routing for a particular topology may choose to select routing choices randomly;)
RE Claim 15: Birrittella discloses:
A system of static dispersive routing of packets in a high-performance computing ('HPC') environment, (¶0355 The Entropy field is used for dispersive routing; ¶0355 packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion) 0001 High-performance computing (HPC))
the HPC computing environment including a fabric comprising a topology of a plurality of switches and links, (Fig. 1 element 102; ¶0007 Recently, high-speed interconnect fabrics are being developed that provide enhancements over Ethernet and InfiniBand that are facilitated, in part, by new protocols. However, much of the current HPC software has been developed to exchange data using Ethernet and/or InfiniBand protocols; Fig. 1 elements 124, 132, 134, 136; ¶0088 Host Fabric Interface (HFI); ¶0089 Links are full-duplex, point-to-point interconnects that connect HFIs to switches, switches to other switches, or switches to gateways)
the system comprising automated computing machinery configured for: (¶0081 The architecture may be implemented to interconnect CPUs and other subsystems that comprise a logical message passing configuration, either by formal definition, such as a supercomputer, or simply by association, such a group or cluster of servers functioning in some sort of coordinated manner due to the message passing applications they run, One type of node, called a Host, is the type on which user-mode software executes. In one embodiment, a Host comprises a single cache-coherent memory domain, regardless of the number of cores or CPUs in the coherent domain, and may include various local I/O and storage subsystems. The type of software a Host runs may define a more specialized function, such as a user application node, or a storage or file server, and serves to describe a more detailed system architecture)
generating an entropy value; ( entropy field value computed as function of address by network software for an OS on a VM machine) (¶0355 The Entropy field is used for dispersive routing; ¶0393 An Entropy value is contained in the Entropy field that enables in-order multi-pathing of different flows between endpoints across the fabric, the entropy field value may be computed by a hash function of the source and destination MAC addresses);
wherein the entropy value is calculated by an application in dependence upon information describing a fabric provided by a fabric manager (¶0092 switches are a Layer 2 devices and act as packet forwarding mechanisms within a fabric. Switches are centrally provisioned and managed by the fabric management software, and each switch includes a management agent to respond to management transactions. Central provisioning means that the forwarding tables are programmed by the fabric management software to implement specific fabric topologies and forwarding capabilities, like alternate routes for adaptive routing; Fig. 47/50a 10B header format with Entropy, Fig. 48/50b 16B header format with Entropy; Fig. 53a elements 5302, 5306, 5304, 5314, 5308, 5326; ¶0389 As shown in FIGS. 50a and 50b, the header fields in the first 8 bytes both formats are the same. The first of these header fields is a 20-bit SLID that identifies the HFI or gateway endpoint source that introduced the Ethernet packet onto the fabric, and is assigned by the Fabric Manager during initialization. This is followed by an 11-bit length field that identifies the length of the entire FP content in flits. The 20-bit DLID identifies the intended destination(s) for the encapsulated Ethernet packet on the fabric; Fig. 55a, 55b);
receiving, by a switch, a plurality of packets, where each packet includes a header with the entropy value and a destination local identifier ('DLID') value; (10B and 16B header formats define packets with entropy and DLID information) (Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; ¶0393 The Entropy field is 8 bits for the 10B header and 16 bits for the 16B header; Fig. 38; ¶0307 forwarding routing table 3808 uses the Destination Local Identifier (DLID) of packet 3818 to determine an output port for this packet; ¶0338 Routing Header and the Base Transport Header are directly used by the Link Fabric Sub-Layer when routing this packet. These fields include the SC, LVer, SL, LNH, DLID, Length, SLID, P_Key, (F)ECN, and (B)ECN fields, which are depicted with crosshatching in FIG. 49)
and routing, by the switch in dependence upon the entropy value and the DLID value, the packets to a next switch in order. (Fabric packet header fields provides a variety of information to help route the packet toward the endpoint. Encoded Ethernet frames are then transmitted to the next hop. ) (Fig. 17, 55, 55b; Table 3; ¶0092 Central provisioning means that the forwarding tables are programmed by the fabric management software to implement specific fabric topologies and forwarding capabilities, like alternate routes for adaptive routing. Switches are responsible for executing QoS features such as adaptive routing and load balancing, and also implement congestion management functions; ¶Abstract The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated; ¶0148 When the flits for a Fabric Packet traverse a routing path including multiple hops, a portion of the flits may be preempted at one or more switches; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices.; Table 3, Link Next Header; ¶0334 A set of Fabric Packet header fields are present at the beginning of each packet spanning multiple bytes that provides a variety of information to help route the packet toward the destination endpoint; ¶0428 The 64b/66b encoded Ethernet frames are then transmitted to the next hop to reach the Ethernet endpoint device associated with the MAC destination address. In the example of FIG. 53a, the next hop is Ethernet switch 5324)
Birrittella does not explicitly disclose:
wherein the application calculates the entropy value in dependence upon a rank, tag, and context value;
However, Dinan discloses:
wherein the application calculates the entropy value in dependence upon a rank, tag, and context value (Each MPI may be described by a three-tuple (c, s, t) corresponding to a communicator, a source rank, and a tag. Communicator is an integer identifier, e.g. Context ID, source rank is the rank of the sending process, and the tag is a user defined tag. Further, source rank and/or the tag may be expressed as a wildcard or “don’t care” value. ¶0028. Hash module generates a hash according to hash(c, s, t) where c is the communicator, s is source rank, and t is tag. ¶0029; Hash function and/or parameters used may vary depending on embodiment. ¶0026; Examiner interprets hash function of three values results as an entropy value given a single bit change of input values results in a different hash output.);
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Birrittella, generating an entropy value based on switch fabric information, with the teachings of Dinan, generating an entropy value based on message passing protocols.
The motivation in doing so would be to support dispersive routing where the content of the field is controlled by the upper L4 transfer layer such as MPI. By using this field, packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion. Entropy may also be used by an L4 implementation to provide receive side scaling, in which case the entropy value may be used by an end point to select which receive queue and/or receive processing thread is to be used to process the packet. (Birrittella: Abstract, ¶¶0003, 0006, 0007, 0355, 0393; Dinan: Abstract: ¶¶0001, 0027-0031, Fig. 2)
RE Claim 16: Birrittella discloses:
The system further configured for routing, by the switch in dependence upon the entropy value and the DLID value, the packets to a next switch including parsing entropy and DLID values and determining whether to forward the packets along a minimal or non- minimal hop toward the destination. (Entropy field is used for dispersive routing where packets may hash over all valid paths. The entropy value contained in the Entropy field enables in-order (minimal) or out-of-order (non-minimal) traffic. In addition the Link Fabric may optimize for latency with minimal hop-count or non-minimal hops depending on latency requirements) (Fig. 50a, 50b; ¶0355 The Entropy field is used for dispersive routing, by using this field, packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion.; ¶0393 An Entropy value is contained in the Entropy field that enables in-order multi-pathing of different flows between endpoints across the fabric, the entropy field value may be computed by a hash function of the source and destination MAC addresses) (Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; ¶0393 The Entropy field is 8 bits for the 10B header and 16 bits for the 16B header; Fig. 38; ¶0307 forwarding routing table 3808 uses the Destination Local Identifier (DLID) of packet 3818 to determine an output port for this packet; ¶0338 Routing Header and the Base Transport Header are directly used by the Link Fabric Sub-Layer when routing this packet. These fields include the SC, LVer, SL, LNH, DLID, Length, SLID, P_Key, (F)ECN, and (B)ECN fields, which are depicted with crosshatching in FIG. 49; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; When optimizing for latency, the fabric minimizes the hop-count toward the destination. When optimizing for bandwidth, non-minimal routing may be utilized for spreading the traffic to reduce congestion.)
RE Claim 20: Birrittella discloses:
The system wherein the entropy value comprises a hashed pseudorandom value.
( Entropy field value may be calculated by a hash of addresses. Packet may be routed in-order, out-of-order, randomly, or fixed. For random routing the address is selected randomly and hashed) (¶0355 The Entropy field is used for dispersive routing; ¶0355 packets travelling toward an endpoint can hash over all the valid paths to help the spreading of traffic and ease congestion; ¶0393 For Ethernet packets, the entropy field value may be computed by a hash function of the source and destination MAC addresses present in the L2 header of the Ethernet packet, or by any other means designed to provide diversity in the hash value while maintaining the same value for a given packet flow when in-order delivery across the fabric is important; ¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; ¶0356 adaptive routing for a particular topology may choose to select routing choices randomly;)
Claim 6, 8-10, are rejected under 35 U.S.C. 103 as being unpatentable over Birrittella in view of Dinan, in view of Cheng et al. (US 20180083868 A1, hereinafter, “Cheng”).
RE Claim 6: Birrittella discloses:
The method wherein determining whether to forward the packets along a minimal or non-minimal path further comprises by comparing an entropy value (Entropy field is used for dispersive routing where packets may hash over all valid paths. The entropy value contained in the Entropy field enables in-order (minimal) or out-of-order (non-minimal) traffic. In addition the Link Fabric may optimize for latency with minimal hop-count or non-minimal hops depending on latency requirements) (¶0347 When the top bit, RC[2], is unset, the bottom bit, RC[0], informs the fabric if the packet is to be routed in-order. For a packet that is allowed to be routed out-of-order, depending on the capability of the fabric, the packet may be routed randomly or be routed based on the congestion level of the routing choices; When optimizing for latency, the fabric minimizes the hop-count toward the destination. When optimizing for bandwidth, non-minimal routing may be utilized for spreading the traffic to reduce congestion ¶0348 Depending on the topology and the routing methods supported by the fabric, each switch examines what is specified in the RC field setting, but may choose to route the packet in a more restrictive manner. In one embodiment, a packet is not allowed to be routed out-of-order if the setting of this field has specified in-order routing. It is permitted however, to route packets in-order even though out-of-order is specified.
Birrittella does not explicitly disclose:
comparing an entropy value for a current dimension with the DLID coordinate for the same dimension.
However, Cheng discloses:
comparing an entropy value for a current dimension with the DLID coordinate for the same dimension. ( Multidimensional fabric may have DLID partitioned into multiple subfields to support network topologies. Data or other information may be transmitted by encapsulating with DLID and other information. A rand number generation module may generate a random value for combination with DLID. In adaptive mode, packets may take different paths due to randomization, e.g. entropy) (Fig. 1, element 100; ¶0022 The fabric 100 in this illustration is laid out in a 2-dimensional array (along the x and y axis) for simplicity. In some embodiments, the fabric may be extended into a third dimension (along the z axis) and/or into higher dimensions; ¶0024 In some embodiments, data or other information may be transmitted from one PE to any other PE by encapsulating the data in a packet that includes a header specifying a destination node address (DLID) and other routing information. The packet may then be routed along a path through any number of switches that each determines the next step in the path based on the packet header contents and further based on routing tables and CSRs within that switch; ¶0034 the DLID may be partitioned into multiple subfields to support configurable network topologies and sizes; ¶0044 Rand number generation module 614 may be configured to generate a pseudo-random value which is then processed by mask and shift module 616 to extract certain bit fields from the random value, as specified by the CSRs 302. The processed DLID and random value are then combined by combination logic 618; Fig. 4, elements 408, 410, 412, 414, 416; ¶0034 a switch may be identified by a column subfield 412, specifying the x-coordinate of a switch within the plane, and a row subfield 410, specifying the y-coordinate of the switch; ¶0053 In adaptive mode, however, packets with the same DLID may take different paths due to the randomization function. )
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Birrittella with the teachings of Cheng. Birrittella discloses a method for an entropy value for dispersive routing via enabling multi-pathing of different flows. Cheng discloses a method to sub partition the DLID for multiple dimension topologies using coordinates to locate network elements with combination of random value, i.e. the use of known techniques to improve similar devices (methods and products) in the same way. (Birrittella: ¶0002, 0347, 0355, 0393) ; Cheng: Fig. 4, 6, ¶0002, 0017-0018, 0034, 0044).
RE Claim 8: Birrittella discloses:
The method of claim 5 wherein the fabric comprises a plurality of dimensions (¶0002 There are many types of HPC architectures, both implemented and research-oriented, along with various levels of scale and performance. However, a common thread is the interconnection of a large number of compute units, such as processors and/or processor cores, to cooperatively perform tasks in a parallel manner. Under recent System on a Chip (SoC) designs and proposals, dozens of processor cores or the like are implemented on a single SoC, using a 2-dimensional (2D) array, torus, ring, or another configuration.)
Birrittella does not explicitly disclose:
and the packet header includes a dimension value and wherein routing, by the switch in dependence upon the entropy value and the DLID value, includes identifying the next destination switch to route the packet in dependence upon the dimension value.
However, Cheng discloses:
and the packet header includes a dimension value (dimension and coordinate specification located in multiple hierarchical subfields of DLID) (¶0018 Each routing table may include multiple sub-tables for each hierarchical sub-field of the DLID address. This enables both indirect routing and direct routing at each level of the hierarchy for the topologies and routing modes that apply. For example, a packet may be routed directly through one hierarchy (e.g., from one dimension to another dimension), and indirectly through another hierarchy (e.g., from one switch to another switch within a dimension) and wherein routing, by the switch in dependence upon the entropy value and the DLID value, includes identifying the next destination switch to route the packet in dependence upon the dimension value. ( header specifies destination node and other routing information for routing to any number of switches) (Fig. 6a, 6b, 7, 8, 9; ¶0024 In some embodiments, data or other information may be transmitted from one PE to any other PE by encapsulating the data in a packet that includes a header specifying a destination node address (DLID) and other routing information. The packet may then be routed along a path through any number of switches that each determines the next step in the path based on the packet header contents and further based on routing tables; ¶0027 ¶0071-0073 the table address generation module is further to select the entry from the routing tables additionally based on a first randomly generated value; and further to select the one or more output ports based on a combination of the second subset of the DLID and a second randomly generated value; ¶0018 Each routing table may include multiple sub-tables for each hierarchical sub-field of the DLID address. This enables both indirect routing and direct routing at each level of the hierarchy for the topologies and routing modes that apply. For example, a packet may be routed directly through one hierarchy (e.g., from one dimension to another dimension), and indirectly through another hierarchy (e.g., from one switch to another switch within a dimension)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Birrittella with the teachings of Cheng. Birrittella discloses a high performance compute architecture with a multidimensional array of compute units. Cheng discloses a dimension value from a composite DLID address with table address module to determine routing by use of that information., i.e. the use of known techniques to improve similar devices (methods and products) in the same way. (Birrittella: ¶0002; Cheng: Fig. 4, 6, ¶0002, 0017-0018, 0024, 0027, 0071-0073).
RE Claim 9: Birrittella discloses:
The method wherein the dimension ( dimension of 2D array, torus, ring, and others - ¶0002 There are many types of HPC architectures, both implemented and research-oriented, along with various levels of scale and performance. However, a common thread is the interconnection of a large number of compute units, such as processors and/or processor cores, to cooperatively perform tasks in a parallel manner. Under recent System on a Chip (SoC) designs and proposals, dozens of processor cores or the like are implemented on a single SoC, using a 2-dimensional (2D) array, torus, ring, or another configuration.)
Birrittella does not explicitly disclose:
value is contained in a coordinate specification ('Cspec') field of the packet header.
However, Cheng discloses:
the dimension value is contained in a coordinate specification ('Cspec') field of the packet header. ( dimension and coordinate specification located in multiple hierarchical subfields of DLID - ¶0018 Each routing table may include multiple sub-tables for each hierarchical sub-field of the DLID address. This enables both indirect routing and direct routing at each level of the hierarchy for the topologies and routing modes that apply. For example, a packet may be routed directly through one hierarchy (e.g., from one dimension to another dimension), and indirectly through another hierarchy (e.g., from one switch to another switch within a dimension) (multiple subfields analogous to a ‘Cspec’ field - ¶0034 the DLID may be partitioned into multiple subfields to support configurable network topologies and sizes; Fig. 10; ¶0063 example packet format 1000 consistent with an embodiment of the present disclosure. The packet format shown is a modified Infiniband packet and includes a header 1002, configured to convey control and routing information, and a body 1004 configured to carry the data payload. The header 1002 is shown to include fields for the DLID 1008, the routing control (RC) 1012, and the virtual lane (VL) 1016. Additional fields in the header, containing values which may be expected to remain constant during transmission of a stream of packets between a source node and end node pair where ordering is required, can be used as elements to generate the hash value previously described)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Birrittella with the teachings of Cheng. Birrittella discloses a high performance compute architecture with a multidimensional array of compute units. Cheng discloses a dimension value from a composite DLID address in the header along with other fields., i.e. the use of known techniques to improve similar devices (methods and products) in the same way. (Birrittella: ¶0002; Cheng: Fig. 10, ¶0002, 0017-0018, 0034, 0063).
RE Claim 10: Birrittella discloses:
The method wherein each packet header (Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3)
Birrittella does not explicitly disclose: each packet header further includes a dimension order value and identifying the next destination switch to route the packet in dependence upon the dimension order value further comprises selecting an output port for the packet in dependence upon the dimension order value.
However, Cheng discloses:
each packet header further includes a dimension order value (dimension and coordinate specification located in multiple hierarchical subfields of DLID) (¶0018 Each routing table may include multiple sub-tables for each hierarchical sub-field of the DLID address. This enables both indirect routing and direct routing at each level of the hierarchy for the topologies and routing modes that apply. For example, a packet may be routed directly through one hierarchy (e.g., from one dimension to another dimension), and indirectly through another hierarchy (e.g., from one switch to another switch within a dimension) and identifying the next destination switch to route the packet in dependence upon the dimension order value further comprises selecting an output port for the packet in dependence upon the dimension order value. ( header specifies destination node and other routing information for routing to any number of switches) ( dimension and coordinate specification located in multiple hierarchical subfields of DLID - (Fig. 6a, 6b, 7, 8, 9; ¶0024 In some embodiments, data or other information may be transmitted from one PE to any other PE by encapsulating the data in a packet that includes a header specifying a destination node address (DLID) and other routing information. The packet may then be routed along a path through any number of switches that each determines the next step in the path based on the packet header contents and further based on routing tables; ¶0027; ¶0071-0073 the table address generation module is further to select the entry from the routing tables additionally based on a first randomly generated value; and further to select the one or more output ports based on a combination of the second subset of the DLID and a second randomly generated value; ¶0018 Each routing table may include multiple sub-tables for each hierarchical sub-field of the DLID address. This enables both indirect routing and direct routing at each level of the hierarchy for the topologies and routing modes that apply. For example, a packet may be routed directly through one hierarchy (e.g., from one dimension to another dimension), and indirectly through another hierarchy (e.g., from one switch to another switch within a dimension)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Birrittella with the teachings of Cheng. Birrittella discloses a header with DLID. Cheng discloses a dimension value from a composite DLID address with table address module to determine routing by use of that information., i.e. the use of known techniques to improve similar devices (methods and products) in the same way. (Birrittella: (Fig. 47, 48, 50a, 50b, 53a, 53b, Table 3; Cheng: Fig. 4, 6, ¶0002, 0017-0018, 0024, 0027, 0071-0073).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s first argument is directed towards the interpretation of ‘a rank, tag, and context value’ for calculation of an entropy value. Applicant submits that “Rank, tag, and context, as those terms are used in the present application, are well-known message passing interface (MPI) terms used in parallel processing.”
Examiner notes that the claims, as written, do not recite a message passing interface implementation nor MPI. The claims, as written, do recite ‘High Performance Computing (‘HPC’) environment’. An HPC environment may exist without MPI implementation such as OmniPath as disclosed in the instant application ¶0060. Therefore, the terms, rank, tag, and context are subject to interpretation with mapping to either a MPI or a non-MPI HPC environment.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., message passing interface, MPI, specific information of rank, tag, and context) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
US 20150180782 A1 Rimmer et al.
US 20150180790 A1 Rimmer et al.
US 20170085625 A1 Dinan et al.
US 20230412712 A1 Suthar et al.
US 20170373991 A1 Wilkinson et al.
The above references disclose various aspects of xxx.
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/PAUL A. LANGER/Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419