DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Examiner acknowledges the amending of claim 1.
Response to Arguments
Applicant's arguments filed 05/29/2026 have been fully considered but they are not persuasive.
At pages 6-8 of the currently filed Remarks, the Applicant has argued the art of Tsunoda does not teach cascaded delay elements and that the delay elements are not in series as outlined by the Examiner.
The Examiner does not agree. Tsunoda shows in figure 11 a single “Data” input into the driving system. This signal proceeds first to branching unit #12a where the signal then splits to both of #14 and #13a. Within #13a the original data signal is delayed. The output of #13a, after having been delayed, proceeds then to branching unit #12b which splits the delayed signal to #15 and to #13b. Within #13b the signal is once again delayed. The twice delayed signal then proceeds to #18 and eventually to the laser diode.
The delay elements #13a and #13b are cascaded as the original signal first flows to #13a and then next flows to #13b, in that order. [0054] of Tsunoda states “The second branch unit 12B branches a second branched data signal Data 3 from a first branched data signal Data 1 that is delayed”. In other words, the input to branching unit #12b is a delayed signal (delayed by #13a) and the delayed signal from #12b is then further input to #13b for an additional delay (see dotted arrow flow path in annotated fig.11 below).
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The delay elements are further considered in series as the input signal cannot reach #13b without first traversing #13a. In other words, the signal first proceeds through #13a and then necessarily proceeds through #13b via the branching unit #12b.
The Examiner notes the Applicants’ figure 2 shows the identical type of splitting of the input enable signal. The Examiner provides a rotated view of figure 11 of Tsunoda next to Applicants’ figure 2 for reference.
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The arguments are therefore not found persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7-9, 13-14, 16-20, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsunoda (US 2015/0207500).
With respect to claim 1, Tsunoda teaches an optical driver circuit (fig.11) comprising: a light generating device (fig.11 VCSEL) ; a plurality of drive cells (fig.11 #14/15/18 along with corresponding transistor pairs such as in fig.12 #31, 32/33a) that are configured to pass a total current (fig.12 current output to OUTP/N) to the light generating device, the plurality of drive cells comprising: a first drive cell (fig.11 #14, fig.12 #31) configured to pass a first fraction of the total current (summed at OUTP/N, see fig.11 #16) to the light generating device; a second drive cell (fig.11 #15, fig.12 #32/33a) configured to pass a second fraction of the total current (summed at OUTP/N, see fig.11 #16) to the light generating device; a third drive cell (fig.11 #18, transistor pairs not shown in fig.12-see modification below) configured to pass a third fraction of the total current to the light generating device (summed at OUTP/N, see fig.11 #16); an enable control signal input (fig.11 conductor line bringing in DATA) logically interfaced to each of the plurality of drive cells (DATA connected to each cell in fig.11), the enable control signal input being configured to communicate an enable control signal (fig.11 DATA); and a plurality of delay segments arranged in a cascaded configuration (fig.11 #13a followed by output to #13b), the plurality of delay segments comprising: a first delay segment (fig.11 #13a) logically between the second drive cell and the enable control signal input (as seen in fig.11), the first delay segment configured to delay passing of the enable control signal for a first time period dTa (fig.11 t1); and a second delay segment (fig.11 t2) logically between the first delay segment and the third drive cell (as seen in fig.11), such that the enable control signal passes through the first delay segment before reaching the second delay segment ([0054], fig.11, signal first passes through #13a before proceeding to #13b), the second delay segment is configured to delay passing of the enable control signal for a second time period dTb (fig.11 t2), wherein: the light generating device, when the enable control signal transitions from off to on, receives: the first fraction of the total current from the first drive cell without delay (as fig.11 input to #14 not delayed), the first fraction of the total current from the first drive cell and the second fraction of the total current from the second drive cell after a first time delay (fig.11 after delay t1, current from #14 and #15 applied as in fig.4/7), the first time delay being equal to the first time period Ta (as this is set by #13a). Tsunoda further teaches the additional summed current from fig.11 Data2 via #20 is summed via an additional transistor pair #33a, but does not clearly disclose in fig.12 that the third driving cell of fig.11 #16 makes use of a similar transistor pair arrangement to sum the current for Data3 at #16 in fig.11. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the circuit of fig.11/12 of Tsunoda to make use of an additional transistor pair arrangement such as shown in fig.12 #31, #32/33a for the un-depicted third cell (fig.11 via #18 input of Data3) in order to follow the same approach as disclosed for summing the input currents for Data1 and Data2, as Tsunoda has demonstrated such a configuration to achieve the stated driving goal and largely amounts to a duplication of existing parts (see MPEP 2144.04 IV B).
Tsunoda further teaches each additional Data inputs beyond Data1 to influence (i.e. overlap) each pulse of the original Data/Data1 signal (see fig.1/2a Data2, fig.4/7 Data2, Data2-2, fig.10 Data1-2, Data2, thereby forming Data out) but does not specify that Data3 in fig.11 overlaps in a similar manner such that the first fraction of the total current from the first drive cell, the second fraction of the total current from the second drive cell, and the third fraction of the total current from the third drive cell after a second time delay, the second time delay being equal to a sum of the first time period Ta and the second time period Tb, the sum resulting from the cascaded configuration of the plurality of delay segments, and the light generating device, when the enable control signal transitions from on to off, continues to receive at least the second fraction of the total current from the second drive cell and the third fraction of the total current from the third drive cell for a third time delay, the third time delay being equal to the first time period Ta. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to follow the overlapping of subsequent signals (e.g. Data2, Data2-2, etc.) with each pulse of Data1 as Tsunoda has demonstrated the overlapping sequence and would allow for manipulation of the characteristics of each input pulse which appears to be the purpose of Tsunoda ([0025, 30, 43]).
After the modifications outlined above the following is met: a second delay segment (fig.11 t2) logically between the first delay segment and the third drive cell (fig.11 #18), the second delay segment is configured to delay passing of the enable control signal for a second time period dTb (t2), wherein: the light generating device, when the enable control signal transitions from off to on, receives: the first fraction of the total current from the first drive cell without delay (as no delay element present), the first fraction of the total current from the first drive cell and the second fraction of the total current from the second drive cell after a first time delay (as Data1 and Data2 overlap after delay t1, similar to fig.2), the first time delay being equal to the first time period Ta (as it is provided via #13a), and the first fraction of the total current from the first drive cell, the second fraction of the total current from the second drive cell, and the third fraction of the total current from the third drive cell after a second time delay (as Data1, Data2, Data3 would overlap after delay t2), the second time delay being equal to a sum of the first time period Ta and the second time period Tb, the sum resulting from the cascaded configuration of the plurality of delay signals (as the delay elements #13a/b are in series), and the light generating device, when the enable control signal transitions from on to off, continues to receive at least the second fraction of the total current from the second drive cell and the third fraction of the total current from the third drive cell for a third time delay (as the initial pulse would end but Data2 and Data3 would continue until end of t1, t2, respectively), the third time delay being equal to the first time period Ta (based on sequenced delays of t1, t2).
Annotated fig.12:
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With respect to claim 2, Tsunoda, as modified, teaches each of the plurality of drive cells comprises an enable transistor (annotated fig.12, left transistor in each pair) in a current path of the light generating device (connected via OUTP/N) and logically interfaced to the enable control signal input (as each is directly receiving input therefrom).
With respect to claim 3, Tsunoda, as modified, teaches the plurality of drive cells are configured in parallel with respect to each other (as seen in annotated fig.12), such that each drive cell of the plurality of drive cells is adapted to pass a respective fraction of the total current through the light generating device (summed at fig.12 via OUTP/N).
With respect to claim 4, Tsunoda, as modified, teaches the light generating device is a laser (fig.11 VCSEL).
With respect to claim 5, Tsunoda, as modified, teaches at least one of the plurality of drive cells further comprises a bias control transistor (annotated fig.12 each right side transistor can be considered a bias transistor as it influences the current received at OUTP/N).
With respect to claim 7, Tsunoda, as modified, teaches the optical driver circuit is configured, in response to the enable control signal received at the enable control signal input transitioning from low to high, to generate results in a step-wise function for a current through the light generating device (this occurs based on the modification of overlapping Data1, Data2, Data3 outlined in the rejection to claim 1 and as partially seen in fig.2a with Data1, Data2.). Tsunoda does additionally teach the “-“ and “+” values can be changed to suit the function ([0055]), but does not explicitly state ascending step-wise. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device of Tsunoda to implement an ascending step-wise function as Tsunoda has demonstrated both step-wise operation and the ability to add the signals such that creating a step-wise ascending function would be obvious in order to create a desired signal type (Tsunoda, [0055]).
With respect to claim 8, Tsunoda, as modified, teaches a time width of a step within the step-wise ascending function is equal to at least one of the first time period dTa or the second time period dTb (based on no change of the delay lengths in rejection of claim 7).
With respect to claim 9, Tsunoda, as modified, teaches the optical driver circuit is configured, in response to the enable control signal received at the enable control signal input results in transitioning from high to low, to generate a step-wise descending function for a current through the light generating device (e.g. as shown in fig.2a).
With respect to claim 13, Tsunoda, as modified above, further teaches a method of modifying edge rates (as seen in fig.2a) in the optical driver circuit of claim 1, the method comprising: communicating, with the enable control signal input, the enable control signal to the first drive cell (fig.11 #14 receives Data); enabling, in response to communicating the enable control signal to the first drive cell, the first drive cell to pass the first fraction of the total current to the light generating device (summed at fig.12 OUTP/N), without delay (fig.11 input to #14 not delayed); delaying the enable control signal to create a delayed enable control signal (fig.11 via #13a); and communicating the delayed enable control signal to the second drive cell (as seen in fig.11).
With respect to claim 14, Tsunoda, as modified, teaches the delaying the enable control signal to create the delayed enable control signal is performed by at least one of the plurality of delay elements (fig.11 #13a).
With respect to claim 16, Tsunoda, as modified, teaches passing a step-wise function for the total current through the light generating device (after modifications outlined in claim 1, and partially demonstrated at fig.2a).
With respect to claim 17, Tsunoda, as modified, teaches the enable control signal includes a logic low to a logic high transition (fig.2a Data). Tsunoda does additionally teach the “-“ and “+” values can be changed to suit the function ([0055]), but does not explicitly state ascending step-wise. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device of Tsunoda to implement an ascending step-wise function as Tsunoda has demonstrated both step-wise operation and the ability to add the signals such that creating a step-wise ascending function would be obvious in order to create a desired signal type (Tsunoda, [0055]).
With respect to claim 18, Tsunoda, as modified, teaches the enable control signal includes a logic high to a logic low transition (fig.2 Data) and the step-wise function is a descending step-wise function (as demonstrated in fig.2a).
With respect to claim 19, Tsunoda, as modified, teaches delaying the delayed enable signal (fig.11 via #13b) to create a further delayed enable control signal and communicating the further delayed enable control signal to the third drive cell (as seen in fig.11).
With respect to claim 20, Tsunoda teaches the method outlined above, but does not teach delaying the delayed control signal sequentially an integer number "n" times to create a further n delayed enable control signals and communicating the further n delayed control signals to a plurality of drive cells, respectively. Tsunoda does further teach adding additional branches with delays ([0031]. It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the device/method of Tsunoda to make use of an additional drive cell and summed “n” delay configuration as demonstrated by Tsunoda in order to further control the pulse shape characteristics (Tsunoda, fig.2a/7).
With respect to claim 22, Tsunoda, as modified, teaches the second drive cell is configured to receive the enable control signal from the enable control signal input without delay from the second delay segment (as seen in fig.11, cell associated with #15 does not receive input from second delay #13b).
Claim(s) 10 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsunoda in view of Mizuno (US 2007/0253313).
With respect to claims 10 and 15, Tsunoda, as modified, teaches the device/method outlined above, but does not teach first the delay segment or the second delay segment comprises at least one of a shift register, a buffer, or a timer. Mizuno teaches a related laser driver with delays (fig.4), wherein the delay element is a buffer type (fig.3 #302, inverter is a type of buffer). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the delay element of Tsunoda to make use of a buffer type element as Mizuno has demonstrated such elements are suitable for providing signal delays.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsunoda in view of Shen et al. (US 2020/0381891).
With respect to claim 12, Tsunoda, as modified, teaches the device outlined above, but does not teach the at least one of the first time period dTa or the second time period dTb is configurable. Shen teaches a related laser driver using multiple drive cells (fig.5) as well as using delays within the drivers (fig.2 #108) and the delay to be adjustable ([0045]). It would have been obvious to one of ordinary skill in the art before the filing of the instant application to adapt the system of Tsnoda to make use of adjustable delay elements as demonstrated by Shen in order to control the summed current timing arriving at the laser (Tsunoda, fig.2a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Please see the previously included pto892 sheet for a list of related references.
US 9628082, 9973738, 11996675, 11936159, 2006/0291512 noted for teaching similar delayed laser driving systems/methods.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOD THOMAS VAN ROY whose telephone number is (571)272-8447. The examiner can normally be reached M-F: 8AM-430PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TOD T VAN ROY/ Primary Examiner, Art Unit 2828
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