DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 06/16/2022. Claims 1-20 are currently pending, of which claims 1-4 and 7-20 are currently rejected. Claims 5 and 6 are objected.
Remarks
An attempt was made to reach attorney Neil R. Kardos over the phone on 12/19/2025, and a voicemail was left. No response was received.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
In Claim 1:
a plurality of multiply-accumulate (MAC) components that are each configured to generate a MAC output in claim 1 (interpreted as any known MAC component implemented in hardware)
an adder component configured to generate an adder component output in claim 1 (interpreted as any known adder component implemented in hardware)
a rounding component configured to round the adder component output in claim 1 (interpreted as any known rounding component implemented in hardware)
The following limitations invoke 35 U.S.C. 112(f) because they use the words means and are not modified by sufficient structure, material, or acts for performing the claimed function:
In Claim 16:
means for receiving map data
means for receiving kernel data
means for receiving an indication of an input precision mode that indicates an input word length for the map data and for the kernel data;
means for receiving an indication of an output precision mode that indicates an output word length;
means for generating a plurality of product accumulations based on the map data, the kernel data, and the input precision mode,
means for generating an adder component output based on the input precision mode and one or more product accumulations of the plurality of product accumulations
means for rounding the adder component output to generate a rounded output based on the output precision mode
means for outputting the rounded output
In Claim 17:
means for adding a most significant set of bits of a product accumulation, of the plurality of product accumulations, and a most significant set of bits of a return value to generate a first adder output
means for adding a least significant set of bits of the product accumulation and a least significant set of bits of the return value to generate a second adder output and a carry bit value
means for concatenating the first adder output and the second adder output to generate a first concatenated sum
means for adding the first adder output and the carry bit value to generate a third adder output
means for concatenating the third adder output and the second adder output to generate a second concatenated sum
means for selecting, based on the input precision mode, one of the first concatenated sum or the second concatenated sum as the adder component output
In Claim 18:
means for receiving a control signal that is based on a coordination mode that indicates whether the apparatus is to sum the plurality of product accumulations
means for controlling the return value based on the control signal
In Claim 19:
means for receiving the plurality of product accumulations
means for outputting each product accumulation, of the plurality of product accumulations, across a plurality of clock cycles for generation of the adder component output
In Claim 20:
means for concatenating the plurality of product accumulations for storage in a shift register.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim limitations “means or receiving map data”, “means for receiving kernel data”, “means for receiving an indication of an input precision mode that indicates an input word length for the map data and for the kernel data”, “means for receiving an indication of an output precision mode that indicates an output word length”, “means for generating a plurality of product accumulations based on the map data, the kernel data, and the input precision mode”, means for generating an adder component output based on the input precision mode and one or more product accumulations of the plurality of product accumulations”, “means for rounding the adder component output to generate a rounded output based on the output precision mode”, and “means for outputting the rounded output” in claim 16, “means for adding a most significant set of bits of a product accumulation”, “means for adding a least significant set of bits of the product accumulation and a least significant set of bits of the return value”, “means for concatenating the first adder output and the second adder output to generate a first concatenated sum”, “means for adding the first adder output and the carry bit value to generate a third adder output”, “means for concatenating the third adder output and the second adder output to generate a second concatenated sum”, “means for selecting, based on the input precision mode, one of the first concatenated sum or the second concatenated sum as the adder component output”, in claim 17, “means for receiving a control signal that is based on a coordination mode”, “means for controlling the return value based on the control signal”, in claim 18, “means for receiving the plurality of product accumulations”, “means for outputting each product accumulation”, in claim 19, and “means for concatenating the plurality of product accumulations for storage in a shift register” in claim 20.
Regarding all the limitations specified in the paragraph above, the specification merely repeats the claim language and does not include sufficient structure to perform the claimed features. See rejection under 35 U.S.C. 112(b) rejection below for further details as to the requirement for the written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitations “means for receiving map data”, “means for receiving kernel data”, “means for receiving an indication of an input precision mode that indicates an input word length for the map data and for the kernel data”, “means for receiving an indication of an output precision mode that indicates an output word length”, “means for generating a plurality of product accumulations based on the map data, the kernel data, and the input precision mode”, means for generating an adder component output based on the input precision mode and one or more product accumulations of the plurality of product accumulations”, “means for rounding the adder component output to generate a rounded output based on the output precision mode”, and “means for outputting the rounded output”. These limitations are merely mentioned in paragraph 0213 of the specification and do not include sufficient structure to perform the claimed features. Claims 17-20 inherit the same deficiency as claim 16 by reason of dependence.
Claim 17 recites the limitations “means for adding a most significant set of bits of a product accumulation”, “means for adding a least significant set of bits of the product accumulation and a least significant set of bits of the return value”, “means for concatenating the first adder output and the second adder output to generate a first concatenated sum”, “means for adding the first adder output and the carry bit value to generate a third adder output”, “means for concatenating the third adder output and the second adder output to generate a second concatenated sum”, “means for selecting, based on the input precision mode, one of the first concatenated sum or the second concatenated sum as the adder component output”. These descriptions describe functional language, and no algorithm or structure could be found in the specification. Claim 18 inherits the same deficiency as clam 17 by reason of dependence.
Claim 18 recites the limitations “means for receiving a control signal that is based on a coordination mode”, “means for controlling the return value based on the control signal”. These descriptions describe functional language, and no algorithm or structure could be found in the specification.
Claim 19 recites the limitations “means for receiving the plurality of product accumulations”, “means for outputting each product accumulation”. These descriptions describe functional language, and no algorithm or structure could be found in the specification.
Claim 20 recites the limitation “means for concatenating the plurality of product accumulations for storage in a shift register”. These descriptions describe functional language, and no algorithm or structure could be found in the specification.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-9, 13-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Finch (U.S. Patent Application Publication No.: US 20220405052 A1), hereinafter “Finch”, in view of Taesik Na in NPL: “Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator” (https://dl.acm.org/doi/pdf/10.1145/2934583.2934625), hereinafter “Na”, in view of Willcock (Patent Application Publication No.: US 20220156344 A1), hereinafter “Willcock”, further in view of Himani Upadhyay in NPL: “A High Speed and Low Power 8 Bit x 8 Bit Multiplier Design using Novel Two Transistor (2T) XOR Gates” (https://www.researchgate.net/publication/270898651_A_High_Speed_and_Low_Power_8_Bit_x_8_Bit_Multiplier_Design_using_Novel_Two_Transistor_2T_XOR_Gates), hereinafter “Upadhyay”.
Regarding Claim 1, Finch teaches:
A device, comprising:
…
a first data port configured to receive map data (Fig. 8A, e.g., Input 101);
a second data port configured to receive kernel data (Fig. 8A, e.g., Coefficient 103);
a plurality of [multiplier] components that are each configured to generate a [multiplier] output … (Fig. 3, e.g., shows Mantissa processor outputting the result of multiplying input and coefficient mantissas.),
a set of map words included in the map data, and a set of kernel words included in the kernel data (¶0098, e.g., floating point inputs 101 and coefficient 103 (map data and kernel data) each include 16 floating point values);
an adder component configured to generate an adder component output based on the input precision mode and one or more MAC outputs of a plurality of MAC outputs generated by the plurality of MAC components (Fig. 8A, e.g., shows 40b adder trees 806 (adder component) receiving data from MAC processor pipeline stages; Fig. 8C, e.g., Adder tree receives mode signal; ¶0099, e.g., Adder tree 806 outputs a single resulting sum (adder component output));
a rounding component configured to round the adder component output, … , to generate a rounded output (Fig. 8B, e.g., Normalizer function 809 (rounding component) performs rounding); and
an output port configured to output the rounded output (Fig. 8B, e.g., Output 812/814; ¶0100).
Finch does not teach:
a first precision mode port configured to receive an indication of an input precision mode that indicates a first word length for data input to the device;
a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device;
a plurality of multiply-accumulate (MAC) components that are each configured to generate a MAC output based on the input precision mode,
a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output;
However, Na teaches:
a first precision mode port configured to receive an indication of an input precision mode that indicates a first word length for data input to the device (Fig. 6(b), e.g., FSM controller receives mode signal (through first precision mode port); Page 4, Section 4.2 Flexible MAC, First paragraph);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the FSM Controller receiving a mode signal as taught by Na with the pipelined floating point multiplier as taught by Finch. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations, and Na enhances the model of Finch because it "enables speeding up training for lower precision computation." (Na: Abstract). Combination would cause for the multiplier taught by Finch to generate an output based on the input precision mode taught by Na.
Finch in view of Na do not teach:
a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device;
a plurality of multiply-accumulate (MAC) components that are each configured to generate a MAC output based on the input precision mode,
a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output;
However, Willcock teaches:
a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device (Fig. 3, e.g., shows Post-Processing component 312; ¶0053, e.g., Post-Processing Component 312 can round accumulated values to a lower precisions based on a control signal);
a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output (¶0053, e.g., Post-Processing Component 312 can round accumulated values to a lower precisions based on a control signal (output precision mode));
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the Post-Processing component receiving a control signal to round to a lower precision as taught by Willcock with the normalizer function 809 as taught by Finch in view of Na. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations, and Willcock enhances the model of Finch in view of Na because the Post-Processing component "can reduce the output bandwidth, which can reduce the number of wires required to extract the output data from the cells." (Willcock: ¶0017)
Finch in view of Na in view of Willcock do not teach:
a plurality of multiply-accumulate (MAC) components that are each configured to generate a MAC output based on the input precision mode,
However, Upadhyay teaches:
a … multiply-accumulate (MAC) component that [is] configured to generate a MAC output (Fig. 13, e.g., shows bitwise MAC unit structure) …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine MAC unit as taught by Upadhyay with Multiplier in the mantissa processor 104 as taught by Finch in view of Na in view of Willcock. One would have been motivated to combine these references because they disclose multiply-accumulate operations, and Upadhyay enhances the model of Finch in view of Na in view of Willcock allowing to perform bitwise multiplication using a simpler architecture.
Regarding Claim 2, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The device of claim 1, further comprising a shift register configured to:
receive the plurality of MAC outputs from the plurality of MAC components (Finch: Fig. 8A, e.g., shows Mantissa PCS stage 122 (shift register) receiving MAC Processor First pipeline stage 150 (MAC) outputs; ¶0090, e.g., PCS 122 performs right shift);
and provide each MAC output, of the plurality of MAC outputs, to the adder component (Finch: Fig. 8A, e.g., PCS processor 122 provides outputs based on MAC Processor First pipeline stage 150 (MAC) to adder trees 806 (adder component)).
Regarding Claim 3, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The device of claim 1, further comprising a coordination mode port configured to receive an indication of a coordination mode that indicates whether the adder component is to sum MAC outputs from every MAC component of the plurality of MAC components (Finch: Fig. 8C, e.g., adders receive mode signal 816 (coordination mode); ¶0101, e.g., mode bit selects operation between first bitwidth and second bitwidth (MAC outputs)).
Regarding Claim 7, Finch in view of Na in view of Willcock in view of Upadhyay teach the device of claim 1. Na further teaches:
wherein the device is configured to:
receive a control signal; and route the adder component output either back to the adder component, as return data, or to the rounding component based on the control signal (Na: Fig. 6(b), e.g., Parallel prefix adder accumulates values based on a state signal (control signal) inputted in a mux).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the adder trees as taught by Finch in view of Na in view of Willcock in view of Upadhyay with the Parallel Prefix Adder accumulating results as taught by Na. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations, and Na enhances the model of Finch in view of Na in view of Willcock in view of Upadhyay by addition operation using one adder, allowing for a smaller circuit scale.
Regarding Claim 8, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The device of claim 1, wherein, to generate the MAC output, the plurality of MAC components are each configured to:
calculate a plurality of products, wherein each product of the plurality of products is generated based on the input precision mode and based on multiplying a map word of the set of map words and a kernel word of the set of kernel words (Finch: Fig. 3, e.g., shows Mantissa processor outputting the result of multiplying input and coefficient mantissas; Upadhyay: Fig. 13, e.g., shows bitwise MAC unit structure (performing a plurality of product operations)); and
generate an accumulation of products, as the MAC output, based on the input precision mode and based on adding the plurality of products (Upadhyay: Fig. 13, e.g., shows bitwise MAC unit structure accumulating products in each iteration).
Regarding claims 9 and 13, they are method claims practiced by the apparatus of claims 1 and 7, respectively. They are rejected for the same reasons as claims 1 and 7.
Regarding Claim 14, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The method of claim 9, wherein the input word length is a same length as the output word length (Na: Fig. 6(b), e.g., FSM controller receives mode signal (through first precision mode port; Fifth page, Section 4.2 Flexible MAC, e.g., mode signal can configure inputs to be 16 or 32 bit inputs); Willcock: ¶0053, e.g., Post-Processing Component 312 can round accumulated values to a lower precisions based on a control signal; ¶0017, e.g., precision can be reduced from 32 bits to 16 bits; word length would be the same if Na’s mode signal and Willcock’s control signal are set for the same precision).
The motivation to combine provided with respect to claims 1 and 9 applies equally to claim 14.
Regarding Claim 15, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The method of claim 9, wherein the input word length is a different length than the output word length (Na: Fig. 6(b), e.g., FSM controller receives mode signal (through first precision mode port; Fifth page, Section 4.2 Flexible MAC, e.g., mode signal can configure inputs to be 16 or 32 bit inputs); Willcock: ¶0053, e.g., Post-Processing Component 312 can round accumulated values to a lower precisions based on a control signal; ¶0017, e.g., precision can be reduced from 32 bits to 16 bits; word length would be different if Na’s mode signal and Willcock’s control signal are set for different precision).
The motivation to combine provided with respect to claims 1 and 9 applies equally to claim 15.
With regards to Claims 16, this claim is a means plus function limitation version of claim 1, wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein.
Regarding Claim 19, Finch in view of Na in view of Willcock in view of Upadhyay teach the apparatus of claim 16. Na further teaches:
means for receiving the plurality of product accumulations; and
means for outputting each product accumulation, of the plurality of product accumulations, across a plurality of clock cycles for generation of the adder component output Na: Fig. 6(b), e.g., Parallel prefix adder accumulates values based on a state signal inputted in a mux, and shows dotted lines (registers) storing values of every computation. Hence, values are accumulated based on clock signals).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the adder trees as taught by Finch in view of Na in view of Willcock in view of Upadhyay with the Parallel Prefix Adder accumulating results as taught by Na. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations, and Na enhances the model of Finch in view of Na in view of Willcock in view of Upadhyay by addition operation using one adder, allowing for a smaller circuit scale.
Regarding Claim 20, Finch in view of Na in view of Willcock in view of Upadhyay teach:
The apparatus of claim 16, further comprising means for concatenating the plurality of product accumulations for storage in a shift register (Finch: Fig. 3, e.g., shows 4 bit outputs being concatenated to form 8/12/16 bit outputs).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, 7, 8-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 17/807,290 in view of Willcock, in view of Finch, and in view of Upadhyay.
Regarding claim 1, claim 1 of reference application teaches all the underlined limitations of the claim as shown in the table below. The bolded limitation “first” merely describes the precision mode port, and the steps recited in the plurality of MACs are recited in the steps that “a plurality of multiply-accumulate (MAC) components that are each configured to”, therefore, the structural components of the multiplier of the reference application is configured to perform “the plurality of MACs” steps recited in the instant claims. Accordingly, the multiplier of the reference application performs the steps of the plurality of MAC components of claim 1 in the instant application. The “a set of map words included in the map data, and a set of kernel words included in the kernel data” merely describes the inputs to the plurality of MAC components. The “data input to the device” limitation in the instant application describes the input data, where in the reference application it is described as “the map data segment and for the kernel data segment”.
17/807,274 (Instant Application)
17/807,290 (reference application)
A device, comprising:
a first precision mode port configured to receive an indication of an input precision mode that indicates a first word length for data input to the device;
a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device;
a first data port configured to receive map data;
a second data port configured to receive kernel data;
a plurality of multiply-accumulate (MAC) components that are each configured to generate a MAC output based on the input precision mode, a set of map words included in the map data, and a set of kernel words included in the kernel data;
an adder component configured to generate an adder component output based on the input precision mode and one or more MAC outputs of a plurality of MAC outputs generated by the plurality of MAC components;
a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output; and
an output port configured to output the rounded output.
1. A device, comprising:
a precision mode port configured to receive an indication of an input precision mode that indicates a word length for the map data segment and for the kernel data segment;
a first data port configured to receive a map data segment;
a second data port configured to receive a kernel data segment;
a multiplier component configured to generate a multiplier component output based on the input precision mode and based on multiplying the map data segment and the kernel data segment;
an adder component configured to generate an adder component output based on the input precision mode and based on the multiplier component output; and
an output port configured to output the adder component output.
4. The device of claim 1, wherein the adder component is configured to:
receive a first MAC output of the plurality of MAC outputs;
receive return data;
add an upper half of the first MAC output and an upper half of the return data to generate a first adder output;
add a lower half of the first MAC output and a lower half of the return data to generate a second adder output and a carry output;
concatenate the first adder output and the second adder output to generate a first concatenated sum;
add the first adder output and the carry output to generate a third adder output;
concatenate the third adder output and the second adder output to generate a second concatenated sum; and
select, based on the input precision mode, the first concatenated sum or the second concatenated sum as the adder component output.
5. The device of claim 1, further comprising:
a first adder configured to
add an upper half of the multiplier component output and an upper half of a return value to generate a first adder output;
a second adder configured to add a lower half of the multiplier component output and a lower half of the return value to generate a second adder output;
one or more components configured to concatenate the first adder output and the second adder output to generate a first concatenated sum;
a third adder configured to add the first adder output and a carry bit, output by the second adder, to generate a third adder output;
one or more components configured to concatenate the third adder output and the second adder output to generate a second concatenated sum; and
a multiplexer configured to select, as the adder component output and based on the input precision mode, one of the first concatenated sum or the second concatenated sum.
7. The device of claim 1, wherein the device is configured to:
receive a control signal; and
route the adder component output either back to the adder component, as return data, or to the rounding component based on the control signal.
7. The device of claim 5, further comprising a demultiplexer configured to:
receive the adder component output;
receive a control signal; and
output, based on the control signal, the adder component output to one of the adder component or the output port.
Claim 1 of the reference application does not explicitly teach the “a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device” or “a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output; and”
However, in the same field of endeavor, Willcock discloses a post processing component configured to perform rounding based on a control signal specifying the precision. Willcock explains “Continuing the previous example, the post-processing component 312 can round accumulated values to a first lower precision format in response to receiving a first control signal, can round accumulated values to a second lower precision format in response to receiving a second control signal, or to not round at all in response to receiving a third control signal. In another example, the post-processing component 312 can perform a given activation function of a set of possible activation functions of the post-processing component 312 based on the control signal.” (Willcock: ¶0053)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the post processing component as taught by Willcock with the device as taught by Ma. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations in a systolic array, and Willcock enhances the model of Ma because the Post-Processing component "can reduce the output bandwidth, which can reduce the number of wires required to extract the output data from the cells." (Willcock: ¶0017)
Therefore, Claim 1 of the reference application as modified in view of Willcock teaches the device of the instant application, including a second precision mode port configured to receive an indication of an output precision mode that indicates a second word length for data output from the device and a rounding component configured to round the adder component output, based on the output precision mode, to generate a rounded output.
Regarding claim 2, Ma in view of Willcock do not teach “a shift register configured to: receive the plurality of MAC outputs from the plurality of MAC components; and provide each MAC output, of the plurality of MAC outputs, to the adder component.” However, in the same field of endeavor, Finch teaches using a pad, complement, shift (PCS) processor to receive multiplication outputs and provide shifted outputs to the adders. See Finch fig. 1A and ¶0090.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the PCS processor as taught by Finch with the device as taught by Ma in view of Willcock. One would have been motivated to combine these references because both references disclose floating point multiply-accumulate operations, and Finch enhances the model of Ma in view of Willcock by aligning mantissa to the exponent difference. See Finch: ¶0011.
Regarding claim 4, every limitation of the instant application is recited in claim 5 of the reference application, as shown in table above, except for “wherein the adder component is configured to: receive a first MAC output of the plurality of MAC outputs; receive return data”. However, as stated above, the steps performed by the plurality of MAC components are taught by the multiplier in the reference application, causing the adder to receive the MAC outputs. Regarding the “receive return data” limitation, this limitation is taught by claim 6 of the reference application, specifically by disclosing “output, based on the control signal, one of the adder component output or the default value to a return port of the adder component”. Return port of the adder component is interpreted to receive return data.
Regarding claim 7, claim 7 of the reference application teaches outputting data from the adder component to the adder component (return data), or to the output port. Combination of Ma in view of Willcock would cause for the post processing component to receive data from the adder component.
Regarding claim 8, the reference application does not explicitly teach the steps of a MAC operation, however, in the same field of endeavor, Upadhyay teaches the structure of a MAC unit performing multiply accumulate operations. It would have been obvious to one ordinarily skilled in the art to combine MAC unit as taught by Upadhyay with the Multiplier in the multiplier as taught by Ma. Both references disclose multiply-accumulate operations, and Upadhyay enhances the model of Ma by allowing to perform bitwise multiplication using a simpler architecture.
Claims 9-20 recite method and means plus function limitations of claims 1-2, 4, 7. They are rejected for the same reasons therein.
Allowable Subject Matter
Claims 4-6, 10-12, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if claim 4, 10-12, and 17-18 rewritten to overcome the 112(b) rejection and double patenting rejection above.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182