DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a truncation component” in claims 1 and 3. Specification figure 8 illustrates a truncation component 808 as a “black box” without sufficient structure to perform the claimed function of truncating. [0153] describes what the truncation component does, but does not describe what it is. Thus, the specification fails to provide sufficient structure to perform the claimed function.
“a rounded output generation component” in claims 1 and 4. Specification figure 8 illustrates a rounded output generation component 806 as a “black box” without sufficient structure to perform the claimed function of generating. [0156] describes what the rounded output generation component does, but does not describe what it is. Thus, the specification fails to provide sufficient structure to perform the claimed function.
“an extension component” in claim 5. The specification fails to provide sufficient structure, material, or acts to perform the claimed function. [0157] merely describes the component 800 generate a sign extension using an extension component. Thus, the specification fails to provide sufficient structure of the extension component.
“a padding component” in claim 6. The specification fails to provide sufficient structure, material, or acts to perform the claimed function. [0157] merely describes the component 800 concatenates padding bits using a padding component. Thus, the specification fails to provide sufficient structure of the padding component.
“the device” in claim 8. Figure 8 [0157] illustrates a device comprises an output port configured to output a rounded output from component 806.
“means for receiving an indication … for a rounded output” in claim 17. Figure 8 illustrates an output precision mode port 802 for receiving output mode indication.
“means for receiving an input value” in claim 17. Figure 8 illustrates a data input port 804 for receiving input data.
“means for truncating the input value … segment value” in claim 17. As described above, figure 8 illustrates a truncation component 808 for truncating as a “black box” without sufficient structure to perform the claimed function.
“means for adding the keep segment value … generate a rounded keep segment value” in claim 17. Figure 8 illustrates an adder component 820 to perform adding.
“means for generating the rounded output … the output precision mode ” in claim 17. As described above, figure 8 illustrates a rounded output generation component 806 for generating the rounded output as a “black box” without sufficient structure to perform the claimed function.
“means for outputting the rounded output based on … the first value” in claim 18. Figure 8 [0157] illustrates an output port 828 to output the rounded output.
“means for generating one of a signed extension … being the second value” in claim 19. As described above, [0157] merely describes an extension or padding component as a “black box” without sufficient structure to perform the claimed function.
“means for outputting the signed extension … or the padded rounded output” in claim 19. As described above, [0157] merely describes an extension or padding component as a “black box” without sufficient structure to perform the claimed function.
“means for receiving an indication of a truncation point … the truncated segment value” in claim 20. Figure 8 [0152] illustrates a truncation point input port 810 for receiving an indication of a truncation point.
“means for truncating the input value comprises means for truncating the input value based on the indication of the truncation point” in claim 20. As described above, figure 8 illustrates a truncation component 808 for truncating as a “black box” without sufficient structure to perform the claimed function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 3-6, 17, 19, and 20 recite “a truncation component”, “a rounded output generation component”, “an extension component”, “a padding component”, and a plurality of means for corresponding to the truncating, generating rounded output, extending, padding, which invoke 112(f) interpretation. However, as explained above in the interpretation section for 112(f), the specification fail to provide sufficient structures for the components to perform the claimed function because the specification merely illustrates and describe the components as “black boxes” without sufficient detail structures.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 3-6, 17, 19, and 20 recite “a truncation component”, “a rounded output generation component”, “an extension component”, “a padding component”, and a plurality of means for corresponding to the truncating, generating rounded output, extending, padding” that invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. As explained above in the interpretation section for 112(f), the specification fail to provide sufficient structures for the components to perform the claimed function because the specification merely illustrates and describe the components as “black boxes” without sufficient detail structures. Thus, the disclosure is devoid of any structure that performs the function in the claim. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a device
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as receive an indication of an output precision mode that indicates a word length for data output; receive an input value; truncate the input value into a keep segment value and a truncate segment value (see at least figure 8 [0153] describes the step of truncating the received input data into keep segment and truncated segment based on the truncation point, thus truncating operation is a mathematical concept of truncating or discarding bit); add the keep segment value and a carry bit of the truncate segment value to generate a rounded keep segment value (see at least figure 8 [0154] describes the step of adding, which is mathematical operation); generate a rounded output based on the rounded keep segment value and the output precision mode, wherein generating the rounded output includes a sign bit of the keep segment value and a first quantity of lower bits of the keep segment value based on the output precision mode being a first value, and wherein generating the rounded output includes the sign bit of the keep segment value and a second quantity of lower bits of the keep segment value based on the output precision mode being a second value (see at least figure 8 [0155] describes the step of generating rounded output based on performing concatenation to combine sign value with a set of value bits, wherein the set of value bits is generated based on the modes, such as 16 bits or 8 bits. Thus, concatenation operation is mathematical operation). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a device comprises a precision mode port, a data input port, a truncation component, an adder component, and a rounded output generation component. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of receiving and processing data. Furthermore, the step of receiving data as recited in the claim is also considered as insignificant extra solution activity because such limitation is mere data gathering. Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer components. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a generic component. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on computer component cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of receiving data is considered to be insignificant extra-solution activity in step 2A, and is determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicates that mere receiving or transmitting data over a network, is well-understood, routing, conventional function when it is claimed in a merely generic manner. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 recites a truncation point input port configured to receive an indication of a truncation point that indicates a quantity of bits to be included in the keep segment value or a quantity of bits to be included in the truncate segment value. The limitation of receiving an indication of a truncation point that indicates a quantity of bits to be included in the keep segment value or a quantity of bits to be included in the truncate segment value cover mathematical calculations, relationship, and/or formula (receiving indication of truncation point to truncate data). Alternatively, the step of receiving data can also be considered as insignificant extra solution activity (e.g., mere data gathering) under step 2A prong two and determined to be well-understood, routine and conventional under step 2B (see MPEP 2106.05(d)(II) section (i) receiving or transmitting data over a network). Furthermore, a truncation point input port is recited at a high level of generality, e.g., computer component performing computer function of receiving value or signal of indication, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 further recites the step to truncate the input value based on the indication of the truncation point. As explained above in claim 1, such limitation of truncation cover mathematical calculations, relationship, and/or formula (performing truncation of data based on truncation point). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 further recites the step to concatenate the sign bit of the keep segment value and the first quantity of lower bits of the keep segment value, to generate the rounded output, based on the output precision mode being the first value, and to concatenate the sign bit of the keep segment value and the second quantity of lower bits of the keep segment value, to generate the rounded output, based on the output precision mode being the second value. Such limitations cover mathematical calculations, relationship, and/or formula (generating rounded output by performing concatenation of bits, which is a mathematical operation). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites an extension component configured to generate a signed extension of the rounded output. Such limitation of generating a signed extension of the rounded output covers mathematical calculations, relationship, and/or formula (performing signed extension of data, which is a mathematical operation). The extension component is recited at a high level of generality, e.g., computer component performing computer function, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites a padding component configured to concatenate padding bits with the rounded output to generate a padded rounded output. Such limitation of concatenate padding bits with the rounded output to generate a padded rounded output covers mathematical calculations, relationship, and/or formula (perform data padding on the rounded output, which is a mathematical operation). The padding component is recited at a high level of generality, e.g., computer component performing computer function, which amounts to no more than mere instructions to apply the judicial exception using computer component. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites an output port configured to output the rounded output, a signed extension of the rounded output, or a padded rounded output. The output port is recited at a high level of generality, e.g., a computer component perform computer function of outputting result, and the step of outputting the rounded output, a signed extension of the rounded output, or a padded rounded output is at most considered as insignificant extra/post solution activity (e.g., mere outputting result) under step 2A prong two and determined to be well-understood, routine, and conventional under step 2B (see MPEP 2106.05(d)(II) section (i), indicates that mere receiving or transmitting data over a network). Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 further recites the device is configured to output a rounding component output, based on the rounded output, that includes a particular quantity of bits regardless of the output precision mode. The device is recited at a high level of generality, e.g., a computer component perform computer function of outputting result, and the step of outputting a rounding component output, based on the rounded output, that includes a particular quantity of bits regardless of the output precision mode, is at most considered as insignificant extra/post solution activity (e.g., mere outputting result) under step 2A prong two and determined to be well-understood, routine, and conventional under step 2B (see MPEP 2106.05(d)(II) section (i), indicates that mere receiving or transmitting data over a network). Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 recites a method claim that would be practiced by the apparatus claim 1. Thus, it is rejected for the same reasons.
Claim 10 further recites outputting the rounded output based on the output precision mode being the first value. Such limitation is at most considered as insignificant extra/post solution activity (e.g., mere outputting result) under step 2A prong two and determined to be well-understood, routine, and conventional under step 2B (see MPEP 2106.05(d)(II) section (i), indicates that mere receiving or transmitting data over a network). Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 11-12 recite method claims having similar limitation as claims 5-7. Thus, they are rejected for the same reasons.
Claim 13 further recites wherein the set of value bits is a quantity of least significant bits included in the keep segment value, Such limitations cover mathematical calculations, relationship, and/or formula (merely describing the set of value bits included in the rounded output values). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 14 further recites wherein the keep segment value includes the sign bit and a set of most significant bits of the input value, and wherein the truncate segment value includes a set of least significant bits of the input value. Such limitations cover mathematical calculations, relationship, and/or formula (describing the keep segment and the truncate segment data of the truncation operation). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 15 further recites wherein the carry bit is a most significant bit of the truncate segment value. Such limitations cover mathematical calculations, relationship, and/or formula (describing the carry bit for the addition operation). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 16 further recites wherein the rounded keep segment value includes the sign bit and a set of non-sign bits, and wherein the set of value bits of the rounded output includes a quantity of bits that is less than or equal to a quantity of bits included in the set of non-sign bits. Such limitations cover mathematical calculations, relationship, and/or formula (describing the bits of the rounded keep segment values generated after the addition operation). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 17 recites an apparatus claim having similar limitation as claim 1. Thus, it is rejected for the same reasons. claim 17 recites a plurality of means for limitations that invoke 112(f) interpretation. However, as explained in the claim interpretation section that such the specification merely recites the components at a high level of generality (see at least figure 8). Thus, such components amount to no more than mere instructions to apply the judicial exception using computer components. Thus, The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 18-20 recite apparatus claims having similar limitations to claims 10-12 and 2-3. Thus, they are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 9-10,13-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hubara - US 10491239 in view of Sirasao - US 10943039.
Regarding claim 1, Hubara teaches a device (Hubara figure 1 illustrates a computational device), comprising: an indication of an output precision mode that indicates a word length for data output from the device (Hubara figure 1 C5L5-9 illustrates that the output size being M [i.e., an indication of an output precision mode that indicates word length for data output);
a data input port configured to receive an input value (Hubara figure 1 illustrates quantization logic 36 having a data input port receives input number [i.e., an input value] from accumulator 34);
a truncation component configured to truncate the input value into a keep segment value and a truncate segment value (Hubara wherein C5L51-54 describes quantization logic 36 and controller 38 are implemented in hardwired digital logic circuits within an integrated chip. Figures 2 and 5 also illustrates the details of quantization logic 36 and C9L5-16 describes the truncation process that truncate the input number 80 [i.e., the input value] into segment 90 [i.e., a keep segment value] and a LSBs 88 define as the quantization remainder [i.e., a truncate segment value]. Thus, the quantization logic would include a truncation component to perform truncation);
an adder component configured to add the keep segment value and a carry bit of the truncate segment value to generate a rounded keep segment value (Hubara C8L21-33 describes implementation of quantization including rounding, wherein the output number is desired to be rounded up or down depending upon the quantization remainder by simply incrementing [i.e., adding] the least significant bit of the extracted bits [i.e., the keep segment value] if the most significant bit of the remainder is 1. Thus, to perform round up, the least significant bit of the extract bits is added to the most significant bit of the remainder [i.e., a carry bit of the truncate segment value]. Also see figure 5 illustrates a rounding block 94 [i.e., an adder component] C9L22-24, perform increment to give out an output value 96 [i.e., a rounded keep segment value]; and
a rounded output generation component configured to generate a rounded output based on the rounded keep segment value and the output precision mode, wherein the rounded output generation component is configured to generate the rounded output to include a sign bit of the keep segment value and a first quantity of lower bits of the keep segment value based on the output precision mode being a first value, and wherein the rounded output generation component is configured to generate the rounded output to include the sign bit of the keep segment value and a second quantity of lower bits of the keep segment value based on the output precision mode being a second value (Hubara figure 1 and 5 illustrates the quantization logic 36 [i.e., a rounded output generation component] that generates an output number 96 [i.e., a rounded output] based on the sign bit and the output value 98 [i.e., the rounded keep segment value] and M bit output [i.e., the output precision mode], wherein the output number 96 includes a sign bit 82 and an output value 98 [i.e., a first quantity of lower bits of the keep segment value] based on M being 8 as provided an example [i.e., a first value]. Thus, when M is some other value [i.e., a second value], then the rounded output would include the sign bit and a second quantity of lower bits corresponding to M).
Hubara does not teach the device comprises a precision mode port receiving an indication.
Sirasao discloses a device comprises a precision mode port for receiving an indication of an output precision mode that indicates a word length for data output from the device (Sirasao figure 6 a circuit 600 [i.e., a device] comprises a quantizer 616 having an input mode port for receiving control data from the control circuit 604, C9L57-64 wherein the control data indicates a MSB to LSB range for data output, which is 8 or 16 bit for Q)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify Hubara to include a port that receive control data at the quantization block as disclosed in Sirasao. This modification would have been obvious because both references disclose concept of data quantization that reduces data output size, wherein Hubara discloses reduces from N to M, and Sirasao is reduces from P to Q. Furthermore, having a control port for controlling number of M allows the quantization block to be programmable to change the value of M, such as 8 or 16 bit as disclosed in Sirasao, which increases the system’s flexibility to adaptively change the number of M based on control signal.
Regarding claim 2, the combined system of Hubara in view of Sirasao teaches the device of claim 1, further comprising a truncation point input port configured to receive an indication of a truncation point that indicates a quantity of bits to be included in the keep segment value or a quantity of bits to be included in the truncate segment value (Hubara figure 1 C5L4-19 illustrates quantization block 36 comprises a port [i.e., a truncation point input port] for receiving quantization factor (QF) from the controller 38. Figure 2 C6L11-28 describes QF = --2 meaning that the least significant bit in the set of bits extracted will be two places to the right of the radix point. Thus, QF corresponds to a truncation point that indicates a quantity of bits (e.g., window 54) to be included in the keep segment or a quantity of bits to be included in the truncated segment value, which is bit outside of the window 54).
Regarding claim 3, the combined system of Hubara in view of Sirasao teaches the device of claim 2, wherein the truncation component is configured to truncate the input value based on the indication of the truncation point (Hubara figure 2 C6L11-28, the truncation is performed on the 32 bit input value [i.e., the input value] according to the quantization factor [i.e., the truncation point]).
Regarding claim 4, the combined system of Hubara in view of Sirasao teaches the device of claim 1, wherein the rounded output generation component is configured to concatenate the sign bit of the keep segment value and the first quantity of lower bits of the keep segment value, to generate the rounded output, based on the output precision mode being the first value, and wherein the rounded output generation component is configured to concatenate the sign bit of the keep segment value and the second quantity of lower bits of the keep segment value, to generate the rounded output, based on the output precision mode being the second value (Hubara figure 1 and 5 illustrates the quantization logic 36 [i.e., a rounded output generation component] concatenates the sign bit 82 with the extracted value 98 [i.e., the sign bit of the keep segment value and the first quantity of lower bits of the keep segment value] to generate the rounded value 96 based on M being 8 [i.e., the output precision mode being the first value]. When M is some other value [i.e., being the second value], then the rounded value 96 is generated based on concatenating the sign bit 82 and the extracted value 98, which is different number of bit [i.e., the sign bit of the keep segment value and the second quantity of lower bits of the keep segment value]).
Regarding claim 7, the combined system of Hubara in view of Sirasao teaches the device of claim 1, further comprising an output port configured to output the rounded output, a signed extension of the rounded output, or a padded rounded output (Hubara figure 1 C9L29-31, describes quantization logic 36 writes an output number 96, comprising sign bit 82 and output value 98, to output memory 42. Thus, further comprises an output port to output the output number 96 to memory).
Claim 9 recites method claims that would be practiced by the apparatus claim 1. Thus, they are rejected for the same reasons.
Regarding claim 10, the combined system of Hubara in view of Sirasao teaches the method of claim 9, further comprising outputting the rounded output based on the output precision mode being the first value (Hubara figures 1 and 5 C5L3-8 describes the output number 96 being output based on the M being 8 [i.e., the output precision mode being the first value).
Regarding claim 13, the combined system of Hubara in view of Sirasao teaches the method of claim 9, wherein the set of value bits is a quantity of least significant bits included in the keep segment value (Hubara figure 2 and 5 illustrates the extracted value [i.e., the set of value bits] is a quantity of bit of least significant bits included in the intermediate value 90 [i.e., the keep segment value]).
Regarding claim 14, the combined system of Hubara in view of Sirasao teaches the method of claim 9, wherein the keep segment value includes the sign bit and a set of most significant bits of the input value, and wherein the truncate segment value includes a set of least significant bits of the input value (Hubara figure 5 illustrates the intermediate value 90 includes the sign bit 82 and a set of extracted value 84 [i.e., a set of most significant bits of the input value], and the quantization remainder or the truncate segment value 88 includes a set of LSB of the input value).
Regarding claim 15, the combined system of Hubara in view of Sirasao the method of claim 9, wherein the carry bit is a most significant bit of the truncate segment value (Hubara C8L21-33 describes rounding up using most significant bit [i.e., the carry bit] of the remainder [i.e., the truncate segment value]).
Regarding claim 16, the combined system of Hubara in view of Sirasao the method of claim 9, wherein the rounded keep segment value includes the sign bit and a set of non-sign bits, and wherein the set of value bits of the rounded output includes a quantity of bits that is less than or equal to a quantity of bits included in the set of non-sign bits (Hubara figure 5 illustrates the output value 96 [i.e., the rounded keep segment value] includes sign bit 82 and value 98 [i.e., a set of non-sign bits], the quantity of bits of the rounded output is equal to the quantity of bits included in the set of non-sign bits).
Claims 17-18 and 20 recites apparatus claim having similar limitation as claims 9-10 and 2-3. Thus, they are rejected for the same reasons.
Claims 5-6, 8, 11-12, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hubara in view of Sirasao as applied to claims 1, 9, and 17 above, and further in view of Simkins - US 20050144211.
Regarding claim 5, the combined system of Hubara in view of Sirasao teaches the device of claim 1, but the combined system of Hubara in view of Sirasao does not teach an extension component configured to generate a signed extension of the rounded output. Simkins discloses an extension component configure to generate a signed extension of data (Simkins figure 17 [0208] describes input buses [i.e., at least one data line] to multiplexing circuit 1721 are less than 48 bits and these input buses are sign extended to 48 bit. Figure 17 illustrates hardware component 1721 that generate a signed extension data, thus a component within figure 17 that performs such sign extension corresponds to an extension component).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the combined system of Hubara in view of Sirasao to include a component to perform signed extension or zero fill to extend the output value 96 to match the output data bus width when the output value 96 having less bits than the output data bus. This modification would have been obvious because both references operate on digital data having a number of bits, wherein Hubara discloses that M bits can be extracted. Therefore; having data width extension component would allow the system to extend the output value 96 in case M is smaller than the output data port size. Thus, performing sign extension or zero filling would generate a correct result at the output port.
Regarding claim 6, the combined system of Hubara in view of Sirasao teaches the device of claim 1, but the combined system of Hubara in view of Sirasao does not teach a padding component configured to concatenate padding bits with the rounded output to generate a padded rounded output. Simkins discloses a padding component configure to concatenate padding bits with data to generate a padded data (Simkins figure 17 [0208] describes input buses [i.e., at least one data line] to multiplexing circuit 1721 are less than 48 bits and these input buses are zero filled [i.e., padding] to 48 bit [i.e., concatenate with data to generate a padded data]. Figure 17 illustrates hardware component 1721 that generate a zero filled data, thus a component within figure 17 that performs such padding corresponds to a padding component).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the combined system of Hubara in view of Sirasao to include a component to perform zero fill to pad the output value 96 to match the output data bus width when the output value 96 having less bits than the output data bus. This modification would have been obvious because both references operate on digital data having a number of bits, wherein Hubara discloses that M bits can be extracted. Therefore; having data width padding component would allow the system to pad the output value 96 in case M is smaller than the output data port size. Thus, performing zero filling would generate a correct result at the output port.
Regarding claim 8, the combined system of Hubara in view of Sirasao teaches the device of claim 1, wherein the device is configured to output a rounding component output, based on the rounded output (Hubara figure 1 illustrates the device configured to output a quantization block output [i.e., a rounding component output] based on the output value 96), but the combined system of Hubara in view of Sirasao does not teach a rounding component output that includes a particular quantity of bits regardless of the output precision mode. However, Simkins discloses a component to output data that includes a particular quantity of bits even though input data having different widths (Simkins figure 17 [0208] describes some of the input buses to multiplexing circuitry 1721 carry less than 48 bits. These input busses are sign extended or zero filled as appropriate to 48 bits. Thus, regardless of input data width, the data are sign extended or zero filled to 48 bit [i.e., a particular quantity of bits]).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention the combined system of Hubara in view of Sirasao to include component to extend data to a desired result data width as disclosed in Simkins. This modification would have been obvious because both references operate on digital data having a number of bits, wherein Hubara discloses that M bits can be extracted. Therefore; having data width extension component would allow the system to extend the output value 96 in case M is smaller than the output data port size. Thus, performing sign extension or zero filling would generate a correct result at the output port.
As modified, the combined system of Hubara in view of Sirasao and Simkins the device is configured to output a rounding component output, based on the rounded output, that includes a particular quantity of bits regardless of the output precision mode (as modified, Hubara figure 1 illustrates device output an output of quantization logic 36 based on output value 96, that includes a particular quantity of bits regardless of M [i.e., the output precision mode]. For example, figure 1 illustrates an example to generate 8 bit width output, if M is less than 8, then the extracted value is less than 8, thus an extension component can perform sign extension or zero padding to extend the result to 8 [i.e., a particular quantity of bits] )
Claims 11-12 recite method claims having limitations that would be practiced by the apparatus claims 5-6. Thus, they are rejected for the same reasons.
Claim 19 recites apparatus having limitations similar to the apparatus claims 5-6. Thus, it is rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Felix – US 20200201602 discloses a converting floating point number to reduce the precision in figure 6, that illustrates component 640 to truncate the mantissa by a predetermined result, which removes the predetermined bits, an adder to add the LSB of the truncated mantissa with the carry bit and generate a lower precision number.
Lee – US 20200218962 [0094] discloses neural network having 32 bit floating point number may be quantized to a neural network having a fixed point of 16 bit, 8 bits or less.
Tinker – US 20190332355 [0007] discloses a simplest method of rounding is to add a 1 bit to the bit just below the least significant bit (“LSB”) of the rounded result, followed by truncating the lower bits. If the bits of the 32-bit number are numbered from 0 to 31, 0 being the LSB and 31 being the most significant bit (“MSB”), adding the fraction ½ is the same as a 1 bit added to bit 15 of the 32-bit number.
Ng – US 5917741 discloses a rounding unit and a rounding determination logic as illustrated in figure 4, wherein the rounding unit includes mode port and data port and a mode selection logic configured to select different precision to be outputted.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182