Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s Amendment filed on 3/31/2026. Claims 1-20 are pending. Claims 1, 6, and 16 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. (US 20200371828 A1), in view of Kundu et al. (US 20210390004 A1), and further in view of Zhang et al. (US 20190124054 A1), hereinafter referred to as Chiou, Kundu, and Zhang, respectively.
Regarding Claim 1, Chiou discloses A server (Fig 1-100; [0004] a physical server), comprising: a processor; a memory (Fig 1-124; [0019] CPU complex comprises the main CPU cores and associated RAM modules of physical server 100); and an offloading card (Fig 1-102; [0017] physical server 100 includes a novel offload card 102) ,
wherein the offloading card comprises (a) a virtualization controller (Fig 1-104; [0017] offload card 102 comprising a SoC 104; Claim 1-SoC is configured to execute, in software, one or more first functions of a hypervisor associated with the one or more VMs)
and (b) a network function accelerator for radio-based applications (Fig 1-106;[0013] by employing an FPGA for accelerating certain hypervisor functions that are amenable to hardware implementation, the offload card can improve the server's efficiency while at the same time maintaining architectural flexibility. For example, if needed, the FPGA can be re-programmed from accelerating one type/class of functions (e.g., networking) to accelerating another type/class of functions (e.g., storage));
wherein the virtualization controller is configured to: communicate with a control plane server to assign one or more networking addresses to be used by the network function accelerator for traffic ([0037] network flow-based forwarding is implemented in hardware on FPGA 106 and a network control plane for determining routes for network flows is implemented in software on SoC 104. In this case, flow table exceptions and rules can be communicated between FPGA 106 and SoC 104 in the form of network packets.; [0046] FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table. Please note that the network control plane running on SoC 104 to determine a flow table comprising network flows corresponds to Applicant’s communicating with a control plane server to assign networking addresses to be used by the NFA for traffic, as it is known in the art that forwarding data packets in accordance with a flow table requires the assignment of networking address. );
and perform one or more configuration tasks pertaining to a compute instance launched at the server and to be executed by the processor ([0010] the SoC of the offload card can run hypervisor functions that require or benefit from the flexibility of a general purpose processor (e.g., networking and storage control plane functions); [0002] a virtualization software layer, known as a hypervisor, that allows for the hosting of virtual machines (VMs). Please note that requiring a general purpose processor corresponds to Applicant’s amended to be executed by the processor.),
including allocation of at least a portion of the memory for use by the compute instance ([0048] guest memory space of the VM); and wherein the memory stores instructions that when executed on the processor:([0018] SoC 104 has its own RAM (random access memory) 110 and flash memory 112; [0031] Regarding (1), SoC 104 can use DRAM module(s) 202 as its working memory for running program code; Claim 7-the SoC is communicatively coupled with one or more volatile memory modules resident on the offload card, the one or more volatile memory modules acting as a working memory from which the SoC can execute the one or more first functions);
Chiou does not explicitly disclose a radio-based application;
radio-based technology stack;
However, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators);
radio-based technology stack ([0655] execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). In at least one embodiment, layer 3 may comprise a radio resource control (RRC) layer. Please note that the protocol stack being executed, where layer 3 may be a radio resource control layer, corresponds to Applicant’s radio-based technology stack.)
Chiou and Kundu are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou to incorporate the teachings of Kundu to modify the server with offload card and wherein the virtualization controller is configured to communicate with a control plane server to assign networking addresses to be used by the network function accelerator for traffic to use the NFA to accelerate the processing of radio-based applications, as described in Kundu.
Chiou-Kundu does not explicitly disclose run a first network function of a layer of a technology stack for a application at the compute instance so that the first network function is executed by the processor; and cause output of the first network function that runs at the compute instance at the processor to be provided via a peripheral interface to the offloading card, wherein the offloading card provides input based at least in part on the output of the first network function to a second network function of another layer of the technology stack lower than the layer for the first network function, wherein the second network function is run at the network function accelerator at the offloading card.
However, Zhang disclose run a first network function of a layer of a technology stack for a application at the compute instance so that the first network function is executed by the processor ([0009] Host 110 can run an application for providing a Web service, security layer protocol stack (TLS/SSL) software, a TCP/IP protocol stack, an expansion card driver, and the like. Please note that the Host 110 running an application for providing a web service or a TCP/IP protocol stack corresponds to Applicant’s first network function of an application at the compute instance so that the first network function is executed by the processor. Additionally, the application being run on the host for providing a web service corresponds to Applicant’s layer of a technology stack, as it is known in the art that applications such as web services are run in an application layer in the technology stack, often the highest layer and above the security layer.);
and cause output of the first network function that runs at the compute instance at the processor to be provided via a peripheral interface to the offloading card, wherein the offloading card provides input based at least in part on the output of the first network function to a second network function of another layer of the technology stack lower than the layer for the first network function, wherein the second network function is run at the network function accelerator at the offloading card ([0096] Host 310 and expansion device 320 are interconnected by external bus 330 and the host bus protocol; [0097] host 310 is used to provide an application and expansion card driver for the web service, and so on. The security layer protocol stack software, TCP/IP protocol stack, as options, can be offload to the acceleration network card […] After the application calls the transport layer security framework (TLS/SSL) interface, the subsequent data paths are fully offload to the TLS/SSL acceleration network card so as to complete the full hardware offload of the security protocol algorithm, the handshake process, and the underlying network protocol stack processing. Please note that the subsequent data paths from the application of host 310 being offload to the acceleration network card corresponds to Applicant’s causing output of the first network function that runs at the compute instance at the processor, i.e., the application of Host 310, to be provided as input, based on the output of the first network function, to a second network function of the application run at the network function accelerator at the offloading card, i.e., at the acceleration network card. This is because the subsequent data paths that are being offload are provided as an input based on the output of the first network function, as they are subsequent to it. Furthermore, the Host 310 and expansion device 320 being interconnected by external bus 330 and the host bus protocol corresponds to providing the output via a peripheral interface from the compute instance running at the processor to the offloading card as input to a second network function, i.e., the subsequent data paths of the processing. Lastly, since the host 310 provides an application for the web service, whereas the security layer protocol stack software, TCP/IP protocol stack can be offload to the acceleration network card, this corresponds to the second network function of another layer of the technology stack being lower than the layer for the first network function, as it is known to one of ordinary skill in the art that the offloaded layers of the protocol stack such as security or TCP/IP are layers that are lower than the layer used for running applications.).
Chiou-Kundu and Zhang are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads related to networking to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou-Kundu to incorporate the teachings of Zhang to modify the server with offload card performing applications to run a first network function of a layer of a technology stack for a application at the compute instance so that the first network function is executed by the processor and cause output of the first network function that runs at the compute instance at the processor to be provided via a peripheral interface to the offloading card, wherein the offloading card provides input based at least in part on the output of the first network function to a second network function of another layer of the technology stack lower than the layer for the first network function, wherein the second network function is run at the network function accelerator at the offloading card, in order to reduce the computational pressure caused by running the network functions on the compute instance, as described in Zhang.
Regarding Claim 2, Chiou-Kundu-Zhang as described in Claim 1, Chiou further discloses: wherein the offloading card comprises a network processing offloader ([0046] With the foregoing offload card architecture in mind, FIG. 4 depicts a flowchart 400 of an example network processing workflow that may be implemented by physical server 100 according to certain embodiments. Flowchart 400 assumes that FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table)
and a networking hardware device to which a network address within a substrate network of a virtualized computing service is assigned ([0048] At block 404, the VM can create a data payload for a network packet to be transmitted to a remote destination and can notify NIC 128 of this. In response, NIC 128 can read the data payload from the guest memory space of the VM (block 406), assemble the data payload into one or more network packets with headers identifying, among other things, the IP address of the VM and the IP address of the intended destination (block 408), and output the network packet out of its egress port connected to network transceiver module 252 of FPGA 106 (block 410)),
and wherein the network processing offloader is configured to: transmit, using the networking hardware device, one or more messages associated with the radio-based application to a destination external to the server from the compute instance ([0049] At blocks 412 and 414, FPGA 106 can receive the network packet and apply its network data plane logic to perform a lookup of the network packet's 5-tuple (source IP address, source port, destination IP address, destination port, protocol) into a flow table. If a matching entry is found in the table (block 416), FPGA 106 can identify the next-hop destination for the network packet in the entry (block 418), update the header of the packet (block 420), and send the packet out of network transceiver module 250 to external network 126 (block 422), thereby ending the workflow).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Regarding Claim 3, Chiou-Kundu-Zhang as described in Claim 1, Kundu further discloses wherein the offloading card ([0089] In at least one embodiment, acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114; [0076] In at least one embodiment, an AAL interface provides a set of functions for various virtualized network function (VNF) and/or containerized or cloud-native network function (CNF) software for offloading certain functions that may be power and/or compute intensive to hardware accelerators)
comprises a first networking hardware device ([0655] In at least one embodiment, processors of application circuitry 5104 may process IP data packets received from an EPC ) and a second networking hardware device ([0658] In at least one embodiment, as discussed above, baseband circuitry 5108 of FIG. 51 may comprise processors 5108A-5108E and a memory 5108G utilized by said processors),
wherein the first networking hardware device is used for transmitting messages to a first set of destinations including a centralized unit (CU) of the radio-based application ([0655] In at least one embodiment, processors of application circuitry 5104 and processors of baseband circuitry 5108 may be used to execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). In at least one embodiment, layer 3 may comprise a radio resource control (RRC) layer),
and wherein the second networking hardware device is used for transmitting messages to a second set of destinations including a radio unit (RU) of the radio-based application ([0658] In at least one embodiment, baseband circuitry 5108 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 5204 (e.g., an interface to send/receive data to/from memory external to baseband circuitry 5108), an application circuitry interface 5206 (e.g., an interface to send/receive data to/from application circuitry 5104 of FIG. 51), an RF circuitry interface 5208 (e.g., an interface to send/receive data to/from RF circuitry 5110 of FIG. 51), a wireless hardware connectivity interface 5210 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 5212 (e.g., an interface to send/receive power or control signals to/from PMC 5106).
Regarding Claim 4, Chiou-Kundu-Zhang as described in Claim 1, Kundu further discloses wherein the offloading card ([0089] In at least one embodiment, acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114; [0076] In at least one embodiment, an AAL interface provides a set of functions for various virtualized network function (VNF) and/or containerized or cloud-native network function (CNF) software for offloading certain functions that may be power and/or compute intensive to hardware accelerators)
comprises another network function accelerator ([0100] In at least one embodiment, hardware accelerator 308 is one or more specialized computer hardware components that process and/or perform various 5G new radio operations. In at least one embodiment, hardware accelerator 308 comprises hardware such as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a systems-on-chip (SoC) and/or variations thereof; [102] In at least one embodiment, there may be one or more hardware accelerators in addition to hardware accelerator 308 that process one or more functions of block 1 310(1) to block N 310(N)),
and wherein the memory stores further instructions that when executed on the processor: cause input to be provided to a third network function executed at the other network function accelerator(Claim 9- The system of claim 8, wherein the instructions to implement the API that at least performs the plurality of 5G new radio operations based at least in part on the API call to perform the plurality of 5G new radio operations and provides the result of performing the plurality of 5G new radio operations to the network interface to be transmitted include instructions that at least: obtain the API call, wherein the API call indicates data to be processed in connection with the plurality of 5G new radio operations; obtain the data to be processed in connection with the plurality of 5G new radio operations; provide the data to one or more hardware accelerators; perform the plurality of 5G new radio operations on the one or more hardware accelerators in connection with the data; and provide the result of performing the plurality of 5G new radio operations on the one or more hardware accelerators from the one or more hardware accelerators to the network interface to be transmitted).
Regarding Claim 5, Chiou-Kundu-Zhang as described in Claim 4, Kundu further discloses wherein the third network function is executed as part of another radio-based application ([0204] In at least one embodiment, an API call indicates one or more workloads to be performed on one or more hardware accelerators. In at least one embodiment, an API call indicates one or more workloads of layer 1 that are to be offloaded to one or more hardware accelerators. In at least one embodiment, an API call indicates a plurality of 5G new radio operations, which can be part of a physical layer pipeline).
Regarding Claim 6, Chiou discloses A computer-implemented method, comprising: performing, by a virtualization controller running at an offloading card of a server (Fig 1-102; [0017] physical server 100 includes a novel offload card 102; Fig 1-104; [0017] offload card 102 comprising a SoC 104; Claim 1-SoC is configured to execute, in software, one or more first functions of a hypervisor associated with the one or more VMs) of a server (Fig 1-100; [0004] a physical server),
one or more configuration tasks pertaining to a first compute instance launched at the server and to be executed by a processor of the server ([0010] the SoC of the offload card can run hypervisor functions that require or benefit from the flexibility of a general purpose processor (e.g., networking and storage control plane functions); [0002] a virtualization software layer, known as a hypervisor, that allows for the hosting of virtual machines (VMs). Please note that requiring a general purpose processor corresponds to Applicant’s amended to be executed by the processor.),
including allocation of at least a portion of memory of the server for use by the first compute instance ([0048] guest memory space of the VM),
wherein the offloading card includes a first network function accelerator for radio-based applications (Fig 1-106;[0013] by employing an FPGA for accelerating certain hypervisor functions that are amenable to hardware implementation, the offload card can improve the server's efficiency while at the same time maintaining architectural flexibility. For example, if needed, the FPGA can be re-programmed from accelerating one type/class of functions (e.g., networking) to accelerating another type/class of functions (e.g., storage));
communicating, by the virtualization controller running at the offloading card, with a control plane server to assign one or more networking addresses to be used by the first network function accelerator for traffic ([0037] network flow-based forwarding is implemented in hardware on FPGA 106 and a network control plane for determining routes for network flows is implemented in software on SoC 104. In this case, flow table exceptions and rules can be communicated between FPGA 106 and SoC 104 in the form of network packets.; [0046] FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table. Please note that the network control plane running on SoC 104 to determine a flow table comprising network flows corresponds to Applicant’s communicating with a control plane server to assign networking addresses to be used by the NFA for traffic, as it is known in the art that forwarding data packets in accordance with a flow table requires the assignment of networking address. );
Chiou does not explicitly disclose a radio-based application;
radio-based technology stack;
However, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators);
radio-based technology stack ([0655] execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). In at least one embodiment, layer 3 may comprise a radio resource control (RRC) layer. Please note that the protocol stack being executed, where layer 3 may be a radio resource control layer, corresponds to Applicant’s radio-based technology stack.)
Chiou and Kundu are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou to incorporate the teachings of Kundu to modify the server with offload card and wherein the virtualization controller is configured to communicate with a control plane server to assign networking addresses to be used by the network function accelerator for traffic to use the NFA to accelerate the processing of radio-based applications, as described in Kundu.
Chiou-Kundu does not explicitly disclose executing a first network function of a layer of a technology stack for the first application at the first compute instance, so that the first network function is executed by the processor; and executing a second network function of another layer of the first technology stack lower than the layer for the first network function at the offloading card, wherein input to the second network function is received via a peripheral interface to the offloading card and is based at least in part on output of the first network function that runs at the first compute instance at the processor.
However, Zhang disclose executing a first network function of a layer of a technology stack for the first application at the first compute instance, so that the first network function is executed by the processor ([0009] Host 110 can run an application for providing a Web service, security layer protocol stack (TLS/SSL) software, a TCP/IP protocol stack, an expansion card driver, and the like. Please note that the Host 110 running an application for providing a web service or a TCP/IP protocol stack corresponds to Applicant’s executing a first network function of a first application at the first compute instance so that the first network function is executed by the processor. Additionally, the application being run on the host for providing a web service corresponds to Applicant’s layer of a technology stack, as it is known in the art that applications such as web services are run in an application layer in the technology stack, often the highest layer and above the security layer.);
and executing a second network function of another layer of the first technology stack lower than the layer for the first network function at the offloading card, wherein input to the second network function is received via a peripheral interface to the offloading card and is based at least in part on output of the first network function that runs at the first compute instance at the processor ([0096] Host 310 and expansion device 320 are interconnected by external bus 330 and the host bus protocol; [0097] host 310 is used to provide an application and expansion card driver for the web service, and so on. The security layer protocol stack software, TCP/IP protocol stack, as options, can be offload to the acceleration network card […] After the application calls the transport layer security framework (TLS/SSL) interface, the subsequent data paths are fully offload to the TLS/SSL acceleration network card so as to complete the full hardware offload of the security protocol algorithm, the handshake process, and the underlying network protocol stack processing. Please note that the subsequent data paths from the application of host 310 being offload to the acceleration network card corresponds to Applicant’s causing output of the first network function that runs at the compute instance at the processor, i.e., the application of Host 310, to be provided as input, based on the output of the first network function, to a second network function of the application run at the network function accelerator at the offloading card, i.e., at the acceleration network card. This is because the subsequent data paths that are being offload are provided as an input based on the output of the first network function, as they are subsequent to it. Furthermore, the Host 310 and expansion device 320 being interconnected by external bus 330 and the host bus protocol corresponds to providing the output via a peripheral interface from the compute instance running at the processor to the offloading card as input to a second network function, i.e., the subsequent data paths of the processing. Lastly, since the host 310 provides an application for the web service, whereas the security layer protocol stack software, TCP/IP protocol stack can be offload to the acceleration network card, this corresponds to the second network function of another layer of the technology stack being executed and lower than the layer for the first network function, as it is known to one of ordinary skill in the art that the offloaded layers of the protocol stack such as security or TCP/IP are layers that are lower than the layer used for running applications.).
Chiou-Kundu and Zhang are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads related to networking to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou-Kundu to incorporate the teachings of Zhang to modify the server with offload card performing applications to execute a first network function of a layer of a technology stack for the first application at the first compute instance, so that the first network function is executed by the processor, and execute a second network function of another layer of the first technology stack lower than the layer for the first network function at the offloading card, wherein input to the second network function is received via a peripheral interface to the offloading card and is based at least in part on output of the first network function that runs at the first compute instance at the processor, in order to reduce the computational pressure caused by running the network functions on the compute instance, as described in Zhang.
Regarding Claim 7, Chiou-Kundu-Zhang as described in Claim 6, Chiou further discloses wherein the offloading card comprises a first networking hardware device ([0046] With the foregoing offload card architecture in mind, FIG. 4 depicts a flowchart 400 of an example network processing workflow that may be implemented by physical server 100 according to certain embodiments. Flowchart 400 assumes that FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table) to which a first network address within a substrate network of a virtualized computing service is assigned ([0048] At block 404, the VM can create a data payload for a network packet to be transmitted to a remote destination and can notify NIC 128 of this. In response, NIC 128 can read the data payload from the guest memory space of the VM (block 406), assemble the data payload into one or more network packets with headers identifying, among other things, the IP address of the VM and the IP address of the intended destination (block 408), and output the network packet out of its egress port connected to network transceiver module 252 of FPGA 106 (block 410)), the computer-implemented method further comprising: transmitting, using the first networking hardware device, one or more messages associated with the first radio-based application to a second compute instance from the first compute instance ([0049] At blocks 412 and 414, FPGA 106 can receive the network packet and apply its network data plane logic to perform a lookup of the network packet's 5-tuple (source IP address, source port, destination IP address, destination port, protocol) into a flow table. If a matching entry is found in the table (block 416), FPGA 106 can identify the next-hop destination for the network packet in the entry (block 418), update the header of the packet (block 420), and send the packet out of network transceiver module 250 to external network 126 (block 422), thereby ending the workflow).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Regarding Claim 8, Chiou-Kundu-Zhang as described in Claim 7, Kundu further discloses wherein the offloading card ([0089] In at least one embodiment, acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114; [0076] In at least one embodiment, an AAL interface provides a set of functions for various virtualized network function (VNF) and/or containerized or cloud-native network function (CNF) software for offloading certain functions that may be power and/or compute intensive to hardware accelerators)
comprises a second networking hardware device ([0658] In at least one embodiment, as discussed above, baseband circuitry 5108 of FIG. 51 may comprise processors 5108A-5108E and a memory 5108G utilized by said processors),
wherein the first networking hardware device ([0655] In at least one embodiment, processors of application circuitry 5104 may process IP data packets received from an EPC )
is used for transmitting messages to a first set of destinations including a centralized unit (CU) of the first radio-based application running at the second compute instance ([0655] In at least one embodiment, processors of application circuitry 5104 and processors of baseband circuitry 5108 may be used to execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). In at least one embodiment, layer 3 may comprise a radio resource control (RRC) layer),
and wherein the second networking hardware device is used for transmitting messages to a second set of destinations including a radio unit (RU) of the first radio-based application ([0658] In at least one embodiment, baseband circuitry 5108 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 5204 (e.g., an interface to send/receive data to/from memory external to baseband circuitry 5108), an application circuitry interface 5206 (e.g., an interface to send/receive data to/from application circuitry 5104 of FIG. 51), an RF circuitry interface 5208 (e.g., an interface to send/receive data to/from RF circuitry 5110 of FIG. 51), a wireless hardware connectivity interface 5210 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 5212 (e.g., an interface to send/receive power or control signals to/from PMC 5106).
Regarding Claim 9, Chiou-Kundu-Zhang as described in Claim 8, Chiou further discloses wherein the second networking hardware device is assigned a second network address within an isolated virtual network of the virtualized computing service ([0037] Ethernet interface 238 allows SoC 104 and FPGA 106 to exchange data in the form of network packets. This is useful for, e.g., hypervisor code that is already written to exchange data via network packets, because such code can be ported for execution on SoC 104 (or implementation on FPGA 106) with relatively few changes. For example, consider a scenario where network flow-based forwarding is implemented in hardware on FPGA 106 and a network control plane for determining routes for network flows is implemented in software on SoC 104. In this case, flow table exceptions and rules can be communicated between FPGA 106 and SoC 104 in the form of network packets; [0050] On the other hand, if a matching entry is not found in the table at block 416 (indicating that this is the first packet in a flow), FPGA 106 can send the network packet to SoC 104 over internal Ethernet interface 238 (block 424)).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Regarding Claim 10, Chiou-Kundu-Zhang as described in Claim 6, Kundu further discloses wherein the offloading card ([0089] In at least one embodiment, acceleration abstraction layer interface 106 provides various interfaces, functions, and processes usable by software such as software of layer 2+ application software 102 to offload certain functions that may be compute and/or power intensive and may be better performed on one or more hardware accelerators, such as hardware accelerator unit 114; [0076] In at least one embodiment, an AAL interface provides a set of functions for various virtualized network function (VNF) and/or containerized or cloud-native network function (CNF) software for offloading certain functions that may be power and/or compute intensive to hardware accelerators)
comprises a second network function accelerator ([0100] In at least one embodiment, hardware accelerator 308 is one or more specialized computer hardware components that process and/or perform various 5G new radio operations. In at least one embodiment, hardware accelerator 308 comprises hardware such as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a systems-on-chip (SoC) and/or variations thereof; [102] In at least one embodiment, there may be one or more hardware accelerators in addition to hardware accelerator 308 that process one or more functions of block 1 310(1) to block N 310(N)),
the computer-implemented method further comprising: executing a third network function at the second network function accelerator (Claim 9- The system of claim 8, wherein the instructions to implement the API that at least performs the plurality of 5G new radio operations based at least in part on the API call to perform the plurality of 5G new radio operations and provides the result of performing the plurality of 5G new radio operations to the network interface to be transmitted include instructions that at least: obtain the API call, wherein the API call indicates data to be processed in connection with the plurality of 5G new radio operations; obtain the data to be processed in connection with the plurality of 5G new radio operations; provide the data to one or more hardware accelerators; perform the plurality of 5G new radio operations on the one or more hardware accelerators in connection with the data; and provide the result of performing the plurality of 5G new radio operations on the one or more hardware accelerators from the one or more hardware accelerators to the network interface to be transmitted).
Regarding Claim 11, Chiou-Kundu-Zhang as described in Claim 10, Kundu further discloses wherein the third network function is executed as part of a second radio-based application ([0204] In at least one embodiment, an API call indicates one or more workloads to be performed on one or more hardware accelerators. In at least one embodiment, an API call indicates one or more workloads of layer 1 that are to be offloaded to one or more hardware accelerators. In at least one embodiment, an API call indicates a plurality of 5G new radio operations, which can be part of a physical layer pipeline).
Regarding Claim 12, Chiou-Kundu-Zhang as described in Claim 6, Kundu further discloses further comprising: presenting a first virtualized representation of the first network function accelerator to the first compute instance, enabling requests for network functions of the first radio-based application to be transmitted from the first compute instance to the first network function accelerator ([0094] In at least one embodiment, VNF/CNF software 204 utilize various functions of AAL interface 206 to perform various functions on hardware accelerator 210. Further information regarding functions of AAL interface 206 can be found in description of FIGS. 5-12. In at least one embodiment, VNF/CNF software 204 utilize an enqueue API function (e.g., FIG. 11) to perform various functions; [0716] In at least one embodiment, VIM 5802 may manage a life cycle of virtual resources with NFVI 5804 (e.g., creation, maintenance, and tear down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, fault and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems );
and presenting a second virtualized representation of the first network function accelerator to a second compute instance launched at the server, enabling requests for network functions of a second radio-based application to be transmitted from the second compute instance to the first network function accelerator ([0138] In at least one embodiment, software executing in connection with layer 2 1302 includes executable code to at least enqueue an uplink task through enqueue API call 1312. In at least one embodiment, enqueue API call 1312 enqueues one or more uplink tasks to be performed part of an uplink PHY pipeline. In at least one embodiment, enqueue API call 1312 enqueues an entire end to end PHY pipeline to be performed. In at least one embodiment, a response to enqueue API call 1312 includes one or more task identifiers of one or more uplink tasks or uplink PHY pipelines).
Regarding Claim 13, Chiou-Kundu-Zhang as described in Claim 6, Chiou further discloses further comprising: updating firmware or software of the first network function accelerator ([0036] For control capabilities, SoC 104 can use PCIe interface 236 (or alternatively a JTAG interface) to manage and update FPGA 106. For example, SoC 104 can validate FPGA configuration images transferred from RAM 110 to FPGA 106 and can update the image on the FPGA or in the FPGA's flash memory 122 using this interface) in response to a message received from a control plane server of a virtualized computing service ([0020] For example, hypervisor functions that benefit from the flexibility of a general purpose processor (or are simply too complex/dynamic to implement in hardware) can be run on SoC 104, which incorporates one or more general purpose processing cores. Examples of such functions include SDN (software-defined networking) control plane functions, which require complex routing computations and need to be updated relatively frequently to support new protocols and features.).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Regarding Claim 14, Chiou-Kundu-Zhang as described in Claim 6, Kundu further discloses wherein the first network function implements at least a portion of one of: (a) a distributed unit (DU) of a radio access network (RAN) ([0164] In at least one embodiment, for downlink, split option 7-2x implements functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU) that implements digital beam forming (BF) and various functions and an O-RU that implements digital BF and various functions in combination with precoding ) or (b) a centralized unit (CU) of a RAN node or (c) a core network of a radio-based technology stack ([0566] FIG. 45 illustrates a network architecture 4500 for a 5G wireless network, in accordance with at least one embodiment. In at least one embodiment, as shown, network architecture 4500 includes a radio access network (RAN) 4504, an evolved packet core (EPC) 4502, which may be referred to as a core network, and a home network 4516 of a UE 4508 attempting to access RAN 4504).
Regarding Claim 15, Chiou-Kundu-Zhang as described in Claim 6, Kundu further discloses wherein the second network function implements an L1 network function of a radio-based technology stack ([0655] In at least one embodiment, processors of application circuitry 5104 and processors of baseband circuitry 5108 may be used to execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers; [0658] In at least one embodiment, baseband circuitry 5108 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 5204 (e.g., an interface to send/receive data to/from memory external to baseband circuitry 5108), an application circuitry interface 5206 (e.g., an interface to send/receive data to/from application circuitry 5104 of FIG. 51), an RF circuitry interface 5208 (e.g., an interface to send/receive data to/from RF circuitry 5110 of FIG. 51), a wireless hardware connectivity interface 5210 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 5212 (e.g., an interface to send/receive power or control signals to/from PMC 5106).
Regarding Claim 16, Chiou discloses: A non-transitory computer-accessible storage medium storing program instructions that when executed on a processor of an offloading card (Fig 1-102; [0017] physical server 100 includes a novel offload card 102; Fig 1-104; [0017] offload card 102 comprising a SoC 104; Claim 1-SoC is configured to execute, in software, one or more first functions of a hypervisor associated with the one or more VMs) of a server (Fig 1-100; [0004] a physical server): perform, by a virtualization controller running at the offloading card of the server, one or more virtualization management tasks pertaining to a compute instance launched at the server and to be executed by a server processor ([0010] the SoC of the offload card can run hypervisor functions that require or benefit from the flexibility of a general purpose processor (e.g., networking and storage control plane functions); [0002] a virtualization software layer, known as a hypervisor, that allows for the hosting of virtual machines (VMs). Please note that requiring a general purpose processor corresponds to Applicant’s to be executed by the processor.),
including allocation of at least a portion of a memory of the server for use by the compute instance ([0048] guest memory space of the VM);
communicate, by the virtualization controller running at the offloading card, with a control plane server to assign one or more networking addresses to be used by a network function accelerator for traffic of a radio-based application, wherein the network function accelerator resides in the offloading card (Fig 1-106;[0013] by employing an FPGA for accelerating certain hypervisor functions that are amenable to hardware implementation, the offload card can improve the server's efficiency while at the same time maintaining architectural flexibility. For example, if needed, the FPGA can be re-programmed from accelerating one type/class of functions (e.g., networking) to accelerating another type/class of functions (e.g., storage); [0037] network flow-based forwarding is implemented in hardware on FPGA 106 and a network control plane for determining routes for network flows is implemented in software on SoC 104. In this case, flow table exceptions and rules can be communicated between FPGA 106 and SoC 104 in the form of network packets.; [0046] FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table. Please note that the network control plane running on SoC 104 to determine a flow table comprising network flows corresponds to Applicant’s communicating with a control plane server to assign networking addresses to be used by the NFA for traffic, as it is known in the art that forwarding data packets in accordance with a flow table requires the assignment of networking address. As the FPGA on the offload card can accelerate networking functions, this corresponds to the NFA residing in the offloading card that uses the networking addresses.);
Chiou does not explicitly disclose a radio-based application;
radio-based technology stack;
However, Kundu discloses a radio-based application([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators);
radio-based technology stack ([0655] execute elements of one or more instances of a protocol stack. In at least one embodiment, processors of baseband circuitry 5108, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of application circuitry 5108 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). In at least one embodiment, layer 3 may comprise a radio resource control (RRC) layer. Please note that the protocol stack being executed, where layer 3 may be a radio resource control layer, corresponds to Applicant’s radio-based technology stack.)
Chiou and Kundu are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou to incorporate the teachings of Kundu to modify the server with offload card and wherein the virtualization controller is configured to communicate with a control plane server to assign networking addresses to be used by the network function accelerator for traffic to use the NFA to accelerate the processing of radio-based applications, as described in Kundu.
Chiou-Kundu does not explicitly disclose obtain, from the compute instance, a request for a second network function of a layer of a technology stock for the application via a peripheral interface to the offloading card, based at least in part on results of the execution of a first network function of first layer of a technology stack by the compute instance at the server processor, wherein the layer of the technology stack is lower than the first layer of the technology stack; and execute the second network function at the network function accelerator incorporated within the offloading card.
However, Zhang disclose obtain, from the compute instance, a request for a second network function of a layer of a technology stock for the application via a peripheral interface to the offloading card, based at least in part on results of the execution of a first network function of first layer of a technology stack by the compute instance at the server processor, ([0009] Host 110 can run an application for providing a Web service, security layer protocol stack (TLS/SSL) software, a TCP/IP protocol stack, an expansion card driver, and the like.; [0096] Host 310 and expansion device 320 are interconnected by external bus 330 and the host bus protocol; [0097] host 310 is used to provide an application and expansion card driver for the web service, and so on. The security layer protocol stack software, TCP/IP protocol stack, as options, can be offload to the acceleration network card […] After the application calls the transport layer security framework (TLS/SSL) interface, the subsequent data paths are fully offload to the TLS/SSL acceleration network card so as to complete the full hardware offload of the security protocol algorithm, the handshake process, and the underlying network protocol stack processing. Please note that the subsequent data paths from the application of host 310 being offload to the acceleration network card corresponds to Applicant’s obtaining a request from the compute instance for a second network function of an application, i.e., at the acceleration network card, based on results of the execution of a first network function by the compute instance at the server processor, i.e., the application of Host 310. This is because the subsequent data paths that are being offload are provided as an input based on the output of the first network function, as they are subsequent to it. Furthermore, the Host 310 and expansion device 320 being interconnected by external bus 330 and the host bus protocol corresponds to obtaining the request via a peripheral interface to the offloading card for a second network function, i.e., the subsequent data paths of the processing. Additionally, please note that the Host 110 running an application for providing a web service or a TCP/IP protocol stack corresponds to Applicant’s first network function executed by the compute instance at the server processor. Lastly, the application being run on the host for providing a web service corresponds to Applicant’s layer of a technology stack, as it is known in the art that applications such as web services are run in an application layer in the technology stack, often the highest layer and above the security layer.);
wherein the layer of the technology stack is lower than the first layer of the technology stack , and execute the second network function at a network function accelerator incorporated within the offloading card ([0097] host 310 is used to provide an application and expansion card driver for the web service, and so on. The security layer protocol stack software, TCP/IP protocol stack, as options, can be offload to the acceleration network card […] After the application calls the transport layer security framework (TLS/SSL) interface, the subsequent data paths are fully offload to the TLS/SSL acceleration network card so as to complete the full hardware offload of the security protocol algorithm, the handshake process, and the underlying network protocol stack processing.; [0099] Expansion device 320 (that is, TLS/SSL full offloading hardware acceleration network card) includes related protocol offload (TCP/IP protocol stack, TLS/SSL protocol layer and corresponding offload control), TLS/SSL algorithm hardware acceleration module. Please note that the subsequent data paths from the application of host 310 being offload to the acceleration network card corresponds to Applicant’s causing output of the first network function that runs at the compute instance at the processor, i.e., the application of Host 310, to be provided as input, based on the output of the first network function, to a second network function of the application run at the network function accelerator at the offloading card, i.e., at the acceleration network card. Lastly, since the host 310 provides an application for the web service, whereas the security layer protocol stack software, TCP/IP protocol stack can be offload to the acceleration network card, this corresponds to the second network function of another layer of the technology stack being executed and lower than the layer for the first network function, as it is known to one of ordinary skill in the art that the offloaded layers of the protocol stack such as security or TCP/IP are layers that are lower than the layer used for running applications.).
Chiou-Kundu and Zhang are both considered to be analogous to the claimed invention because they are in the same field of offloading computer workloads related to networking to accelerators. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chiou-Kundu to incorporate the teachings of Zhang to modify the server with offload card performing applications obtain, from the compute instance, a request for a second network function of a layer of a technology stock for the application via a peripheral interface to the offloading card, based at least in part on results of the execution of a first network function of first layer of a technology stack by the compute instance at the server processor, wherein the layer of the technology stack is lower than the first layer of the technology stack, and execute the second network function at a network function accelerator incorporated within the offloading card, in order to reduce the computational pressure caused by running the network functions on the compute instance, as described in Zhang.
Regarding Claim 17, Chiou-Kundu-Zhang as described in Claim 16, Chiou further discloses wherein the offloading card is linked to a processor of the server via a peripheral interface ([0017] In the embodiment shown, offload card 102 is implemented as a PCIe (Peripheral Component Interface Express)-based expansion card and thus interfaces with the mainboard of physical server 100 via a standard PCIe x16 3.0 edge connector interface 108. In other embodiments, offload card 102 may be implemented using any other type of peripheral interface).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Regarding Claim 18, Chiou-Kundu-Zhang as described in Claim 16, Chiou further discloses storing further program instructions that when executed on the processor of the offloading card: obtain, from another compute instance, a request for a second network function ([0043] Conversely, FPGA 106 can receive incoming network packets from external network 126 via module 250, process/transform them appropriately, and send them to NIC 128 via module 252 (at which point they can be communicated to the correct destination VM) );
and execute the second network function at the network function accelerator ([0043] Regarding (4), network transceiver module 250 enables FPGA 106 to receive incoming network traffic from and transmit outgoing network traffic to external network 126. Further, network transceiver module 252 enables FPGA 106 to exchange network traffic with NIC 128. This is useful in scenarios where FPGA 106 implements network plane functions because FPGA 106 can receive outgoing network packets from NIC 128 via module 252, process/transform them appropriately, and send them out to external network 126 via module 250)).
Regarding Claim 19, Chiou-Kundu-Zhang as described in Claim 16, Kundu further discloses wherein the first network function implements at least a portion of one of: (a) a distributed unit (DU) of a radio access network (RAN) node ([0164] In at least one embodiment, for downlink, split option 7-2x implements functions up to resource element mapping in a O-RAN distributed unit (O-DU) and supports both an O-RAN radio unit (O-RU) that implements digital beam forming (BF) and various functions and an O-RU that implements digital BF and various functions in combination with precoding ), (b) a centralized unit (CU) of a RAN node, or (c) a core network of a radio-based technology stack ([0566] FIG. 45 illustrates a network architecture 4500 for a 5G wireless network, in accordance with at least one embodiment. In at least one embodiment, as shown, network architecture 4500 includes a radio access network (RAN) 4504, an evolved packet core (EPC) 4502, which may be referred to as a core network, and a home network 4516 of a UE 4508 attempting to access RAN 4504).
Regarding Claim 20, Chiou-Kundu-Zhang as described in Claim 16, Chiou further discloses wherein the offloading card comprises a first networking hardware device ([0046] With the foregoing offload card architecture in mind, FIG. 4 depicts a flowchart 400 of an example network processing workflow that may be implemented by physical server 100 according to certain embodiments. Flowchart 400 assumes that FPGA 106 of offload card 106 is configured to maintain a flow table comprising network flows determined by a network control plane running on SoC 104 and to forward data packets in accordance with the flow table), the non-transitory computer-accessible storage medium storing further program instructions that when executed on the processor of the offloading card: transmit, using the first networking hardware device, one or more messages associated with the radio-based application to a destination external to the server. ([0049] At blocks 412 and 414, FPGA 106 can receive the network packet and apply its network data plane logic to perform a lookup of the network packet's 5-tuple (source IP address, source port, destination IP address, destination port, protocol) into a flow table. If a matching entry is found in the table (block 416), FPGA 106 can identify the next-hop destination for the network packet in the entry (block 418), update the header of the packet (block 420), and send the packet out of network transceiver module 250 to external network 126 (block 422), thereby ending the workflow).
Additionally, Kundu discloses a radio-based application ([0087] In at least one embodiment, hardware accelerator unit 114 is one or more specialized computer hardware components that process and/or perform various workloads, such as 5th generation new radio operations.; [0340] In at least one embodiment, one or more systems depicted in FIG. 23 are utilized to implement an API that provides software with functionalities to perform one or more fifth generation new radio operations on one or more hardware accelerators).
Response to Arguments
Applicant's arguments filed 03/31/2026, with respect to rejections of Claims 1-20 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Applicant’s arguments are summarized as the following:
Regarding amended Independent Claim 1, the cited references do not teach the limitations of the amended Claim. The combination of references does not teach an offloading card comprising a virtualization controller and NFA as cited in the Applicant’s claim. Additionally, the virtualization controller performs multiple functionalities-in addition to performing configuration tasks including memory allocation for the compute instance, it also communicates with a control plane server to assign networking addresses to be used by the NFA. Chiou discloses a hypervisor as the only function running on the offloading card, and Kundu only discusses running the network accelerator as the only function of the offloading card. The Zhang reference discloses using the offloading card to run only TLS/SSL protocol-related encryption and decryption algorithms instead of running on the server CPU. In all the cited references, the offloading card is specialized for only one purpose, and not for running both the virtualization controller and NFA on the offloading card.
The combination of references additionally does not teach running a first network function of a layer of a radio-based technology stack for a radio-based application at the compute instance and the second network function of another layer of the radio-based technology stack lower than the layer of the first network function, wherein the second network function is running at the NFA of the offloading card. This is because Chiou performs all the network functions on the CPU complex, Kundu performs all the network functions on the network accelerator, and Zhang has all the network functions, TLS/SSL, and TCP/IP running on the offloading card, none of which teach the hybrid architecture.
Therefore, none of the references, regardless of how combined, teach Applicant’s claim, and the rejections under 35 U.S.C. 103 should be withdrawn.
Amended independent claims 6 and 16 are submitted as patentable over the cited references for at least reasons similar to those provided above for Claim 1.
Numerous ones of the dependent claims recite further distinctions over the cited references and Applicant traverses their rejections under 35 U.S.C. 103 for at least the reasons given above regarding the claims from which they depend.
The examiner respectfully disagrees.
Regarding A), as stated above, the system of references teaches the amended limitations regarding the offloading card comprising a virtualization controller and NFA, as Chiou discloses an offload card comprising both a SoC 104 that executes functions of a hypervisor associated with VMs, corresponding to the virtualization controller, as well as a FPGA 106 that accelerates network functions, corresponding to the NFA, as stated in [0013] and [0017]. Furthermore, the network control plane running on SoC 104 to determine a flow table comprising network flows corresponds to Applicant’s communicating with a control plane server to assign networking addresses to be used by the NFA for traffic, as it is known in the art that forwarding data packets in accordance with a flow table requires the assignment of networking address.
Additionally, as described above by Zhang, the application being run on the host for providing a web service corresponds to Applicant’s layer of a technology stack, as it is known in the art that applications such as web services are run in an application layer in the technology stack, often the highest layer and above the security layer. As further stated in [0096], since the host 310 provides an application for the web service, whereas the security layer protocol stack software, TCP/IP protocol stack can be offload to the acceleration network card, this corresponds to the second network function of another layer of the technology stack being lower than the layer for the first network function, as it is known to one of ordinary skill in the art that the offloaded layers of the protocol stack such as security or TCP/IP are layers that are lower than the layer used for running applications. Thus, the hybrid architecture is taught by the system of references, as Kundu further discloses radio-based applications and technology stacks.
Therefore, the recited features can be found in the combination of references, amended Independent Claim 1 remains rejected under 35 U.S.C. 103 for the reasons stated above, and the combinations would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the application.
Regarding B), contrary to Applicant’ arguments, because the independent Claims 6 and 16 contain similar limitations to rejected Claim 1 and do not add limitations that overcome the rejection, they likewise remain rejected. Therefore, the recited features can be found in the combination of references, amended Independent Claims 6 and 16 remain rejected under 35 U.S.C. 103 for the reasons stated above, and the combinations would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the application.
Regarding C), independent claims 6 and 16 remain rejected for the reasons stated above, as independent Claim 1 remains rejected. Thus, contrary to Applicant’s arguments, because the dependent claims depend from unpatentable independent claims and do not add limitations that overcome the rejection, they likewise remain rejected.
Therefore, the rejections under 35 U.S.C. 103 are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pong (US 20060274788 A1) discloses an SOC for network application acceleration, offloading data processing for network protocols to a chip from a host processor to reduce implementation cost, using a bus conducive to offloading, and passing a block processed by the application to the offload engine for subsequent processing (see [0004, 0019, 0021, 0028]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARAZ T AKBARI whose telephone number is (571)272-4166. The examiner can normally be reached Monday-Thursday 9:30am-7:30pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FARAZ T AKBARI/ Examiner, Art Unit 2196
/APRIL Y BLAIR/ Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights